File was using stdint.h defined types without including and caused a
build error depending on include ordering.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Some configurations have the system timer driver hardwired in.
Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Do not select CONFIG_CACHE_MANAGEMENT in the Microchip SAM CAN driver
Kconfig but rather leave it up to the SoC/platform Kconfig to enable it as
needed and enable CACHE_MANAGEMENT by default for the Atmel SAM E70/V71 SoC
series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Currently on zephyr, RAIL is used only for bluetooth. RAIL library is
needed to use efr32 radio regardless of the protocol used. We add
SOC_GECKO_USE_RAIL kconfig option to indicate if we use radio.
FPU is needed when using RAIL, we configure it if SOC_GECKO_USE_RAIL
is set.
Signed-off-by: Antoine Bout <antoine.bout@silabs.com>
Add an option to control whether or not hpsram banks should
be switched off during the power down. This is particular useful
when running tests because we don't want to lose the contents
of the memory window before we capture it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Pinmuxing is now done by a pinctrl driver, not by board.c,
so the code used previously for pinmuxing can be removed.
Fixes#59186.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
CC13/26xx's pinctrl_cc13xx_cc26xx.c driver included ioc.h and
(indirectly) pinctrl_soc.h which contained duplicate defines.
This change removes the header conflict and redundant definitions.
This prepares for subsequent changes in this change set that add
additional flags to the pinctrl driver which would otherwise trigger the
header conflict.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some EFR32 build broke after 3d2194f11e with:
pm.c:152: undefined reference to `pm_state_exit_post_ops'
Add an extra empty function to make this one build again.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
The Keystone 3 (K3) family encompasses a wider variety of SoC's.
This aligns the soc/arm64 naming with the soc/arm directory.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The PM hooks were guarded with CONFIG_PM_POLICY_CUSTOM, however, they
need to be guarded (if file is always compiled) with CONFIG_PM. In fact,
CONFIG_PM_POLICY_CUSTOM requires to implement a custom policy hook,
something this module did not provide.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The clock rates for ACE series of Intel Audio DSP have changed.
The values come from the SOF project in their board configs.
CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test
can pass.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Updated the clock init to reflect the sdk also
updated the clock frequencies to reflect the
respective soc clock values, this file originally
contained unexpected clock values, updated comments
to reflect changes and got rid of doxygen style
comments
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes
toolchain only. Andes toolchain will replaces suitable 32-bit instructions
with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a
corresponding 32-bit instruction in look up table.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream.
This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Refine PMA driver and define MPU_ALIGN() to PMA granularity in
RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround
kernel object address may be 0x0 in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").
This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:
set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).
Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.
Add only needed driver strength and bias pins to PFC,
e.g. SDx and UART TX/RX pins.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.
Note: some of files copy-pasted from Renesas Arm 32
SoC directory and this commit is a temporary
solution, we need to rework it in order to use
the same source files for both architectures.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.
The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some boards has ESP_SPIRAM enabled by default, which is
causing issues when MCUboot is used as 2nd bootloader.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This fixes the following build error:
```
zephyr/zephyr.elf', needed by 'zephyr/zephyr.ri', missing and no known
rule to make it
```
This appears when CONFIG_KERNEL_BIN_NAME is used.
Therefore, do not use zephyr.elf since some samples might be called
based on CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.
This commit inserts additional `nop` instruction after waking up
to delay access to the memory.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.
Use the board's debug connector (P6 / LPUART2) as default console.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Unify the pinctrl_soc.h header for all the NXP S32 family by using
the HAL macros that expose the features supported on specific
devices. This approach still need a different binding for each device to
expose in DT different properties and allowed values.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce minimal power initialization for NXP S32 SoCs and allow to
reset the SoC through the sys_reboot() API.
Presently only S32K3 SoCs is supported but it can be extended later to
other NXP S32 SoCs, hence it's placed in a common directory.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This patch sets ENET2 ref clock to be generated by External OSC
ENET2 ref clock direction as output
ENET2 ref clk frequency to 50MHz
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.
Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.
Signed-off-by: Keith Packard <keithp@keithp.com>
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The ifdefs in in dmic headers is getting out of control and makes
maintainence very ddifficult, especially when having to maintain out of
tree SoCs sharing the same data and information.
Keep header clean and per SoC and share some common registers in one
place instead avoiding confusion and making it easier to read and
maintain.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Where the bottom is the only one which interacts with
the host operating system.
And the top the only one that interacts or is aware
of the hosted operating system (Zephyr).
The bottom uses the native simulator CPU
start/stop emulation.
By now we replicate its code as a provisional measure,
until the native simulator becomes standard.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Where the bottom is the only one which interacts with
the host operating system, and does not necessarily
need to know about the Zephyr OS.
This is in preparation for the native simulator,
which which the bottom is also fully Zephy agnostic.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
A known issue exists that does not allow a CC13/26x2R device to
establish a link to a CC13/26x2P device unless the capacitor array is
tuned to a non-default value in the P device.
See SimpleLink(TM) cc13xx_cc26xx SDK 6.20+ Release Notes, Known Issues.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
The native_tasks logic is unrelated to the remaining
of the soc logic (which handles CPU start/stopping)
refactor it out into its own file.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Let's remove the native_posix part from the SOC description
and just refer to "native".
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The native_tasks header requires the toolchain header.
Let's include it directly instead of requiring users
of this header to include it before.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
When CONFIG_PM_DEVICE is enabled IPC Device may be during power transition
during a call to intel_adsp_ipc_send_message function.
Changed signatures of intel_adsp_ipc_send_message and its sync version
to return int and negative error codes on error.
On attempt to send IPC message during Device power transition
-ESHUTDOWN error code is returned, on busy state -EBUSY.
Updated all function references.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
When option CONFIG_PM_DEVICE is enabled, IPC driver is capable
of entering D3 power state described as PM_DEVICE_ACTION_SUSPEND
(and leaving that state - powering back to PM_DEVICE_ACTION_ACTIVE).
New power control callbacks 'ipc_power_control_api' are introduced for
use during power state transisions. They allow Zephyr application
specific code to be executed.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Provides a way to use pinctrl to allow internal loopback
on a peripheral pin for testing purposes.
This is done by using output-enable on a input pin and
input-enable on a output pin.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
All Cortex-M processors can support RTT by default. This change enables
RTT support for the cc13xx/cc26xx SoC series (tested in hardware on
CC1352R).
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Added a new function to check whether a clock source is supported by a
platform and to retrieve its frequency.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Disable RT boot header for CM4 core. This will ensure the boot header is
not present when building an application targeting RAM on the CM4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Zephyr currently only supports CLINT direct mode and CLINT vectored
mode. Add support for CLIC vectored mode as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add support for INTEL FPGA Nios V/g RISC-V based Processors.
Also amended SOC_NIOSV_M to use ATOMIC_OPERATIONS_BUILTIN.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Amount of memory banks should vary depending on platform, otherwise
power down sequence might result in ipc timeout as the memory used by
the ipc itself is shutdown.
Lift the needed defines from sram.c to adsp_memory.h and shorten the
names to avoid collision with sof code. No functional change to sram.c.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
It doesn't make sense to select this option at SoC level. This feature
is meant for subsystems/modules that need device handles to be
modifiable at runtime.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The field offset is incorrect, L1EXP is at bit 24 and L1ETP at bit 25.
Fixes: cc6e9c094a ("soc/intel_adsp: Low level HDA driver and tests")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
The Nordic board are selecting CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT by
default and rely on some HAL code to implement a cycle accurate busy
delay loop.
This is in general fine for real hardware but when QEMU and emulation is
taken into account, a cycle accurate busy wait implementation based on
delay in executing machine code can be misleading.
Let's take for example qemu_cortex_m0 (that is based on the nRF51
chipset) and this code:
uint32_t before, after;
while (1) {
before = k_cycle_get_32();
k_busy_wait(1000 * 1000);
after = k_cycle_get_32();
printk("diff cycles: %d\n", after - before);
}
With CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 this diff cycles should
be always around 1000000, in reality when executed with:
qemu-system-arm -cpu cortex-m0 -machine microbit -nographic
-kernel build/zephyr/zephyr.elf
This results in something like this:
diff cycles: 22285
diff cycles: 24339
diff cycles: 21483
diff cycles: 21063
diff cycles: 21116
diff cycles: 19633
This is possibly due to the fact that the cycle accurate delay busy loop
is too fast in emulation.
When dealing with QEMU let's use the reliable busy loop implementation
based on k_cycle_get_32() instead.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
As a result of the 11a2107d991b("riscv: timer: driver revamp") commit,
gd32vf103 no longer works properly.
In the
c9c04e491e0f("soc: riscv: Add initial support for GigaDevice GD32V SoC")
that is the first commit of implementation of this SoC,
set the CPU frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
and riscv_machine_timer divide the clock with the value of
CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.
The CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should set the timer's clock,
so I fixed to set the config as 27MHz in this PR. Also, remove the
unnecessary CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER setting.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Updated the flash segment alignment on S3,
so that mapping corresponds with the linkage.
Fixed hard-coded flash size for ESP32.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub
RX/TX registers needs to be explicitly enabled before use.
The logic follow hardware initialization done in
SOF project sof/src/platform/intel/cavs/platform.c
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
1. Add support for the USB Full Speed controller
2. Add a Kconfig to specify if a dedicated USB
RAM is available in the SoC.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add FLEXSPI1 and FLEXSPI2 memory sections for RT5xx SOC. These sections
can be used by the user's application as part of a custom linker script,
if the application needs to relocate a buffer to external SRAM connected
to FLEXSPI1 or FLEXSPI2
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds watchdog reset as a reset source at SoC init. This is achieved by:
1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
1. Fixes the number of interrupts in OpenTitan by default. This should
be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
including interrupt 0.
2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
PLIC interrupt on IRQ 11.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The SoCs/Boards using those headers were dropped, so remove those
remaining headers that were forgotten.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commits selects the `CONFIG_SOC_GECKO_SE` option for the BG27 SoC
series. This is required for BLE support, as it enables the inclusion of
the `sl_protocol_crypto` component from SiLabs HAL.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Internal bootloader will only run application image if valid product
header is present on flash. This means product header is required for
application that are not linked to code partition. Other applications
that are linked to code partition are meant to be run by MCUboot and
should not touch product header, with the exception of MCUboot itself
which is also run by internal bootloader so requires product header.
Default flash load offset for applications not linked to code partition
is set to 0x2400 as this is where internal bootloader looks for an
application image to run based on product header written by flasher.
Flash load offset for MCUboot is set from boot partition.
Valid product header is added by ezFlashCLI when using "flash_image"
command.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Applications that are run from MCUboot should reconfigure cache to
ensure they run from cached ared on flash. Initial cache configuration
is done by internal bootloader and is valid for MCUboot only.
Cache is configured once at boot, then new configuration is applied by
triggering SW reset.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Initialize threadptr with 0 during the boot before it possibly be used
since the architectural reset state is undefined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
sl_power_manager can only be used if HAL services infrastructure
is enabled, and that is controlled by SOC_GECKO_DEV_INIT kconfig option.
Therefore, SOC_GECKO_PM_BACKEND_PMGR may not be enabled without
SOC_GECKO_DEV_INIT.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Using EM2 or deeper sleep states (where HF clocks are off) requires
special care if BLE radio is used, since BLE radio relies on that clock,
and its power/clock requirements need to be taken into account
On SiLabs, radio PM is implemented as part of RAIL blob, which relies
on sl_power_manager HAL service. I've implemented SoC PM
state changes using sl_power_manager instead of emlib, and added
call to RAIL PM initialization in Gecko HCI driver.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This patch modifies intel_adsp_ipc_is_complete function so it don't
report that IPC is completed when we are still waiting for ACK from
HOST.
This change will allow to solve the problem that occurs during the power
state transitions. Occasionally, the Application decides to enter the
power gating state after sending an IPC message, before receiving an ACK
from the HOST. This results in broken IPC communication when coming back
to Idle state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Thanks to PR [1] which introduces support for cache management
operations on xtensa architecture NXP SoCs can now use the
Zephyr native cache management API.
This commit enables some configurations that will allow us
to use the native Zephyr cache management API.
[1]: https://github.com/zephyrproject-rtos/zephyr/pull/50136
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The end of the heap should be the same as _heap_sentry. The current end
marker just covers the range of memory that is explicitly put in
.heap_memand not account until the end of L2_SRAM_BASE +
L2_SRAM_SIZE memory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
1. Enable os_timer as a wakeup-source in the board
dts file.
2. Enable PM_DEVICE when PM is enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The macro HW_STATE_CHECK_DELAY represents the number of usec to
busy-wait when waiting for a h/w register state change. This value
has been lowered by 75% to correct a couple of issues related
to Power Management (PM).
1. This resolves a kernel.timer.tickless test failure (see
tests/kernel/timer/timer_api) on the LNL simulator where the test
was taking too long to wake after sleeping for 50 ticks. This
was tracked down to the xtensa SOC power management code where
it was performing a busy wait of 256 usec, which was equivalent
to 2.56 ticks.
2. Furthermore, this delay of 256 usec contradicted the information
in the DTSI (see power-states for d0i3) which states that the
"exit-latency-us" is 100 usec. Reducing this value to 64 helps to
keep that in line.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This aligns `soc/xtensa/nxp_adsp/` with commit
fad2da39aa ("intel_adsp: move `west sign` from `west flash` to earlier
`west build`")
The --if-tool-available option preserves backwards-compatibility:
nothing happens if rimage is not found.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Added logging declaration to soc.c of stm32wl, which resolves build
errors when using this SOC with DEBUG logging level
Fixes: #57655
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
(resubmitting after it has been reverted by 0f2a352cbd ('Revert
"xtensa: remove ELF section address rewriting"')
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
board:
- update device tree to use flexcomm devices to the chip design
- enable clocks (soc init file)
- setup connections for loopback test in system controller (board init
file)
tests:
- update board files (overlay, conf)
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The Mi-V implements the A extension therefore it shouldn't use the C
version. The built-in version generates code with proper machine
opcodes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.
So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.
Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"
For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig
The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Rename soc to mimx8ml8 to link this board to the
MIMX8ML8 device from nxp_hal/mcux/mcux-sdk/.
We need this in order to use the drivers from mcux-sdk.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Improve the radio off code, mainly:
- Compile the file only if necessary, ie, LORA radio not in use
- Use pin information from DT, so that we do not need to hardcode pins
and can switch to dt-spec APIs.
- Improve error handling, includes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Ensure code cache is enabled at boot for RT11xx. CMSIS SystemInit should
enable the code cache, but if CONFIG_INIT_ARCH_HW_AT_BOOT=y and
CONFIG_CACHE_MANAGEMENT=y, then the cache will be disabled after
SystemInit is called. Since calling SCB_EnableICache will not
change hardware settings if the ICACHE is already enabled, just
call it unconditionally during init.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Do not use XTENSA_HAL when building with xt-clang, instead use the HAL
that is provided by the toolchain, similarly to xt-xcc.
Signed-off-by: Paul Olaru <paul.olaru@nxp.com>
Clearing of shared memory by one side of the communication
is no longer required after
commit 0620cb1fe1
("ipc: ipc_service: icmsg: Increase reliability of bonding")
was merged.
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Build of Intel cAVS2.5 platforms fails due to undefined reference
sys_cache_data_flush_and_invd_all(). Fix this by adding missing
header include to bring in the inline definition for this function.
Fixes: 6388f5f106 ("xtensa: use sys_cache API instead of custom interfaces")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Move additional cache code related to architecture support into arch.h
and leave cache.h with cache API implementation.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Disable the hardware I2C target detection on the IT82xx2 SoC family.
Note: The register setting of I2C target detection is different in
IT81XX2 and IT82XX2 SOC.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
It is enabled by default if Device Tree includes a flash controller,
and disabled otherwise. SoC defconfig should not touch it.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The mps3 soc is missing PMU defines required for CMSIS. This
adds the defines __PMU_PRESENT and __PMU_NUM_EVENTCNT
enabling the api for the PMU.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Move STM32H7_DUAL_CORE to
soc/arm/st_stm32/stm32h7/Kconfig.soc
add select STM32H7_DUAL_CORE for SOC_STM32H745XX/H747XX
Cleanup old occurences where was set to y
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This new Kconfig option lets the developer configure if the Cortex M4
core should be force-booted during M7 init independent of the BCM4
option byte.
This allows to disable this default behaviour via Kconfig which was not
possible so far.
Signed-off-by: Jan Krautmacher <jan@krautmacher.org>
Deprecates setting GPREGRET to the reset reason as this has been
replaced with the boot mode retention subsystem for nRF51/nRF52.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Secure Element's mailbox is needed for entropy gathering purposes.
Enable it in the EFR32MG24 SoC series Kconfig.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
use helper macros from csr.h instead of inline assembly which results
in cleaner and more maintainable code
Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
To enable IMR on LNL platform new header added to
support context save/restore must be added also to LNL.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit adds the SiLabs Bluetooth HCI driver. It also enables this
BLE HCI driver on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This prevents configuration errors if a board is configured when
the SoC indicates segger RTT support but the segger module is
not available.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds some structs for interrupt stack frames to make it
easier to access individual elements, and ultimately getting
rid of magic array element numbers in the code. Hopefully,
this would aid in debugging where you can view the whole
struct in debugger.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Introduce config for all ESP32 chips which
may be using different architectures but
shares common peripherals and features.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This commit adds a missing `__weak` symbol to the `pm_policy_next_state`
function.
This is needed for e.g. `tests/kernel/profiling/profiling_api` to build
correctly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit creates identity mappings for all memory regions required
by SOF. This is needed because drivers using these memory regions have
not yet been ported to Zephyr.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since SOF uses some extra sections we need to add them to the linker
script. The used linker script is simply a copy of arm64 linker script
with SOF regions included. This is because conditionally adding sections
to the main arm64 linker script is not really desirable.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
1. Increase sram to 256KB.
A block sram of SCAR0~15 is 4KB.
A block sram of SCAR16~19 is 16KB.
A block sram of SCAR20~23 is 32KB.
2. Removed the register of RVILMCR which has no effect.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use one common `if SOC_SERIES_NRF52X` instead of `depends on` for
each particular SoC option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 4be102f8e05a9fa12290d8209a8cb38569265478.
Inclusion of `<system_nrf*.>` from `soc.c` files is no longer needed
since `SystemInit()` is not called from those files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The power off sequence in cavs is meant to be used only by custom pm
policy handler thus guard it with proper ifdefs.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
The native_tasks definition was directly in the soc_inf soc.h
header. But soc.h pulls a lot of other headers.
Some of those could cause conflicts, say with application
headers, for users who only wanted the be able to register
native tasks in a module.
Let's refactor the native tasks definitions into their own header
and include that header from soc_inf's soc.h.
In this way users who need only need to register a native tasks
can just include posix_native_tasks.h, and all previous users
see no change.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Initialization part of this anomaly is now handled internally
by the startup code provided by the MDK.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Invoking `west sign` in `west build` accelerates twister because `west
build` is run in parallel, see rationale in superseded and very
different (CMake-based) PR #52942.
To maximize backwards compatibility:
- `west sign` is optional in `west build`
- `west flash` will sign (again) if any rimage --option is passed
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.
Signed-off-by: scott worley <scott.worley@microchip.com>
This commit introduces power management support for EFR32BG SoCs.
Tested on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The purpose of the GIC ITS is to translate message-passing interrupts into
LPIs. The LPI range starts at value 8192, which means the current default
value (200) is too low. Therefore, bump the highest IRQ number when ITS
is enabled.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added UART instances and changes to enabled
support for PCIe UART instances.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When CONFIG_NOCACHE_MEMORY=y, the .nocache section is placed in between
__rodata_region_end and _app_smem_start/__kernel_ram_start. Make sure
this region is covered by the MPU background region so that the static
region for nocache is configured correctly.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It's best practice to run as little code as possible as root (especially
when listening to network ports). When not itself running as root
already, remote-fw-service.py has always tried to invoke cavstool.py
with "sudo". Unfortunately this looks like it never worked; at least not
on Ubuntu 22 where this commit was tested. Moreover it did not fail
immediately but mysteriously timed out without any useful error message.
- The first, most obvious bug was that "sudo" does not propagate
SIGKILL (and a few other signals), see "man sudo". Compare:
```
$ sudo sleep 30 &
$ kill $! # sudo propagates the TERM signal and sleep is terminated
$ sudo sleep 30 & sudoPID=$!
$ kill -KILL $sudoPID
$ ps xfao pid,ppid,pgid,sid,comm | grep -C 5 -e PID -e sleep -e sudo
```
Fix this by invoking proc.terminate() first before proc.kill().
proc.terminate() is more "polite" with cavstool even when not using
sudo.
- Second issue: when signals are sent to sudo, strace shows that its
signal handler invokes `getpgid()` and then ignores signals coming from
its own process group. `man sudo` states: "sudo will not relay signals
that were sent by the command it is running...", which seems related.
`start_new_session=True` option moves sudo to a different PGID which
stops sudo from ignoring signals from its remote-fw-service.py parent.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Introduce the new stm32h5 soc serie from STMIcroelectronics.
Note that stm32h503x do not have TrustZone nor SAU
Signed-off-by: Francois Ramu <francois.ramu@st.com>
A recent change introduced the possibility to declare MPU memory
regions using the device tree and the framework described in
zephyr/linker/devicetree_regions.h.
So remove the device region declared in mpu_regions[] and the used
defines for the addresses, rename REGION_DEVICE_ATTR to REGION_IO_ATTR
in arm_mpu.h to be compatible with the framework and add a device tree
node to fvp_baser_aemv8r.dts to describe the device memory region.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Remove the manually created linker section, because it's already
automatically generated for all sram regions in the DTS with the
"zephyr,memory-region" compatibility.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This reverts commit 7a85983ebc.
This commit was merged prematurely and is causing issues on multiple
platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some pico-sdk drivers call a panic function, originally implemented
as part of the Pico's C runtime. This commit adds a Zephyr compatible
implementation of panic, so that those drivers could be compiled with
Zephyr.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
In general, RTC and TIMER driver implements counter API but there
are exception when those peripherals are used in a custom way
(e.g. for system timer or bluetooth). In that case, system must
prevent using counter based on a reserved instance. Previously,
it was managed by Kconfig options but that cannot be maintained
when switching to devicetree configuration of the counter driver.
A new approach removes Kconfig options and instead adds static
asserts in the files which are using direct peripherals. Those
asserts check if given node is not enabled in the device tree.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Some platforms need to define multiple memory regions with
various attribute. This patch adds dts defined regions in the mpu
configuration. The memory attribute can be set in the device tree.
Signed-off-by: Yanqin Wei <Yanqin.Wei@arm.com>
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Removed the EEPROM and ESPI configuration from file
Kconfig.defconfig.mec172xnsz. Since it overrides the
setting present in the Device Tree file.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Adding this condition will limit the minimum residency time to enter
sleep mode. This will fix tests in test\kernel\sleep\usleep.c causing
longer than expected test times due to going into sleep mode with no
time limit.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Enabled GPIO support for rpl_crb board by adding
platform GPIO specific definitions.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Use Device Tree bindings to configure clock source/frequency for enabled
UARTs only.
Get rid of UART clock ungating from `soc.c`, as that functionality has
been moved to the clock controller.
Signed-off-by: Artur Rojek <artur@conclusive.pl>
Add functionality for changing the code location
based on the flash chosen node for RT devices.
Remove obsolete Kconfigs that used to be used
to set the code location for RT devices.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Reusing existing code during CPU init at power gating exit.
Additional changes:
- replacing magic value for memctl and atomctl with more readable
definitions,
- using dedicated macros in place of asm inlines.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
There is a spi-flash fl256s on emsdp board, which can be
contolled by DesignWare SPI driver. Now add DW SPI and
SPI-FLASH support for emsdp board.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Allow selecting between direct SMPS and LDO on the startup. This
enables selecting to use SMPS regulators which can save bit of power.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
The STM32H730 series has a variant built with SMPS. It uses
`stm32h730xxq.h` header file instead of `stm32h730xx.h`, which has the
SMPS macro defined.
This commit adds the `SOC_STM32H730XXQ` configuration option to allow
the build system include the proper header file. With this change,
boards can enable `CONFIG_POWER_SUPPLY_DIRECT_SMPS` to set up the power
supply for the CPU.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add clock initialization for MIPI and LCIDF to NXP RT5xx SOC.
Note that clock divider properties are used by both initialization
routines, as the required clock divider will vary depending on
attached display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is a follow-up to commit 7195db01f4.
Restore the check that was accidentaliy removed in the above commit,
so that the message is again logged only once per detection of the
anomaly 160 conditions.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Now building twice back to back does not build anything the second time
when CONFIG_CLEANUP_INTERMEDIATE_FILES (which obviously breaks
incremental builds) is also turned off.
Fixes commit 2906d1aa51 ("soc/intel_adsp: Build bootloader with Zephyr")
Properly implementing custom commands requires BOTH
`add_custom_command()` and an `add_custom_target()` wrapper with some
careful DEPENDS wizardry between them.
https://cmake.org/cmake/help/latest/command/add_custom_target.html
> Use the add_custom_command() command to generate a file with
> dependencies.
The documentation of add_custom_command() also similarly refers to
add_custom_target()
When this is not done properly, the build is cursed in various, very
time-consuming ways which are not officially documented but here
instead:
https://samthursfield.wordpress.com/2015/11/21/cmake-dependencies-between-targets-and-files-and-custom-commands
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This is a bugfix. It uses the right storage label `slot0_partition` for
esp32s2. Note that this is already the case for esp32 and esp32s3.
This should address
https://github.com/zephyrproject-rtos/zephyr/issues/55286.
Signed-off-by: Ning Shang <syncom.dev@gmail.com>
This is a follow-up to commit fe3b97a87f.
This message should not be a warning, as it does not actually indicate
that something potentially bad happened. On the contrary, it informs
that conditions in which the anomaly 160 could occur were detected and
the anomaly was prevented from occurring. There is no need for this
message to appear in the default configuration (INFO level). In fact,
the message would undesirably flood the console in some cases (like
the kernel/mem_protect/stack_random test) and sometimes it would also
require enlarging the stack of the idle thread (the function is called
underneath k_cpu_idle()). Therefore, the logging level of this message
is changed to DEBUG.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Voltage comparator driver submits notifications into system work queue,
this change will make driver to use dedicated work queue, and priority
of dedicated work queue are configurable as well.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update ESP32-C3 architecture as IMC instead IMA.
Although not documented, ESP32-S3 supports CSR instructions.
It also needs to be enabled, otherwise build will fail.
Fixes#53555
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For RISCV arch, enable FLASH_SIZE and FLASH_BASE_ADDRESS config.
To avoid duplicated work, remove flash config from RISCV soc.
Signed-off-by: Jonas Otto <jonas@jonasotto.com>
Drop the non existing option PINMUX_XEC, this has been removed in
d76f4f2c8a drivers: pinmux: mchp_xec: drop driver
And is currently causing build errors.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add the stm32U5 serie for the support of the STM32_BACKUP_SRAM
The PWR peripheral is enabled by the soc/arm/st_stm32/stm32u5/soc.c
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the following warning:
cavstool.py:706: DeprecationWarning: There is no current event loop
asyncio.get_event_loop().run_until_complete(main())
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This is a follow-up to commit fe3b97a87f.
Add a cmake warning issued when the workaround for the nRF5340 anomaly
160 cannot be applied because the application is configured with no
system clock.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Drop STM32 pinmux driver in favor of pinctrl. Some definitions located
in pinmux headers were used by the pinctrl driver, so they have been
moved there.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Cleanup core if booting from bootloader using RT5xx. This is required
because the call to SystemInit will push data to the stack, and the
bootloader may have configured stack limits or MPU settings. Either
would cause the core to fault if these settings are not first
cleaned up.
Perform this cleanup if the boot header is not present, as in this case
the application was likely kicked off via a bootloader.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow to include boot header for code linked into
not only FlexSPI controlled memory.
Fixes#53867
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
Implement a workaround for the nRF53 anomaly 160. This consist of
a set of writes to certain hardware registers that is done at boot
and a piece of code that is executed when the CPU is made idle and
that prevents the CPU from switching between active and sleep modes
more than five times within a 200 us period.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use CMSIS SystemInit for all NXP iMX.RT SOCs, to simplify initialization
flow, and remove redundant code where possible.
Introduce Kconfigs to disable Cache at boot, since SystemInit will enable
code cache on these platforms, which may be undesirable behavior.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert NXP LPC SOCs to use CMSIS SystemInit, and remove redundant code
where it exists. This will enable initialization flows to be more
standardized across all platforms.
Since LPC54xxx and LPC55xxx series enables SRAM banks in SystemInit,
provide Kconfigs to bypass this setting and keep additional SRAM
banks unclocked.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add call to SystemInit for all NXP Kinetis SOCs and remove any
redundant code from initialization flow. This allows watchdog
initialization to be removed from all Kinetis SOCs as it is handled
by SystemInit.
Since Kinetis watchdog is enabled by default at boot, allow watchdog
setup to by bypassed with CONFIG_WDOG_ENABLE_AT_BOOT. This
setting requires the user to provide a watchdog configuration hook
using z_arm_watchdog_init, but will allow the watchdog to remain
enabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS
samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...
tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Allow the the SoC to enter deep sleep when CONFIG_PM_DEVICE
is enabled. This will allow to selectively add low power
support for certain drivers like UART and ADC.
The previous checking of ifndef CONFIG_PM_DEVICE was
incorrect. The MEC172x requires the soc power file to perform
some operations when CONFIG_PM_DEVICE is enabled to allow
the hardware to shut down the PLL.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added intel_adsp_ipc_send_message_emergency function that allows to send an
ipc message notifying about emergency event, such as watchdog timeout.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The non-maskable interrupt have no corresponding bit in INTERRUPT and
INTENABLE registers so its occurrence cannot be confirmed. Removed the code
that checked if the interrupt flag is set.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
rodata section for xtensa overrides the .ctors section
containing the constructor info and the _ZEPHYR_CTOR_LIST_.
Removes the ctor related linker script lines from the rodata
section of the ace linker script to ensure that the .ctors is
properly generated and placed when using the xcc-clang compiler.
Fixes#54730
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
PR #30403 implemented nocache regions for ethernet DMA buffers in sram3 to
fix issue #29915. Unfortunately, some STM32H7 variants do not have any
sram3 so they still suffer from #29915.
All H7 variants have sram2 though, so use that for targets without sram3.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
When running the blinky example on STM32H747, with the BOOT_CM4 bit set
to 0, the M4 core goes into panic.
Increasing the value of the hardware semaphore retry prevents this.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This patch allows successive reflashing operation on stm32f3
boards by Enabling the Debug Module during SLEEP mode.
This will especially makes reflahing and debugging possible
with pyocd runner on west commands.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adding additional core power-off before core is properly power-up after
power domains is wake up from power gaiting state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is moving common power configuration code outside of the
section only for the primary core. This should be enabled for all cores
and it was put there probably by mistake.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
When building with picolibc and gcc, the loops to do zeroing/copying
get replaced by gcc with calls to memset/memcpy. This fails this early in
the boot process and results in an illegal instruction exception.
Marking the variables being manipulated in the calls as volatile prevents
the compiler from optimizing the loops (replacing them with memset/memcpy).
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
On some STM32 MCUs SEGGER RTT is only working with realtime updates
when DMA is clocked. The STM32U5 series uses a new DMA controller
module called GPDMA.
Refs: #34324Fixes: #54316
Signed-off-by: Almin Iriskic <almin.iriskic@student.tugraz.at>
Add SOC_CC1352P and SOC_CC2652P chip types to SoC's Kconfig
(with integrated high power amplifiers).
Also requires modifications to HAL TI's family conditions.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
New KConfig option to set `CCFG_FORCE_VDDR_HH` inside CC13xx/CC26xx
customer configuration file, making it it possible to use 14dBm
TX power (instead of the default 13 dBm limitation).
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Explicitly define function pointer as (void*)() and not (void*).
In C this cast is done implicitly, but C++ does not allow it.
Also, the const is moved to the correct location. Now it's a constant
pointer to a function(void) that returns void, instead of a pointer
to a function(void) returning (const void).
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
The nRF HW models have been updated to correspond to a 52833 instead
of a 52832. Let's follow them.
The motivation for the change is to enable proper BIS encryption support
(for BT LE Audio ISO).
Changes:
* Point in manifest to latest HW models
* SOC_COMPATIBLE_NRF52832 has been removed, and SOC_COMPATIBLE_NRF52833
added in its place (with no uses at this point)
* Where SOC_COMPATIBLE_NRF52832 was used to set encryption like for a 52832
(to avoid using the MAXPACKETLENGHT), we set the condition to just
SOC_NRF52832.
Note: The MAXPACKETLENGHT register exists in the new simulated nrf52833,
thought it does nothing.
* In the BLE ctrl LLL radio HAL, all macros are renamed accordingly
(timings are NOT changed).
* Board dts definition now refers to the 52833 soc definition. New 52833
features set as not supported by now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
The parameter doc string for hda was incorrect as the parameters
had been updated to take the IP base address, block size, and stream id
instead. Updates all doc string comments to account for the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The DMA API contract specifies that start/stop may be called multiple
times. Prior to adding power management this was perfectly fine as it was.
In adding power management, there are additional side effects that can
cause issues. Instead check the state of the channel prior to start/stop
and do nothing if already in the desired state.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit modifies the defconfig for efr32bg22 SoC so that Gecko SPI
selection depends on the DT_HAS_*_ENABLED define.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Update usage of zephyr_code_relocate to follow new API. The old method
of relocating a file was the following directive:
zephyr_code_relocate(file location)
The new API for zephyr_code_relocate uses the following directive:
zephyr_code_relocate(FILES file LOCATION location)
update in tree usage to follow this model. Also, update the NXP HAL SHA,
as NXP's HAL uses this macro as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The value in this bitfield is provided in the two's complement form,
so it requires special handling. Previously, it was read as just an
unsigned value and this could result in a wrongly computed CAPVALUE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This reverts commit 81908cd367.
This commit introduced a regression on SOF. Value of soc_cpus_active is
set by the core X it self in functions pm_state_set and
pm_state_exit_post_ops. soc_adsp_halt_cpu can by called only by the
primary core.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:
* Common registers, offset 0x00-0x0f, accessible regardless of the value
of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1
In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.
This CL tries to simplify this by the following steps:
1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
SMB registers.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
The code used the name DFDSPBRCP referring to the DSP Boot / Recovery
Capability Pointer register from DSP Subsystem Capability / Status
Registers range. The address used, however, pointed to DSP Core Shim
(DSPCS) registers block. Changed define names to not be misleading.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
1. Support Sleep, Deep Sleep and Deep Power down modes
2. Enable the MEMC FlexSPI driver when using device power
management so we can reconfigure the FlexSPI pins to
save power. The MEMC FlexSPI driver is enabled when we
enable the Flash subsystem, however we would like to
reconfigure the FlexSPI pins even when the Flash driver
is disabled, hence MEMC is selected when PM_DEVICE
is turned on.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.
This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add support for configuring FlexSPI1 clock speed to RT5xx soc
initialization, so that memory present on FlexSPI1 can be accessed.
Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this
SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
If defined(CONFIG_ASSERT) and !defined(CONFIG_ADSP_IMR_CONTEXT_SAVE),
build will fail as symbol "global_imr_ram_storage" is not defined.
Link: https://github.com/thesofproject/sof/issues/6896
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Xtensa's ESP32 misses this base CCOUNT value, which causes wrong
arch_timing_freq_get() value reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enabling by default (if SPI3 used) because it affects all revisions
since "Engineering B", including the most recent one as of today
(revision 3).
Size changes when enabled:
- -Og: flash +160 bytes (+0.02%), RAM +8 bytes (+0.01%)
- -Os: flash +144 bytes (+0.02%), no change to RAM usage
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
Save FP user register and FP register file during context switch.
This change enables shared FP registers mode using CONFIG_FPU_SHARING.
Since there is no lazy stacking, the FPU registers will be saved regardless
of whether floating point calculations are performed in the threads when
CONFIG_FPU_SHARING is enabled. This require 72 additional bytes in the
stack memory.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The unaligned trap bit is set by default, contrary to the xmc
reference manual. This PR unsets the bit in the initialization.
It can still be set later via the CONFIG_TRAP_UNALIGNED_ACCESS
option.
Note that the same approach is used in xmc4500 reference software
init code (see SystemCoreSetup() in infineon hal module).
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Cleaning up the instances of CODE_LOCATION used in the soc
clock_init and replaced them with the Kconfig
FLASH_MCUX_FLEXSPI_XIP due to the correlation with
the flexspi clocks and the XIP feature of Flexspi.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
This Kconfig is moved to the soc level since it determines
the flexspi clock initialization for XIP.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added information about pin output direction into
Z_PINCTRL_STM32_PINCFG_INIT if output_low or output_high is provided.
GPIO output flag is set in configuration struct and this will end up
being loaded into MODE register. Because of that it is no longer
required for pinctrl_configure_pins() to set MODE register value for
GPIO input/output.
Fixes#53141.
Signed-off-by: Lukasz Mazur <lukasz.mazur@hidglobal.com>
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
xmc_device.h sets which XMC4xxx.h file to include and also sets
other defines such as GLOCK_GATING_SUPPORTED.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add region calculations and implementation of
sys_mm_drv_query_memory_regions to pass calculated regions down
the line.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add i.MX93 Cortex-A Core support on Zephyr.
i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
This patch makes IMR context save an option that can be enabled. By
default FW, after D3 state transition, will be boot using normal flow.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
IT8XXX2 HW support sha256 calculation, and its calculation is
faster than FW. We place SHA256 message, hash and key data
(total 512bytes) in RAM. If we enable hw sha256, because
HW limits, the sha256 data must place in first 4KB of RAM.
We add sections for hw sha256 calculation in linker.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Currently, memory from __rodata_region_end to __kernel_ram_start (or
_app_smem_start if config userspace) was uncovered by programable MPU
region. But to config static MPU region (nocache region is on ths
region), the programable MPU region need confg full patition.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the messaging unit to ensure that the RT11xx dual core mode will
wait for the second core to boot successfully during early init
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx features CM4 core, which must be booted from CM7 core. Add
support for loading an image for the CM4 to RAM, and booting the CM4 core
from this image. Each image is built independently using sysbuild, and the
M4 image build produces built collateral with load address information the
M7 image can use to load it to RAM
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow linking code into OCRAM region when building for RT1xxx SOCs. This
can be used on the RT11xx dual core SOCs as a shared memory region, when
the M7 core needs to load code into a region accessible to the M4 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Low-power management is part of the RTC peripherals' domain
on ESP32C3. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Low-power management is part of the RTC peripherals' domain
on ESP32S2. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
- Adds initial system power management support.
- Adds option to add extra delay when waking from
deep sleep.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Low-power management is part of the RTC peripherals' domain
on ESP32. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Expand ifdef by adding new Kconfig option UDC_KINETIS as
preparation for USBFSOTG UDC driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.
In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.
In particular this changeset is doing three things:
1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
`CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`
2. The cache API has been reworked.
3. Comments are added.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
When MCUBoot is enabled, IRAM region needs to be set
to a smaller value to avoid overlapping. This shall be re-worked
when MCUboot build for ESP32 is performed in Zephyr environment.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a hidden Kconfig option to select the index of the target RTU
(Real-Time Unit) subsystem. This index can be used by peripheral
drivers, for example, to know the peripheral instance index since the
HAL is index-based.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Added a missing SDK function POWER_PowerInit
to the clock_init function of the soc in lpc55S36.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
- Put L2C init level in pre_kernel_2 to wait for syscon driver
- Check if SMU exists when preprocessing
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Control shared interrupts enabling/disabling via IDU.
With that we can easily enable and disable them for all cores
in one place.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
EXTRA_IMGTOOL_ARGS is used to set additional options by the user.
Any user change will overwrite this option, which
is unintuitive.
Also option ROM_START_OFFSET will be overwritten which is also unintuitive.
Replace hardcoded config option MCUBOOT_EXTRA_IMGTOOL_ARGS
with proper config ROM_START_OFFSET.
Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
Be consistency with zephyr.strip
This will help with reproducibility issues like the one in
https://github.com/thesofproject/sof-bin/pull/106
Use the `strip_command` introduced by commit c060b075a6 ("cmake:
toolchain: bintools abstraction")
boot.mod is already deterministic because it has no debug symbols; no
need to strip it.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
SOF compilation is sensitive to compilation warnings
Some simple and neutral changes to avoid them
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
IMR save and restore context is a flow implemented for ACE
move boot specific procedures to ace subdir
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
In ACE architecture, only core 0 should receive IPC interrupts from host.
Unmasking secodnary core IPC interrupts was causing race condition in
ipc irq handler after enabling secondary core.
Signed-off-by: Przemyslaw Blaszkowski <przemyslaw.blaszkowski@intel.com>
The linker script for intel_adsp ace was missing the
snippets-sections.ld include, causing it to ignore any custom section
defined in with cmake zephyr_linker_sources().
Adding it in the same location as it's done in xtensa-cavs-linker.ld.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
HAL for NXP S32 is updated to a newer version, hence some headers and
macro definitions must be updated accordingly.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Update rt5xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update rt6xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Context save is saving whole memory to persistent
memory area, than turning off memory and CPU
Context restore is a modified boot flow, where
the previously saved context is restored
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Updated the clock_init function to the latest sdk
and added a safe initialization for the flash setup
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added a selecion on rt6xx that allows the loading of
the safe flash clock initialization to be inside SRAM
if the user code is being executed from flash.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Call CMSIS SystemInit at early platform boot, to ensure that registers
are configured correctly on RT10xx series.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch updates ipc response procedure in power down function. New
flow is only limited to the writs into two registers. We need to clear
the IPCxIDD register in case if its contains any leftovers from a
previous responce. And then write a response to the IPCxIDR.
To prepare response we need to copy incoming request and then mark it as
replay. New message with IPC Busy bit set is then send to host.
The reason for this is a change in the behavior of the IPC driver
compared to how it worked when this function was originaly implemented.
The biggest difference are enabled interrupts in register IPCxCTL.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Zephyr maps start/end of rodata section with variables
using __rodata_region namespace. The exception was Xtensa.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add XIP support with MWDT toolchain. To have it proper tested
add separate nsim platforms for XIP (flash + sram) and
non-XIP (sram) memory organization in addition to existing
nsim_hs platfor with CCMs (ICCM + DCCM) memory organization.
This PR also enables MPU for all nsim hs3x based platforms
(like we previously enabled it for qemu_arc_hs) to have proper
memory regions permissions.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Since DTS doesn't contain the BDF anymore (it's looked up at runtime),
hardcode the BDF value for the use of early serial.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Update lpc54114 support to use LMA address offset instead of linking
secondary core image into primary core memory. This will allow support
with sysbuild to be enabled. Additionally, use partitions to select where
the secondary core image will be located in flash
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use LMA adjustment building dual core image with LPC55s69. The load
address adjustment allows the second core image to be flashed onto the chip
by the debugger, into the secure region of the LPC flash.
Additionally, remove the build dependency that was enforced by the SOC.
This requirement to build the secondary core image first can be enforced
by the project itself, instead of the core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Move setting soc_num_cpus into its own SYS_INIT function such
that we can ensure it happens as one of the first things. We
need soc_num_cpus set before soc_mp_init is called but also before
interrupt controller init functions might be called.
Also, by having it in its own function, it ensures that
soc_num_cpus gets set regardless of how CONFIG_MP_MAX_NUM_CPUS
is set. Since if CONFIG_MP_MAX_NUM_CPUS=1, we do not call
soc_mp_init().
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
\MTL SOF is not compiling when
8d0eb6ce10
(devicetree: remove deprecated DT_CHOSEN_*_LABEL macros)
is applied
Fix - zephyr/toolchain used to be included by
devicetree/zephyr.h. The file has been removed by 8d0eb6ce10
Include is needed for ALWAYS_INLINE macro
Signed-off-by: Marcin Szkudlinski <marcin.szkudlinski@intel.com>
Move regs configuration from previous pinmux.c to soc layer.
This involves the debug interface, configuring the GPIO bank power
and the test clock out pin.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Only include fsl_flexspi_nor_boot when a boot header is present,
as this is the only case where the boot header data will be required.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use spisc_it8xxx2_regs instead of IT83XX_SPI_*** registers declaration
to fix in cros_shi_it8xxx2.c
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
The `mps2_an521_remote` and `mps2_an521_ns` targets have the same
memory layout for code and ram, meaning that you can't use TF-M
(`mps2_an521_ns`) and the second core (`mps2_an521_remote`) at the
same time.
This commit updates the memory map of the `_ns` build targets as
follows:
- Reduces the code memory region from 1 MB to 512 KB, maintaining the
existing base memory address of `0x0010 0000`
- Maintains the existing 512 KB ram memory at `0x2810 0000`
It updates the `_remote` target as follows:
- Reserves 468 KB code memory at address `0x0038 B000`
- Reserves 512 KB ram memory at address `0x2818 0000`
This ensures that the code region for the `_remote` target doesn't
overlap with the code region used by the single flash image layout
defined upstream in TF-M, which the `_ns` target is based upon.
Signed-off-by: Kevin Townsend <kevin.townsend@linaro.org>
When CONFIG_MP_MAX_NUM_CPUS=1, which it does for some tests, we will
get compiler warnings with soc_adsp_halt_cpu(), so only build it
when CONFIG_MP_MAX_NUM_CPUS > 1.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Some SAM0 contains revisions with separated includes for example
SAMC21 and SAMC21N.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
We look at the Intra DSP communications capability register (DFIDCCP)
to determine the number of cores. There might be a better way to
determine the number of cores, but this works for now.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add Kconfig SOC_HAS_RUNTIME_NUM_CPUS symbol that an SoC can
set to specify that it supports determining the number of CPUs
at runtime.
On xtensa add support for SOC_HAS_RUNTIME_NUM_CPUS and expose
soc_num_cpus that the SoC code should set early in boot as the
means to expose the number of cpus.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Basically:
- Name RAMABLE_REGION as "RAM";
- Insert the relocation hooks for gen_relocate_app.py.
Also, to help with "rimage" peculiarities, `fix_elf_addrs.py` changed to
not copy empty sections to output, as this would prevent someone trying
to move all of some section (such as BSS) to a different location and
reuse the platform linker script - which would generate an empty section
anyway.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Besides adding ARCH_HAS_CODE_DATA_RELOCATION, this patch also adds
support for the "sample_controller" SoC (used by qemu_xtensa) as
demonstration.
As Xtensa lacks a common linker script at the arch level, enabling it
for each platform will be a piecemeal effort. This patch adds it to the
`soc/xtensa/sample_controller` SoC. Basically, default RAMABLE_REGION is
set to be called "RAM", and hooks are inserted so that
gen_relocate_app.py can add the relevant linker bits.
Also, `tests/application_developent/code_relocation` was tweaked to
support the qemu_xtensa platform. Basically, add the relevant linker
script and ensure that relevant memory regions have their program header
(PHDR) associated.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Xtensa is the odd one out by using _data_start/_data_end instead. Using
the Zephyr standard helps avoid ifdefs for common code, like tests.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Fix a bug where an IPC message is sent while the peer/host ack for
the previous message has not yet been processed. There is existing
logic to check 'idr' INTEL_ADSP_IPC_BUSY bit, but this leaves
the following race:
- DSP: msg A sent by DSP to host
- HOST: IRQ, msg A acked, host sets DONE bit -> ADSP_IPC_BUSY cleared
- DSP: msg B sent by DSP to host, IPC_BUSY is clear so proceeding to send
-> e.g. 'devdata->sem' is reset --> BUG!
- DSP: IRQ, msg A done
-> e.g. call to 'sem_give(&devdata->sem)' which is wrong as
the semaphore was just reset in previous step for msg B
Add additional state to track handling of the acks. This allows
to postpone sending message B (in above example), until message A
is fully processed.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
STM32WB Controller supports application to initiate the "PHY Update
Procedure" (BT_USER_PHY_UPDATE) while it doesn't support it to be
automatically triggered on connection establishment (BT_AUTO_PHY_UPDATE).
Default BT_USER_PHY_UPDATE to true, which automatically defaults
BT_AUTO_PHY_UPDATE to false.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update Intel ADSP timer driver to use DT_HAS_<compat>_ENABLED Kconfig
symbol to expose the driver and enable it by default based on
devicetree.
We remove setting 'default y' for the timer driver in
Kconfig.defconfig.series as that is now handled in the driver Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Now that IPM drivers are enabled based on devicetree we can
remove any cases of them getting enabled by Kconfig, *defconfig*,
and *.conf files.
We need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x eSPI SAF has significant hardware changes
requiring a new SAF configuration structure. In preparation
for the MEC172x we move the current SAF header out of common
to the MEC1501 subfolder, remove an unused and empty common
header and remove includes of the moved headers from MEC172x.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Move runtime checks to use arch_num_cpus(). This is to allow
runtime determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Add #ifdef CONFIG_SMP around code that only needs to exist when
SMP is enabled.
Also include ksched.h to get decleration of z_sched_ipi.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Cleanup CMakeLists fixing error message:
...
No SOURCES given to Zephyr library: soc__x86__raptor_lake
...
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
IT8xxx2 uses a relatively slow SPI flash for ROM with a small 4k
I-cache. As a result in large or busy applications, instruction fetch
can be very costly due to I-cache misses. Since exception handling code
is some of the hottest code in most applications, add an option (enabled
by default) causing that code to execute out of RAM in order to improve
performance.
This is very similar to exception section placement on XIP niosii
platforms (which has similar motivation), but can still be disabled by
configuration.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
These functions are small and may be very hot depending on the workload,
so are usually a good choice to execute from RAM.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
The chip I2C driver uses chip_get_pll_freq(), so that function needs to
be built even when the PLL configuration is not changed at boot.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Fixes boot failure on CAVS platforms with
CONFIG_NO_OPTIMIZATIONS=y by moving z_soc_mp_asm_entry
into .text linker section to ensure it is copied to
SRAM.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Sometimes IPC message acknowledgement should be done by external
code to provide sufficient timing (example assemble code related
to powering down). Added bool return type to ipc message done handler
that if callback function returns true, IPC API skips writing
IPC message completion bits.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
The restore vector after power gating was configuring the MEMCTL register
incorrectly. This caused an FW crash during the cache prefetch.
Additionally, since lp sram cache issue was fixed, xtensa hal function
can be replace with zephyr equivalent.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
eSPI PUT_IOWR_SHORT protocol can send 1/2/4 bytes of data in a single
transaction. This allows the host to send max 32-bits Port80 code
at one time. This CL sets bits OFS0_SEL~OFS3_SEL in the DPAR1 register
to let the EC hardware put the full Port80 code to DP80BUF FIFO.
It also groups the N-byte code into a single 32-bits variable when
necessary by analyzing the offset field in the DP80BUF register.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Allows applications to use other frequencies than 60 MHz.
For example 48 MHz for USB communication with usbserial driver.
Signed-off-by: Michal Sieron <msieron@antmicro.com>
Continue to phase out MP_NUM_CPUS, change Kconfig to be
MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Change automated searching for files using "IRQ_CONNECT()" API not
including <zephyr/irq.h>.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include the correct header file. This was uncovered due to
a recent change where zephyr/kernel.h include was removed
from init.h
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The soc.h from the espressif HAL module provides register definitions
like APB_CLK_FREQ, which are required for the Zephyr TWAI driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Introduce support for Pinctrl driver on NXP S32Z/E SoC's.
The NXP S32 pin controller is a singleton node responsible for
controlling the pin function selection and pin properties, based on the
pin node group approach. The pinmux configuration is encoded in a
32-bit value.
Each S32 SoC implementing Pinctrl must create a `pinctrl_soc.h` header
which define SoC-specific macros to initialize the pinctrl structure.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This patch introduces support for NXP S32 devices, specifically for
S32Z27 from S32Z/E family.
NXP S32Z27 processors are composed of two Real-Time Units (RTU)
containing each four ARM Cortex-R52 cores with flexible split/lock
configuration, and dedicated internal SRAM.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
The commit boot code does not call hp_sram_pm_banks() so there is
no need to do an extern declare.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The functions to get memory bank counts are simple enough that
they can be always inlined. This mostly helps with debugging,
especially with NO optimizations, as inlining is being done only
if the inline keyword is specified. This creates a chicken and
egg problem where the SRAM init functions need to call these
before code copying can be done. However, these functions are
not in memory before code copying, resulting in jumping into
memory with random bits.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is a "load" flag associated with segment to be copied
into Xtensa attached memory during manifest parsing. So only
copy those segment if indicated so. There may be some segments
in the struct with NULL destination address. So this is
to avoid memcpy into NULL.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is an assumption in parse_module() during code/data copying
that the memory has already been zero-ed, and hence no need to
clear memory when a BSS segment is encountered. In CAVS ram
initialization code, bbzero() is called. However, in ACE code,
there is no such call. So add them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Now that VMPIDR_EL2 will be initialized in z_arm64_el2_init, the code
that I wrote for initializing VMPIDR_EL2 on fvp_baser_aemv8r can be
removed.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
The `ARCH` init level was added to solve a specific problem, call init
code (SYS_INIT/devices) before `z_cstart` in the `intel_adsp` platform.
The documentation claims it runs before `z_cstart`, but this is only
true if the SoC/arch takes care of calling:
```c
z_sys_init_run_level(_SYS_INIT_LEVEL_ARCH);
```
Which is only true for `intel_adsp` nowadays. So in practice, we now
have a platform specific init level. This patch proposes to do things in
a slightly different way. First, level name is renamed to `EARLY`, to
emphasize it runs in the early stage of the boot process. Then, it is
handled by the Kernel (inside `z_cstart()` before calling
`arch_kernel_init()`). This means that any platform can now use this
level. For `intel_adsp`, there should be no changes, other than
`gcov_static_init()` will be called before (I assume this will allow to
obtain coverage for code called in EARLY?).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
MTL is just one platform and this code is going to be used in multiple
platforms currently under development, so reduce the confusion and move
to a common namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
File still not being removed due to out-of-tree usage. We will drop it
once the external code has stopped referencing it.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Split the defines based on domain and cleanup ace_v1x-regs.h so we can
finally remove it and stop include soc specific headers across the tree.
Future generations of this family will be able to use the same naming
scheme without having to use the version name in the file name.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Convert timer driver to use a light weight syscon and DTS and convert
register information to use offsets and sys_read/sys_write instead of
structs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Now that we have shim defined for each platform, no need to support all
platforms within the same struct. This change exposes some bugs where we
were relying on the old structure and calling into unused register space
for example for SRAM initialization on some SoC generations.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup soc.h and move interrupt defines into own headers. Rename some
of the defines for ACE to have a unified namespace.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The DW register block was duplicated into the ACE header while we had
the same thing in the driver. Move everything to the driver as the first
step with further improvements planned on top of this.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The file uses architecture specific IRQ calls without including
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
sys/util.h is not needed by soc.h, and was causing troubles with
redefinitions of ARRAY_SIZE (from HAL) in CI.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files were using macros defined in sys/util.h without including it,
e.g. for MHZ().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of NMI API (NMI_INIT()) without including the
appropriate headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
With the incoming removal of kernel.h/types.h from init.h, lots of files
start to show compile errors because they relied on indirect
definitions, including errno.h.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some files make use of CMSIS APIs/definitions without explicitely
including CMSIS headers.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The sys* ops like sys_clear_bit are indirectly included via arch CPU
header. Other stuff like find_msb_set end up included via this header as
well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Do FW communication outside of memory window setup to accomodate for
additional IPC commands and headers.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This is not guaranteed to match the physical layout of the memory, so
get them individually based on node label.
For initialization, use bbzero.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This was all done as part of the soc and called from the soc. Define
this type of console under drivers/console and use it in the SoCs
supporting that via SYS_INIT instead of calling the console code
directly.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of just declaring the memory window register in DTS and have
everything else all over the place (headers, Kconfig, etc.) this change
defines the memory window instances in DTS and uses the device model to
initialize the windows. Code is still part of the SoC, given that we do
not have a driver subsystem suitable for this type of device yet.
Move FW status to own workflow and separate from window setup.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clean up and refactor x86 SoC headers in preparation of adding
new platforms in the future.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
add common mec_gpio.h to allow access to common gpio_regs
structure for both mec15xx and mec17xx, used in pinctrl driver
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
This is an AArch64 board. We also add RK3399 SoC support,
as well as a very simple Synopsys 8250dw UART driver.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
The Inter-DSP Communication (IDC) is being used to send
sched IPI to other CPU cores. When a core receives an IDC,
it needs to ACK it by clearing the BUSY bit in TDR, and also
needs to the BUSY bit in TDA to signal done after processing.
These two steps are needed to complete one IDC message.
If we do only one (and not both), the other side will not be
able to send another IDC message as the hardware still thinks
the core is processing the IDC message (and thus will not send
another one). So add the step to clear the BUSY bit in TDA so
we can have multiple sched IPIs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit updates the intel_adsp build script to invoke the
`fix_elf_addrs.py` Python script using the Python executable detected
by the build system.
This ensures that the script is run using the same Python installation
used by the Zephyr build system.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
The platform has support for pinctrl, but it is selecting both pinmux
and pinctrl. Legacy applications requiring pinmux should enable it
manually.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
() The check for whether the CPU is already active before halting
was incorrect. It should only fail if the CPU is not active,
but the CHECKIF() conditional was inverted. So invert it.
() Also need to set the entry in the bookkeeping array to false
once a CPU is considered powered down.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The conditionals to check if the CPA bit is already set or cleared
are incorrect. This results in the code always asserting. So fix
those.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add options about Internal RC(IRC) oscillator.
- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Linker scripts contains a `.last_section` section that is placed in rom
region as NOLOAD for the purpose of retrieve the actual number of bytes
contained in the image. See d85efe0b10
However, a previous section may cause the location counter to be
incremented for alignment purposes. This can result in the size of the
image to be 0x10FA but location counter to be 0x1100 because it has been
aligned for next section placement.
Therefore, two new Kconfig settings are introduced.
Those settings request the linker to will write a pattern in
`.last_section`. Together with removing NOLOAD and writing a patten to
the section then we ensure that data is written after alignment of
location counter, and thereby forces the image size to be in sync with
the location counter.
The default pattern used will be 0xE015 (end of last section).
Some systems may fill up the flash completely, or simply write data at
the end of the flash, which in both cases can result in overflow.
Therefore, the new settings can be disabled.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Allow building for nRF non-secure and TF-M enabled without having the
platform partition enabled.
In this configuration the soc_secure functions have no valid
implementation, leave it as a compilation error if the application
includes the functions.
Add missing dependency on soc_secure functions being available for
SOC_HFXO_CAP_INTERNAL configuration.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Make Kconfig produce an error when GPIOs cannot be forwarded in the
current configuration instead of silently excluding the forwarding.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
It's useful for RAMABLE_REGION to have a uniform name when
CODE_DATA_RELOCATION is supported, because otherwise the build system
needs to be aware of how the region name differs between architectures.
Since architectures tend to prefer one of 'SRAM' or 'RAM' for that
region, prefer to use 'RAM' as the more general term.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
This will trigger link commit immediately after start
to fix hda start flow.
Applies to link out only.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
On ACE, there is another layer of interrupt masking where
this masks, in addition to the DesignWare controllers.
So we need to un-mask during IPC init or else we are not
going to get any host IPCs.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Zephyr encodes multi-level interrupts in a certain way, and
the driver is not utilizing the encoding correctly. So fix
it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit removes the `k_mem_pool` section for the memory pool API,
which was removed in the v2.5.0 release.
Signed-off-by: Stephanos Ioannidis <stephanos.ioannidis@nordicsemi.no>
console can't handle the amount of data coming from many tests, so
introduce a delay beween testcases.
Use ZTEST_TEST_DELAY_MS to delay test execution.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
...Z_THREAD_STACK_BUFFER.
This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
...Z_THREAD_STACK_BUFFER.
This is currently a symbolic change as Z_THREAD_STACK_BUFFER
is simply an alias to Z_KERNEL_STACK_BUFFER without userspace,
and Xtensa does not support userspace at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
In commit c75e6cfcb9
("soc: intel_adsp_ace1x: Added IPC/IDC implementation")
definition for INTEL_ADSP_IPC_DONE was modified for ace1x platforms.
This change was not correct as the new definition was also used to
program the IDA register.
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
1) HDA logging seems to be using some padding like '\x00'. Such
string can print well on a terminal but corrupt the string match.
And this can cause false failure if RunID matching is affected.
Remove such padding before checking RunID.
An affected RunID example:
'7aa9ba3c6db12\x00\...\x00\x00\x00\x00d0c7fcf382a4af40ec6'
Expected:
'7aa9ba3c6db12d0c7fcf382a4af40ec6'
2) Use non-displayable chars for live connection check. Otherwise
the log output will have subtle garbage like extra spaces which
locate randomly.
This solution comes from the PR #50071, the author is smrtos.
Signed-off-by: Ming Shao <ming.shao@intel.com>
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Remove the remote service logic in the FW loader, now
the FW loader is a pure FW loader as it used to be.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Spilt the cavs server and FW loader, to make the cavstool.py
a pure FW loader and runner as it used to be. The reasons is
try to keep the FW loader won't be affected by the client-
server-based HW service as possible, and more easy to debug.
After splitting them, the service program spawns another
process to run the FW loader. The advantage is no matter when
the FW loader is stuck, the service can detect and stop it,
then continue to next test.
Fixes#47652.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Copy cavstool.py to remote-fw-service.py in order to track changes
for following splitting work of cavstool.py.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
If the target is built without CONFIG_PM this stack is not
used and does not need to be defined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The tool has caused some hard to detect failures when used
concurrently with the SOF Linux driver to observe logs. This
has been rootcaused to the code to handle and send IPC messages
that has been active even in logs-only mode. In vast majority
of cases, the SOF kernel driver is faster to act and handles
the IPC interrupts. But occasionally the cavstool.py timing was
just right and it managed to ack a message before Linux driver.
Fix the problem by not handling IPC messages when the tool
is run in logs-only mode.
Reported-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Interrupt vectors level 5 and 6 are not available in ACE. Just remove
them from the linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In ace15_mtpm the debug exception vector address is mapped to INTLEVEL4
and not INTLEVEL 6. This can be checked in the core-isa header:
"""
define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
"""
in
modules/hal/xtensa/zephyr/soc/intel_ace15_mtpm/xtensa/config/core-isa.h
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In normal operation the clock for peripheral devices is derived from
the PLL clock.
During sleep, the xmc4xxx can switch its system clock source (f_sys)
from the PLL clock to an f_ofi clock. Switching to the f_ofi clock
is the default behaviour which breaks UART comms.
Use the PLL clock source during sleep instead to fix the issue.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
1. Add USB_STACK_USE_DEDICATED_RAM=1 define that is
used by the SDK USB driver
2. Delete unused "config USB_DEDICATED_MEMORY"
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
and fsl_os_abstraction.h. These headers are used by
the SDK USB driver. usb_dc_mcux.h header file is not longer
needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
driver and use the one implemented inside the SDK USB
driver. This requires updating the references to
usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
out of the header file that is included by the SDK and
into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
Interrupts should be enabled after the init is successful,
else we see errors of the ISR getting called before the
init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
SDK USB driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Now that timer drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Instead of deciding based on SoC version, add information to Kconfig and
get it from there on code.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of deciding to init based on SoC version, define that
information in Kconfig and use it from there.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of using SoC version to decide to power on or not, add this
information to Kconfig and get it from there.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of using SoC versions, define the information about base and
extended ports on Kconfig, and use this information from there.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Instead of using version of the SoC, declare on Kconfig the need for it,
and use this information to decide upon enabling the code or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
error: assignment to 'void *' from 'unsigned int' makes pointer from int
| lpsheader->lp_restore_vector = (uint32_t) &dsp_restore_vector;
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
ARC processors are highly configurable, so ARC toolchain supports
big amount of mcpu options for all that HW configurations.
As difference in many configurations among the same processor
family usually doesn't affect Zephyr code we don't want
to create Kconfig option for each possible CPU configuration
(just to map Kconfig option to correspondent mcpu value
in 'cmake/gcc-m-cpu.cmake').
Instead we prefer being able to set proper mcpu value
individually for any ARC SoC and using 'cmake/gcc-m-cpu.cmake'
just for reasonable defaults.
To apply SoC-related changes for build-options on early stages of building
'tune_build_ops.cmake' should be created in appropriate SoC directory.
Example:
./soc/arc/snps_qemu/tune_build_ops.cmake
File content:
set(GCC_ARC_TUNED_CPU hs4xd)
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
The Xtensa arch has historically had state/user register accessor
macros with bare three-byte symbol names. I think this might have
been in the original Cadence-contributed arch integration, but I'm not
sure. In any case they also exist in the same names in vendor
HAL/toolchain code and are causing collisions. We never should have
had these symbols exposed in our header.
Put them under an XTENSA_ prefix to decollide.
Signed-off-by: Andy Ross <andyross@google.com>
The enet1g peripheral was missing in device tree for nxp rt11xx.
With this commit, the peripheral can be operated like the enet peripheral
with the eth_mcux (kinetis-ethernet) driver at 10/100 Mbit (no gigabit).
Signed-off-by: Nils Larsen <nils.larsen@posteo.de>
According to RM, there are 2 pins that need a 3 bit mask for daisy chain,
changed it accordingly.
(E.g. IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT for imx6sx)
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
Fix NXP MPU configuration for k6x flash region. The previous flash MPU
setting was based around the assumption that the user was executing from
the flash region at 0x0000_0000–0x07FF_FFFF, which may not be case if the
user selects to execute from SRAM, such as running from sram_l
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove description from SOC_FAMILY_SMARTBOND so it's not directly
selectable. Also fix related board configuration.
Fixes#49916
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano
applications processor, composed of a quad Cortex®-A53 cluster
and a single Cortex®-M47 core.
Zephyr OS is ported to run on the Cortex®-A53 core.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Place vector sections after ROM_START sections.
Also add init.ld script that will prevent overlapping .init sections
in telink_b91 SoC.
Fixes#49036.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
This patch adds core restore vector. FW will restore core context from
memory and then return to the state it was in before power gaiting.
Adding struct of LPSRAM header. ROM during reboot check this struct in
serching for magic value and restore vector address.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch adds initial implementation of dynamic power gating for ace
platforms. The code is limited to enabling PG in HW registers and
disabling all interrupts.
CPU context storing and restoring still needs to be implemented. PG at
this moment will cause FW to halt during reboot.
Patch contains small refractor. Value CORE_POWER_CHECK_DELAY has been
moved to common header so it can be reused in other places.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is renaming primary core power down procedure by removing ACE
prefix. Prefix was added to avoid name conflicts while linking. The
problem is now resolved and name can be revert to the original version.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Similarly to other drivers, use auto generated DT_HAS_<COMPAT> Kconfig
symbol to control use of STM32 lptim driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Added code to enable platform specific Virtual Wire GPIOs. With this
change, able to send the USB-C overcurrent Virtual Wire event to
Meterolake SOC.
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Update all esp32 socs to include esp_timer early init, which
is part of hal v4.4.1 update.
Update reboot function to meet proper SoC init/deinit peripherals.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This patch is to increase kernel VM size to 1.5MB and
memory size to 2MB to ready for future driver bring up.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
According to RM the daisy chain mask should include both bit 0 and 1, not
only bit 0.
Updated bitmask accordingly
Signed-off-by: Antonio Tessarolo <anthonytexdev@gmail.com>
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The STM32G070 and STM32G0B0 Socs don't have USB power delivery support
but the PINs PD0, PD2, PB15, PA8 pins of these still have the same
pull down on boot configuration options as the SOCs with UCPD support.
This commit skips the check if such a peripheral is enabled,
therefore the configuration will always be applied on these SOCs
and the compile error is resolved.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
On STM32U5 series, when an image is build with mcuboot,
image starts at offset 0x400 instead of default 0x200.
This should be taken into account when calling imgtool by using
dedicated option to set header-size value.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that clock control drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This allows to disable UART peripheral driver and still be able to build
correctly (header is not visible when LPUART driver is not enabled).
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
So far systick frequency was duplicated in 'sysclk' DT nodelabel's
'clock-frequency' property and in per SoC SYS_CLOCK_HW_CYCLES_PER_SEC
default value. Set the latter based on DT configuration.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This adds initial support for Renesas SmartBond(tm) DA1469x series SoC.
Initailly only DA14699 is explicitly supported, however this code should
also run on other SoCs in this series since all of them support the same
core features available initially.
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This has been moved to the NXP HAL layer so that all
SDK NonCacheable symbols get placed in the nocache
region
Also pull in the HAL changes associated with this
change.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This commit replaces API that became deprecated with the release
of nrfx2.9 - see CHANGELOG in zephyrproject-rtos:hal_nordic repository
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Now that crypto drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Consolidate common kconfigs of the CAVS series into the series level and
remove duplication among all supported SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit updates the custom target architecture type specified for
the `SOC_OPENISA_RV32M1_RI5CY` and `SOC_OPENISA_RV32M1_ZERO_RISCY` SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.
Note that the hack overriding the build system-default `-march` flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Implements a logging backend implementing the mtrace protocol
to relay log messages over SRAM. This protocol is implemented
by the SOF Linux driver ("mtrace" debugfs interface).
This implementation follows example of the ADSP HDA logger implemented
in commit 6913da9ddd ("logging: cAVS HDA based logger").
Cc: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Define SRAM window 2 details to the headers and open access to host to
the window in bootloader.
Also clarify Kconfig documentation that the semantics of the windows can
vary depending on which host<->DSP communication scheme is in use.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Similar to pinctrl, almost all device drivers will depend on the reset
controller being available, so default the driver class to y at SoC
level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
* Adds a default hook and init function for cavstool.
* Adds an optional padding on flush feature to ensure all data is written.
* Fixes an error in cavstool.py for correctly wrapping the ring buffer.
* The test case now ensures wraps and flushes occur numerous times.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Now that DMA drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Replaced hand coded use with DT_STRING_UPPER_TOKEN_BY_IDX. We should have
introduced the APIs when this was needed since the token values in
devicetree_generated.h should only be accessed via an API macro.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that I2S drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit enables the SoC's flash memory controller.
- added lpc55s36 specific code in the NXP MCUX driver
to take advantage of the SoC's check-before-read
capability
- enabled the FMC node in the SoC's dtsi (iap)
- added the flash controller chosen node to the board's dts
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Now that usb device drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Set the default value for SYS_CLOCK_HW_CYCLES_PER_SEC based on DT cpu0
clock-frequency property.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
USB SRAM region was accidentally deleted by an earlier
commit. Rename the memory region used by USB to USB_SRAM instead
of SRAM4. SRAM4 was the wrong name for this region.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
It includes the definition for the DMA peripheral of this type,
present on stm32U5 devices.
A particular DMA_STM32U5 config is selected for that purpose.
The driver is derived from the existing dma_stm32.c
The GPDMA is counting channels (0-15) ; stream offset is 0.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The low power mode logic for i.MX RT1064 indirectly includes the HAL
definitions, but this is fragile and depends on specific Kconfig options.
This fixes build issues if for example CONFIG_ARM_MPU is not set.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Pull more function into ram code section to effectively improve
access speed and performance.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding I2C FIFO mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
The I2C master supports two 32-bytes FIFOs, channel A and C
are supported now.
I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.52ms(2.4ms->1.88ms) compared to the original pio mode when the
frequency is 100KHz.
3. It is normal to read sensor data through I2C on Nereid's platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Attached the correct clock frequency for
FlexComm15 which connects to the PMIC_I2C peripheral
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Do not usu XTENSA_HAL when building with xt-clang, instead uses
the HAL provided together with the toolchain. Just like it is
done with "xcc" toolchain variant.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Many device pointers are initialized at compile and never changed. This
means that the device pointer can be constified (immutable).
Automated using:
```
perl -i -pe 's/const struct device \*(?!const)(.*)= DEVICE/const struct
device *const $1= DEVICE/g' **/*.c
```
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Non-functional polish of Kconfig symbol description and
QEMU_CPU_TYPE_${ARCH} variable (used only for verbose cmake comments)
for HS6x QEMU.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Remove the static MMU entries for each available Xilinx PS UART
instance. Those are no longer required now that the PS UART
driver uses the DEVICE_MMIO API for register space mapping.
Signed-off-by: Immo Birnbaum <immo.birnbaum@weidmueller.com>
Don't setup CONFIG_ARC_HAS_ACCL_REGS option for board explicitly
if we use it default value.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Increase the default user-allocable number of RTC channels to meet
the nrf_802154 driver requirements.
Signed-off-by: Adam Zelik <adam.zelik@nordicsemi.no>
1. Update soc.c file to add USB clock setup
2. Add a linker file to move USB transfer
buffer and controller buffers to USB RAM
3. Update Kconfig's to add USB support
4. Add zephyr_udc0 nodelabel
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This had bitrotten a bit, and didn't build as shipped. Current
libasan implementations want -fsanitize=address passed as a linker
argument too. We have grown a "lld" linker variant that needs the
same cmake treatment as the "ld" binutils one, but never got it. But
the various flags had been cut/pasted around to different places, with
slightly different forms. That's really sort of a mess, as sanitizer
support was only ever support with host toolchains for native_posix
(and AFAICT no one anywhere has made this work on cross compilers in
an embedded environment). And the separate "gcc" vs. "llvm" layers
were silly, as there has only ever been one API for this feature (from
LLVM, then picked up compatibly by gcc).
Pull this stuff out and just do it in one place in the posix arch for
simplicity.
Also recent sanitizers are trying to add instrumentation padding
around data that we use linker trickery to pack tightly
(c.f. SYS_INIT, STRUCT_SECTION_ITERABLE) and we need a way
("__noasan") to turn that off. Actually for gcc, it was enough to
just make the records const (already true for most of them, except a
native_posix init struct), but clang apparently isn't smart enough.
Finally, add an ASAN_RECOVER kconfig that enables the use of
"halt_on_error=0" in $ASAN_OPTIONS, which continues execution past the
first error.
Signed-off-by: Andy Ross <andyross@google.com>
Previous versions were using, incorrectly, the host in/out regblock size
of 40 bytes for all peripherals when in fact the link in/out regblock size
is 20 bytes in size.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Besides in a form of {host}:{port} to specifying the port using, we
also support specifying --log-port and --req-port parameters for the
cavstool client.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Because we use INADDR_ANY by default now, specifying a net interface
is no longer needed. Remove it and remove the dependency of the
netifaces python package.
Fixes. #48584
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Make the cavstool service can start with specifying the port
optionally by:
cavstool.py -s {host}:{log port} --req-port {req port}
OR
cavstool.py -s {host} --log-port {log port} --req-port {req port}
And we can also specify the network interface instead:
cavstool.py -i {network iface}
If the server address or the network interface is not specified,
it will use INADDR_ANY by default.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Add specifying the port for the remote cavstool remote service.
Ex.
west flash --remote-host {host}:{port} \
--pty {host}:{port}
Specify the port is optional when running west.
And another major change is now we have to specify the remote log
service by --pty to make it output the log message immediately.
Previously it will output directly. Why we make this change is
because this is more close to the behavior we use west flash.
Fixes. #46865
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT600.
Added alias for usdhc0 to be able to use SDHC test.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Now that peci drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This option was previously enabled only if the M extension was
available, because typical compilers do not provide internal libraries
for RV32IAFC so builds fail at link-time. An appropriately-configured
compiler (such as GCC configured with
`--with-multilib-generator=rv32iac-ilp32--f`) can support such a build
however, so don't lie about the presence of an FPU.
This doesn't affect existing builds because CONFIG_FPU gates use of the
FPU, and is off by default. Enabling CONFIG_FPU will require an
appropriately-configured compiler, possibly also requiring careful
choice of CONFIG_FLOAT_HARD.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Now that ethernet drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
DMA controller ownership can be done in the driver
initialization, it does not need to be part of the SoC. It simplify
the code and remove duplicated definitions.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Currently the USB-C PD dead battery support is disabled very early in
the boot process, in order to give access to CC1 and CC2 pins to the
application. However this breaks dead battery support as this instructs
the PD source to stop delivering power.
This commit changes the behavour to keep the internal pull-up in dead
battery pins enable if the UCPD driver is enabled, and the corresponding
UCPD peripheral is also enabled. The code is a bit complex as it aims to
support possible G0 devices with a single UCPD controller (as opposed to
the current one), and also because I haven't found any simple way to
match the UCPD peripheral with the bits in the SYSCFG_CFGR1 register (I
used the same trick with the base address as in the driver).
Given I have not been able to get that working with macros, the check is
done at "runtime", however GCC is smart enough to optimize the code. The
generated code is identical if none of the UCPD peripheral is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
add the MMU page table entries for all instances of the Xilinx AXI GPIO
controller IP core. Other than any Zynq-7000 peripheral supported so far,
the existance of 1..n instances of the IP core within the FPGA part of the
SoC is optional. Therefore, other than addressing instances of supported
peripherals using their DT node label as has always been the case so far,
the data for the MMU page table is added using the DT_FOREACH_STATUS_OKAY
macro.
Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
The use of the RT11xx CAAM requires
cache write-through mode,
otherwise some tests give a compiler warning.
Add to the soc CMake to do this
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Now that sdhc drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
The macro INPUTMUX_PINTSEL_COUNT is name INPUTMUX_PINT_SEL_COUNT
on certain SoC's in the SDK.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
There are several test cases that create fake ethernet devices and
expect the fake device to be the only ethernet device enabled. Some
tests handle this be explicitly disabling actual ethernet drivers,
but this doesn't scale well.
Change drivers/ethernet/Kconfig to utilze a menuconfig option that
wraps all the drivers. This allows us for those test cases that
don't want any actual ethernet drivers to disable them with a
simple CONFIG_ETH_DRIVER=n.
Note, the fake ethernet devices utilize CONFIG_ETH_INIT_PRIORITY so
we have it outside of the 'if ETH_DRIVER' block.
Signed-off-by: Kumar Gala <galak@kernel.org>
Make all series consistent with regard to where code is located and put
the power init code in power.c alongside other power related code.
Reduce soc.c per series to an empty file that can be removed.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
initializing the SoC is the same across series, so put everything in one
place in the common code base.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Now that counter drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
machine-timer node name changed in #48429.
but Kcondif.defconfig.gd32vf103 not followed it.
It makes misconfigures the RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.
So the machine-timer did not count the actual time.
Correcting node name to fix this problem.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Remove NET_CONFIG_IEEE802154_DEV_NAME in favor of DT based choice using
zephyr,ieee802154.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Have the kscan device enabled in devicetree will now get the driver
enabled by default when CONFIG_KSCAN=y is set. So we can remove
driver enabling Kconfig values in various Kconfig.defconfig files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that entropy drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Have the display enabled in devicetree will now get the driver
enabled by default when CONFIG_DISPLAY=y is set. So we can remove
setting driver enabling Kconfig values in various .conf and
defconfig files.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that flash drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
All IEEE 802.15.4 drivers are now automatically enabled if they are
'okay' in DT and all of its dependencies are 'y', including
CONFIG_IEEE802154. This means individual driver enablement is not
necessary anymore in Kconfig.defconfig files or samples/tests. Boards
need to still make sure any dependencies are enabled, e.g. SPI bus in
some cases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
COUNTER_RTC_STM32 used to be enabled directly based on COUNTER status.
This should not be the case anymore as we should first check
DT_HAS_ST_STM32_RTC_ENABLED status (which is already done in
drivers/counter/Kconfig.stm32_rtc).
Remove these 3 lines that are not correct anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In some arm64 boards, MMU regions are set so userspace can access all
peripherals (MT_P_RW_U_RW), including the GIC.
This seems like a mistake, which has been copy/pasted in some boards.
Change this to no userspace access by default (MT_P_RW_U_NA),
like the other boards.
Signed-off-by: Henri Xavier <datacomos@huawei.com>
This is temporary until support has been enabled. lpc55s36's IAP controller
is different and does not match previous implementations.
The Zephyr driver uses a data structure matching the IAP controller to
implement a feature that should normally come out of the ROM.
Since IAP support is not in yet, disabling the option in the SoC's Kconfig
and disabling the node in the device tree is the proper way to go forward.
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
LPC55s3x family has an additional analog mode bit available. Update
IOCON binding and IOCON driver to support setting this bit via a pin
control property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Now that CAN drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the CAN.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
All SOC_ERET definitions expand to the mret instruction (used to return
from a trap: exception or interruption). The 'eret' instruction existed
in previous RISC-V privileged specs, but it doesn't seem to be used in
Zephyr (ref. RISC-V Privileged Architectures 3.2.2).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_NRF5_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME.
All SoC files have been updated with the addition of an ieee802154 node
(disabled and only on those SoCs that define ieee802154-supported. The
peripheral has been enabled in the nRF52840DK board (used for testing
ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_KW41Z_DRV_NAME in preparation for the removal
of NET_CONFIG_IEEE802154_DEV_NAME.
KW41Z files have been updated with the addition of radio and an
ieee802154 nodes The peripheral has been enabled in the frdm_k41z board
(used for testing ieee802154).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe the radio and IEEE 802.15.4. This allows to
remove usage of IEEE802154_CC13XX_CC26XX_DRV_NAME in preparation for the
removal of NET_CONFIG_IEEE802154_DEV_NAME. All boards used in testing
have been updated to enable the peripheral in DT as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that watchdog drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
watchdog and not respect the devicetree state of the watchdog.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that DAC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the DAC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
The ARC <soc.h> headers are no longer used, so they can be removed.
Refer to the previous commits for more context.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The soc.c source only contains code relevant to SMP, and in fact, it is
a file that is left empty when pre-processed from a compiler perspective
if CONFIG_SMP=n. This change renames it to smp.c to make it clear it
contains SMP related code, and, it compiles it conditionally to
CONFIG_SMP=y.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
ICI (Inter-Core Interrupt Unit) interrupts and priorities were hardcoded
in C files. This patch moves this information to Devicetree and updates
code to make use of it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
sysconf base address was hardcoded in <soc.h>. Create a new compatible
and define it in Devicetree, where hardware needs to be described.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The definitions provided by this file seem to be unused throughout the
tree, so remove it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.
DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:
- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include what is necessary: <zephyr/init.h> and a platform specific
architecture header.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Andes fpga base AE350(60M Hz) may fail in XIP because it causes hundreds
of cycles to fetch instructions, decreased tick rate to 100 if CONFIG_XIP.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Now that ADC drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the ADC.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Add the "zephyr/" prefix to various #include statements that are
preventing the CI form running with LEGACY_INCLUDE_PATH=n.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
After some analysis I found out that there's no machine timer provided
by the "riscv" vendor. There are some specs for the mtime/mtimecmp
registers (this is why we can have a single driver), but the actual
register layout or implementations differ amongst vendors. GD32 uses the
Nuclei implementation, named "system timer" in their documentation. This
patch aligns with vendor specs.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The HAS_I2C_DW was to limit Kconfig visibility to only platforms
that utilize the I2C DW IP. The Kconfig for I2C_DW depends on
DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED which will cause the same
visbility limitation to only platforms that have I2C DW devicetree
nodes. Thus we can remove HAS_I2C_DW and its references.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that I2C drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the I2C.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
During transition into D3 state, watchdog timer have to be paused. FW can
resume it when core is re-enabled.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Now that clock control drivers are enabled based on devicetree we
need to remove any cases of them getting enabled by Kconfig.defconfig*
files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a sensor and not
respect the devicetree state of the clock control. Additionally we
can get problems with prj.conf/defconfig getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
This PR adds a KConfig option that allows moving
all .noinit content related to wifi a net stack into external
ram. This free dram space to application.
Linker script files are also modified so that the content
are mapped into external ram.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Base address for PRCI is not used anywhere in the tree for this
platform. Again, if ever used, this needs to come from DT.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is no GPIO driver for such platform, and if it existed, all this
information should be provided in Devicetree (as other platform drivers
like UART do).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
- zephyr/toolchain.h is not needed
- gd32vf103.h is not needed (no CMSIS here)
- undefinition not needed, HAL is now patched with a prefix for this
definition.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
SystemInit is declared in gd32vf103.h. Include it instead of relying on
indirect soc.h includes.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Put ace headers alongside other headers. The contents of ace_v1x-regs.h
will be moved around to new headers being added across all series and
SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of enabling WOVCRO clock based on the SOC, use a configuration
to indicate support, so that each platform can specify if WOVCRO is
supported or not.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
If test for WOVCRO clock fails, code shouldn't just choose WOVCRO clock
as the lowest frequency one, but LPRO instead.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
For intel adsp platforms we have a common multiprocessing.c file and
then another multiprocessing.c for ace and multiprocessing_cavs.c for
cavs. Rename the cavs specific implementation to follow the convention.
There is not need to "cavs" suffix since the file is already inside its
specific directory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Inside the common directory there were files that are CAVS specific and
are not used by ACE_V1X. Lets create a subdir called cavs inside the
common to put files that are common for only cavs plaftorms.
Note that there are still remaining code that in the common folder that
are using cavs namespace like "cavs_ipc_*" that may need some additional
work.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We already have riscv_clic.h and riscv_plic.h, no need to have the same
declarations in soc_common.h as well.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Now that PWM drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the PWM.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that SPI drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the SPI.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that gpio drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the GPIO.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Intel ADSP CAVS is now a proper series with all CAVS SoCs running under
it. This will give us to Intel ADSP series:
- CAVS
- ACE v1.x
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to ace linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In order to coredump dump the ram memory, it is necessary that we define
in the linker scripts two variable to indicate the start and the end of
the ram area. Adding these variables to cavs linker script.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
cavs/version.h was never used by Zephyr, it was supposed to be needed by
SoF. This no longer seems to be the case, just removing it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Now that sensor drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the sensor.
Additionally we can get problems with prj.conf/defconfig
as well getting incorrectly overridden.
Fixes#48198
Signed-off-by: Kumar Gala <galak@kernel.org>
This CL adds a DT node, 'power_leakage_io', which property,
'leak-gpios', contains GPIOs that have leakage current. In oerder to get
better power consumption, npcx power driver will disable the connections
between these io pads and input buffers before entering deep sleep.
Then, restore the connections after ec wakes up.
The users can overwrite this property at board DT file. Here is an
example:
&power_leakage_io {
leak-gpios = <&gpio0 0 0
&gpiob 1 0>;
};
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL configures low-voltage (1.8V) detection via GPIO driver with
GPIO_VOLTAGE_1P8 flag. It also adds support for this flag in
pin_get_config() function.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Cleanup npcx low-voltage (1.8V) detection configuration. It removes
unused soc utilities, macros, and DT node. We will configure this
feature by GPIO driver with GPIO_VOLTAGE_1P8 flag later.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
ITE EC chip it81202 and it81302 both have embedded integrated
pd module (support two usbpd ports), this is different from
standalone TCPC. To prevent cc pins leakage, we disable not
active ITE USBPD port cc modules, then cc pins can be used
as gpio if needed.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Declare clock control in the shim header per SoC and remove ifdeffry
from the driver simplifiying it and making it ready for the next
platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Declare those register in the adsp_shim header instead of the code
applying ifdefs that limit the scope to only specific SoCs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move those defines and values back to headers. Kconfig is not a good
place for this, later this should move to DTS.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
using once single header to support multiple socs and product
generations is error prone and not easily maintained.
Over time we have been adding conditional code in headers and extending
structs to support new HW features which becomes a problem.
Goal is to keep platform headers in sync with hardware specification and
allow of introduction of new platforms and hardware features by just
introducing a new SoC with its own set of headers.
This is now just a copy of existing cavs-shim.h with slight changes,
goal is to clean this up long term and sync with hardware datasheets and
align on naming as well.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move headers into the include/ folder per soc and rename fw_defs.h to
adsp_memory to align with SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The driver has be DT_INST based for a while so the Kconfig
symbols CONFIG_UART_PL011_PORT0<n> aren't used. So lets
remove them.
Signed-off-by: Kumar Gala <galak@kernel.org>
MISRA C:2012 Rule 14.4 (The controlling expression of an if statement
and the controlling expression of an iteration-statement shall have
essentially Boolean type.)
Use `do { ... } while (false)' instead of `do { ... } while (0)'.
This commit is a subset of the original commit:
5d02614e34a86b549c7707d3d9f0984bc3a5f22a
Signed-off-by: Simon Hein <SHein@baumer.com>
Uses a macro with a define flag to enable register dumps on the DSP
side. On the python side a simple booling flag.
The default disabled both debug flags and makes the tests
considerably quieter.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Any project with Kconfig option CONFIG_LEGACY_INCLUDE_PATH set to n
couldn't be built because some files were missing zephyr/ prefix in
includes
Re-run the migrate_includes.py script to fix all legacy include paths
Signed-off-by: Tomislav Milkovic <milkovic@byte-lab.com>
Include linker sections header to move z_arm_platform_init to text
section. It is now is placed in the TEXT section.
Signed-off-by: Bernard Lee <bernard.lee@nordicsemi.no>
For SAML21-based parts, the REFCTRL register is locked while the ADC is
enabled. Permit some parts to declare that they need the ADC to be
disabled before modifying REFCTRL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAMR34 and SAMR35 parts, tested on a SAMR34
Xplained Pro dev board. Confirmed operational peripherals: UART, GPIO,
PWM, ADC.
NOTE: The SAMR34 datasheet lists NVIC line 20 for the ADC's interrupt,
but the SAML21 datasheet gives line 22. It appears that the SAMR34 sheet
is incorrect (the ADC doesn't function with line 20), and as such, I have
also omitted the adjustments for TC4 and AC...
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Implement support for SAML21 parts, tested on a SAML21 Xplained Pro dev
board. Confirmed operational peripherals: UART, GPIO, PWM, ADC.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Some tests was built failed due to cannot find the __imr macro:
Try to fix it by including the linker/section.h in soc.h.
Fixes#47830.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Clean up unused psl functions in scfg.c, unused DT macros, unused psl DT
nodes and related yaml files. Currently, PSL pad configurations are made
by pinctrl mechanism. Please refer
https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
irq_lock() returns an unsigned integer key.
Generated by spatch using semantic patch
scripts/coccinelle/irq_lock.cocci
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
HDA is a common IP used across the entire ADSP line and deserves
a name respecting that alongside similiar IP drivers such as the
ADSP GPDMA driver.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Those belong where other attribute macros are usually defined. They are
not xtensa or ADSP specific and are used across Intel SoCs on all
architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Instead of ifdeffing on SOCs and missing things along the way, maintain
platform definitions that are different among SoCs in one single file
per SoC and use data from that file critical spots.
In this case, we were checking for CAVS25, setting one value where
everything else was set to 0, so new SoC like ACE was getting 0 as well,
although it has the same value as TGL.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Clean up unused pinmux function 'npcx_pinctrl_mux_configure()' and
related 'NPCX_DT_IO_ALT*' macro functions.
Please refer https://issuetracker.google.com/234861079 for more detail.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Adding command queue mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
I2C command queue mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.72ms(2.54ms->1.82ms) compared to the original pio mode when the
frequency is 100KHz.
3. krabby platform can boot normally.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix build error if CONFIG_PM and CONFIG_INIT_VIDEO_PLL are enabled.
Added 2 missing semicolons.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Introduce a new RISCV_HAS_CLIC symbol for platforms using CLIC,
reorganize the Kconfigs and make the Nuclei ECLIC depending on the new
symbol.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add static MPU regions for this SoC.
These regions will be initialized as static region during system boot.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
cAVS and ACE gpdma driver have several similarities. This commit merge
this two drivers into a single one for Intel ADSP devices.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c: In function
'z_soc_irq_is_enabled':
zephyr/soc/xtensa/intel_adsp/ace_v1x/irq.c:47:3: warning: 'return'
with no value, in function returning non-void [-Wreturn-type]
47 | return;
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Move to use DEVICE_DT_GET instead of device_get_binding as
we work on phasing out use of DTS 'label' property.
Signed-off-by: Kumar Gala <galak@kernel.org>
Change APL_GPIO_DEV_* defines to be DT_NODELABELs instead of
"label" strings. This lets us change users of these defines to
use DEVICE_DT_GET.
We update samples/board/up_squared/gpio_counter to use DEVICE_DT_GET
as part of this change.
Signed-off-by: Kumar Gala <galak@kernel.org>
Uses the dt_compat_enabled Kconfig preprocessor to set defaults
for each HDA driver.
Each direction is uniquely selectable which can be useful when building
with SOF where only some directions may wish to be enabled at any given
time.
By default, given the device tree (intel_cavs.dtsi) only the host
directions are enabled but an overlay may adjust that as needed.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
This adds a new stm32f412Rx in the list of stm32F4 devices.
The module stm32cube/stm32f4/soc/stm32f412rx.h exists
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change some behaviors when --log-only is passed in order to add support
for DSP power state: D3. This makes it possible to keep `cavstool
--log-only` running permanently in the "real-world" use case where the
Linux kernel loads the firmware and powers down audio when not in use.
More specifically:
- Do not disable D3 when using --log-only.
- Wait forever for the FW at boot time.
- Check live status when an invalid IPC is received and wait forever if
not alive.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Add a new timeout_s parameter that can also be 'None' = infinite.
No functional change. Required to add future support for DSP power
state: D3
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This CL introduces how to configure PSL (Power Switch Logic) pads
properties such as input detection mode/polarity, pin-muxing and so
on via pinctrl mechanism. It includes:
1. Add two pinctrl properties and their enums for PSL input
detection configuration.
psl-in-mode:
- "level"
- "mode"
psl-in-pole:
- "low-falling"
- "high-rising"
2. Add macro functions to get PSL input detection and pin-muxing
configurations from 'pinmux', 'psl-offset' abd 'psl-polarity'
properties.
Here is an example to configure PSL_IN2 as the PSL detection input and
its mode and polarity.
/* A falling edge detection type for PSL_IN2 */
&psl_in2_gp00 {
psl-in-mode = "edge";
psl-in-pol = "low-falling";
};
A device will be introduced later which uses this pinctrl node to
configure PSL input detection settings and how to turn off VCC1 power
rail by PSL_OUT.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
For vectored interrupts use the generated IRQ vector table instead of
relying on a custom-generated table.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Both idle and suspend states were just being used to set the cpu
idle. That is not necessary, if the pm policy does not find a suitable
power state the kernel automatically calls k_cpu_idle().
This remove unnecessary code and the weirdness of having
min-residency-us set to 0 and other arbitrary values.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
1. Improve the firmware transfer reliability by fixing the misuse
of the socket. Fix the most frequent occurence of the common `recv()`
bug described here:
https://docs.python.org/3/howto/sockets.html#using-a-socket
The longer term fix is to switch to a higher level API like Python
Remote Objects.
2. Not rely on the client's command to disconnect. Previously we
rely on the SIGINT to send stop_command to the server, but it does
not work well in some environments. Refine the whole logic and the
sever disconnect service by checking if the client is alive or not.
These changes make the client-server-based cavstool more stable.
Fixes#46864
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Header soc.h is included during C++ source file compilation
and required adding C++ casts as implicit casting from void*
is forbidden. Fixed minor warning comparing signed with unsigned
integer.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Replaced hardcoded for intel_adsp_ace15_mtpm board
HP_MEMORY_BANKS value used in SOF code with generic approach -
using PLATFORM_HPSRAM_EBB_COUNT read from Devicetree.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Properly prefixing some include files with "zephyr", also organizing
the order they are included.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
These two timers were sharing pretty much the same code. Actually
mtl timer was a "superset" of cavs timer. Just merge them into a
single one called intel audio dsp timer (intel_adsp_timer).
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Do not duplicate code in new SoC and reuse code from intel_adsp/common.
Move SRAM code into own file in common code and setup SRAM in soc for
MTL platform.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This patch implements pm_state_set function for ACE platforms.
This is initial implementation and only includes the basic handling of
PM_STATE_SOFT_OFF.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch add soc_adsp_halt_cpu implementation for ace. Function disable
power and check CPA status to report success. Function should be used only
for secondary cores and can be executed only from primary core.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Poll for CPA bit by which HW confirms that the core has been powered up.
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Add ace/mtl rom flags definitions.
Set the flags in battr to indicate to rom that it should execute
secondary core procedure.
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Meteorlake support as part of the Intel ADSP family.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Co-authored-by: Michal Wasko <michal.wasko@intel.com>
Co-authored-by: Konrad Leszczynski <konrad.leszczynski@intel.com>
Co-authored-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Co-authored-by: Enjia Mai <enjia.mai@intel.com>
Co-authored-by: Flavio Ceolin <flavio.ceolin@intel.com>
Co-authored-by: Tomasz Leman <tomasz.m.leman@intel.com>
Co-authored-by: Bonislawski Adrian <adrian.bonislawski@intel.com>
Co-authored-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Co-authored-by: Andrey Borisovich <andrey.borisovich@intel.com>
Following zephyr's style guideline, all if statements, including single
line statements shall have braces.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We need more time to run codes because of the performance,
so I tune CONFIG_SYS_CLOCK_TICKS_PER_SEC down to reduce
the times of running k_usleep(1), then it can pass test_usleep().
Verified by follow test pattern:
west build -p always -b it8xxx2_evb tests/kernel/sleep
fixes#46208
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Keep the cavstwist.sh it is still working by specifying an
environment variable when CAVS_OLD_FLASHER is set. Provide
a fallback once the client-server-based tool does not work
well in some conditions.
Signed-off-by: Enjia Mai <enjia.mai@intel.com>
Since the timer interrupt is delivered to all cores at the same
time, it needs to be disabled (or masked) to prevent it from
waking a suspended CPU core.
Note that there is no need to re-enable (unmask) timer
interrupt separately as it is being taken care of in
smp_timer_init() when the CPU re-inits itself.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
To power down secondary cores on cAVS 2.5 platforms the primary core
enables the power-saving mode for the respective secondary core and
waits until that core enters idle() and executes the waiti
instruction at which point the core should enter a lower-power mode.
However, that core can then also automatically wake up and execute
its reset path if, e.g. an interrupt is delivered to it. However, it
isn't entirely clear which events are able to wake up cores from that
state. Disabling interrupts on the interrupt controller didn't seem
to prevent that from happening completely. In particular a specific
ADL notebook seems to be susceptible to this problem. Checking for
such sporadic boots and returning to idle fixes the problem.
BugLink: https://github.com/zephyrproject-rtos/zephyr/issues/46372
BugLink: https://github.com/thesofproject/sof/issues/5733
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Select HAS_MCUX_XBARA Kconfig symbol for MIMXRT1062,
since the XBARA Inter-Peripheral Crossbar Switch peripheral is present
on this SOC.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Added mchp mec zephyr image generator python script. It takes
zephyr.bin as input and produces zephyr.mchp.bin.
The default behavior is to not pad to SPI flash size.
(Enable through CONFIG_MCHP_MEC_UNSIGNED_HEADER=y and
CONFIG_MCHP_MEC_HEADER_FLASH_SIZE_256K=y)
zephyr.mchp.bin is composed of:
1. First 4KB contains TAG at offset 0 and header at offset 0x100
2. Offset 0x1000 is the start of zephyr.bin which has been padded
to a multiple of 128 bytes.
3. Boot-ROM EC Info Block (128 bytes)
4. Boot-ROM Co-Signature Block (96 bytes)
5. Boot-ROM trailer (160 bytes) contains the SHA-384 digest of 2-4.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
A full second is too much, and since "Ack local interrupt before
processing IPC" patch, it doesn't seem necessary. This whole second
wait would break tests that log too much content, as the firmware
is already running during the reset - and the host script wouldn't read
the contents, thus some of the logs would be overwritten.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
External libraries can contain processing module code or common library
code. Library manager need to distinguish between both type of modules
for proper loading.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit introduces driver for granting access for own grant
table and for mapping/unmapping foreign gref. Grant tables are used
for data exchange between Xen domains via shared memory page(s) (e.g.
for sharing ring buffer with driver data) This functionality is
widely used and needed for implementing PV backend/frontend drivers.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
It seems a race can happen between the host acknowledging a DONE
interrupt and the DSP being able to mark some IPC as done. To avoid
this, the host script now always acknowledges the DONE interrupt
_before_ processing the IPC message.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Default to 1 CPU core on the Xilinx Zynq-7000 SoC series since Zephyr does
not yet suppport SMP on aarch32.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add Xilinx Zynq-70000 pinctrl header file to define SoC specific
pinctrl_soc_t structure. This is used to store pin configurations for the
pinctrl driver.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Unlock the Xilinx Zynq-7000 System Level Control Registers (SLCR) at boot
to allow write access using the generic syscon driver.
Since the generic syscon driver uses the DEVICE_MMIO_* APIs for
memory-mapped IO we can remove the dedicated SLCR MMU region.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
When using CONFIG_NPCX_IMAGE_OUTPUT_HEX, set the hex_file
runners_yaml_props_target property, so that west flash will flash the
correct file.
Change the cmake flash rules to populate the hex_file value in the
runners.yaml file if either CONFIG_BUILD_OUTPUT_HEX is enabled or some
cmake file set the runners_yaml_props_target hex_file property.
Update the npcx9m6f_evb instructions now that the filename is implicit.
Signed-off-by: Jeremy Bettis <jbettis@google.com>
They may be disabled in some environments (such as Gentoo based
developer mode on Chromebooks). Use extended regular expressions
instead.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Select missing HAS_MCUX_SRC Kconfig symbol for MIMXRT1062,
that allows using NXP i.MX mcux SRC hwinfo driver.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.
Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.
Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
Placing these in the __ram_code section generates a relocation error when
building with toolchain version 0.14.1, moving them back to .text fixes
that (presumably with a performance penalty).
Signed-off-by: Keith Packard <keithp@keithp.com>
ESP32 linker loader needs all sections to be align correctly.
When MCUBoot is enabled, device handles provide by device-handles.ld
does not make the ALIGN(4) at the end, which breaks the loader
initialization. This PR make sure that this particular section
is placed in DRAM instead.
For now this is a workaround until this can be handled in loader script.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Referenced spi_flash_rom_patch.c object was wrongly
linked, which can cause crash due to flash cache disabled
operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
For some reasons RISCV is the only arch where the vector table entry is
called __irq_wrapper instead of _isr_wrapper. This is not only a
cosmetic change but Zephyr expects the common ISR handler to be called
_isr_wrapper (for example when generating the IRQ vector table).
Change it.
find ./ -type f -exec sed -i 's/__irq_wrapper/_isr_wrapper/g' {} \;
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add the definition of address which is used by ROM to jump to FW.
Signed-off-by: Rafal Redzimski <rafal.f.redzimski@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable testcases under tests/drivers/gpio/gpio_basic_api
To run in twister, "-X gpio_loopback" parameter is needed.
Signed-off-by: Yinfang Wang <yinfang.wang@intel.com>
This commit drops the `IRAM_ATTR` macro from the function declarations
because:
1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro,
which increments for every macro invocation and causes the section
specified in the forward declaration to not match that of the
function definition.
2. Section attributes need not be specified for forward declarations.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Commit b91d21d32c added the possibility to define MPU regions from the
device tree, however commit c276088567 removed that possibility for H7
SoC, as it now uses a SoC specific definition of the MPU regions without
the DT-defined regions (probably because the two PRs got developped in
parallel).
Fix that by adding the macro which adds the DT-defined regions to the
STM32H7 specific file.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Currently there are two soc variants (IT81202BX and IT81302BX) on
it8xxx2 series. The IT81202BX is 128-pin package (GPIO K and L groups
aren't bonding with pad).
This makes soc variant configurable and apply corresponding configuration
for a soc.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
