ITE: drivers/usb/device: Add USB Device Controller Support
Add USB Device Driver (usb_dc) of ITE IT82xx2 TEST=west build -p always -b it82xx2_evb 1. zephyr/sample/subsys/usb/hid 2. zephyr/sample/subsys/usb/hid-mouse Signed-off-by: BJ Chen <bj.chen@ite.com.tw>
This commit is contained in:
BJ Chen
Carles Cufí
parent
843d613f1d
commit
215f180296
11 changed files with 2113 additions and 32 deletions
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@ -197,6 +197,13 @@
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pinctrl-names = "default";
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};
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zephyr_udc0: &usb0 {
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status = "okay";
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pinctrl-0 = <&usb0_dm_gph5_default
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&usb0_dp_gph6_default>;
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pinctrl-names = "default";
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};
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&flash0 {
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partitions {
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compatible = "fixed-partitions";
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@ -13,6 +13,7 @@ supported:
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- adc
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- espi
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- gpio
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- usb_device
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- i2c
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- kscan
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- pm
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@ -18,5 +18,6 @@ zephyr_library_sources_ifdef(CONFIG_USB_NATIVE_POSIX
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zephyr_library_sources_ifdef(CONFIG_USB_NRFX usb_dc_nrfx.c)
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zephyr_library_sources_ifdef(CONFIG_USB_MCUX usb_dc_mcux.c)
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zephyr_library_sources_ifdef(CONFIG_USB_DC_SMARTBOND usb_dc_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_USB_DC_IT82XX2 usb_dc_it82xx2.c)
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endif()
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@ -188,6 +188,13 @@ config USB_MCUX_THREAD_STACK_SIZE
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endif # USB_MCUX
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config USB_DC_IT82XX2
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bool "ITE IT82XX2 USB Device Controller Driver"
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default y
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depends on DT_HAS_ITE_IT82XX2_USB_ENABLED
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help
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ITE IT82XX2 USB Device Controller Driver
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config USB_NATIVE_POSIX
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bool "Native Posix USB Device Controller Driver"
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help
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1672
drivers/usb/device/usb_dc_it82xx2.c
Normal file
1672
drivers/usb/device/usb_dc_it82xx2.c
Normal file
File diff suppressed because it is too large
Load diff
24
dts/bindings/usb/ite,it82xx2-usb.yaml
Normal file
24
dts/bindings/usb/ite,it82xx2-usb.yaml
Normal file
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@ -0,0 +1,24 @@
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description: |
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ITE IT82XX2 USB in device mode
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compatible: "ite,it82xx2-usb"
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include: [base.yaml, pinctrl-device.yaml, usb-ep.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true
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wucctrl:
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type: phandles
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description: |
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usbd node WUC interrupt.
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@ -968,6 +968,19 @@
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gpios = <&gpiof 0 0>;
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uart-dev = <&uart2>;
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};
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usb0: usbd@f02f00 {
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compatible = "ite,it82xx2-usb";
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interrupts = <IT8XXX2_IRQ_USB IRQ_TYPE_LEVEL_HIGH
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IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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wucctrl = <&wuc_wu90>;
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reg = <0x00f02f00 256>;
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status = "disabled";
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num-bidir-endpoints = <1>;
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num-in-endpoints = <10>;
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num-out-endpoints = <5>;
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};
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};
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};
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@ -390,4 +390,12 @@
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pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_3>;
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};
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/* USB alternate function */
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usb0_dm_gph5_default: usb0_dm_gph5_default {
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pinmuxs = <&pinctrlh 5 IT8XXX2_ALT_DEFAULT>;
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};
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usb0_dp_gph6_default: usb0_dp_gph6_default {
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pinmuxs = <&pinctrlh 6 IT8XXX2_ALT_DEFAULT>;
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};
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};
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@ -30,6 +30,7 @@
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#define IT8XXX2_IRQ_SMB_C 16
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#define IT8XXX2_IRQ_WU24 17
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#define IT8XXX2_IRQ_WU22 21
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#define IT8XXX2_IRQ_USB 23
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/* Group 3 */
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#define IT8XXX2_IRQ_KBC_IBF 24
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#define IT8XXX2_IRQ_PMC1_IBF 25
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@ -116,11 +116,16 @@ IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_WNCKR, 0x0b);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_SPCTRL1, 0x0d);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_SPCTRL4, 0x1c);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RSTC5, 0x21);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, gctrl_pmer2, 0x33);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_EPLR, 0x37);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_IVTBAR, 0x41);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_MCCR2, 0x44);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_P80H81HSR, 0x50);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_P80HDR, 0x51);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_H2ROFSR, 0x53);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_RVILMCR0, 0x5D);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_ECHIPID2, 0x86);
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IT8XXX2_REG_OFFSET_CHECK(gctrl_it8xxx2_regs, GCTRL_ECHIPID3, 0x87);
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/* PECI register structure check */
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IT8XXX2_REG_SIZE_CHECK(peci_it8xxx2_regs, 0x0F);
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@ -139,6 +144,51 @@ IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, WFCSV, 0x0B);
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IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, RFCSV, 0x0C);
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IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, AWFCSV, 0x0D);
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IT8XXX2_REG_OFFSET_CHECK(peci_it8xxx2_regs, PADCTLR, 0x0E);
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/* USB Device register structure check */
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IT8XXX2_REG_SIZE_CHECK(usb_it82xx2_regs, 0xE9);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_ctrl, 0x00);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_trans_type, 0x01);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_line_ctrl, 0x02);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_sof_enable, 0x03);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_addr, 0x04);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_tx_endp, 0x05);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_frame_num_msp, 0x06);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_frame_num_lsp, 0x07);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_interrupt_status, 0x08);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_interrupt_mask, 0x09);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_status, 0x0A);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_pid, 0x0B);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, misc_control, 0x0C);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, misc_status, 0x0D);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_connect_state, 0x0E);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_sof_timer_msb, 0x0F);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_ctrl, 0x40);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_status, 0x41);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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usb_ep_regs[EP0].ep_transtype_sts, 0x42);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_ctrl, 0x4C);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_status, 0x4D);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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usb_ep_regs[EP3].ep_transtype_sts, 0x4E);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_control, 0x50);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_frame_num_lsp, 0x56);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_rx_fifo_data, 0x60);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_tx_fifo_ctrl, 0x74);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl, 0x98);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
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fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_device_control, 0xE0);
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IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, port1_misc_control, 0xE8);
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/* KSCAN register structure check */
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IT8XXX2_REG_SIZE_CHECK(kscan_it8xxx2_regs, 0x0F);
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IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOL, 0x00);
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@ -445,6 +445,295 @@ struct peci_it8xxx2_regs {
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};
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#endif /* !__ASSEMBLER__ */
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/**
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*
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* (2Fxxh) USB Device Controller (USBDC) Registers
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*
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*/
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#define EP_EXT_REGS_9X 1
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#define EP_EXT_REGS_BX 2
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#define EP_EXT_REGS_DX 3
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#ifndef __ASSEMBLER__
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/* EP0 to EP15 Enumeration */
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enum usb_dc_endpoints {
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EP0,
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EP1,
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EP2,
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EP3,
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EP4,
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EP5,
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EP6,
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EP7,
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EP8,
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EP9,
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EP10,
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EP11,
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EP12,
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EP13,
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EP14,
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EP15
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};
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struct it82xx2_usb_ep_regs {
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volatile uint8_t ep_ctrl;
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volatile uint8_t ep_status;
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volatile uint8_t ep_transtype_sts;
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volatile uint8_t ep_nak_transtype_sts;
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};
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/* Reserved EP Extended Registers */
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struct ep_ext_regs_7x {
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/* 0x75 Reserved */
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volatile uint8_t ep_ext_ctrl_75;
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/* 0x76 Reserved */
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volatile uint8_t ep_ext_ctrl_76;
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/* 0x77 Reserved */
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volatile uint8_t ep_ext_ctrl_77;
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/* 0x78 Reserved */
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volatile uint8_t ep_ext_ctrl_78;
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/* 0x79 Reserved */
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volatile uint8_t ep_ext_ctrl_79;
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/* 0x7A Reserved */
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volatile uint8_t ep_ext_ctrl_7a;
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/* 0x7B Reserved */
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volatile uint8_t ep_ext_ctrl_7b;
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/* 0x7C Reserved */
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volatile uint8_t ep_ext_ctrl_7c;
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/* 0x7D Reserved */
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volatile uint8_t ep_ext_ctrl_7d;
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/* 0x7E Reserved */
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volatile uint8_t ep_ext_ctrl_7e;
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/* 0x7F Reserved */
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volatile uint8_t ep_ext_ctrl_7f;
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};
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/* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers
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* are defined, and their bits definitions are as follows:
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*
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* Bit Description
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* 7 Reserved
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* 6 EPPOINT5_ISO_ENABLE
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* 5 EPPOINT5_SEND_STALL
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* 4 EPPOINT5_OUT_DATA_SEQUENCE
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* 3 Reserved
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* 2 EPPOINT4_ISO_ENABLE
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* 1 EPPOINT4_SEND_STALL
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* 0 EPPOINT4_OUT_DATA_SEQUENCE
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*
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* Apparently, we can tell that the EP4 and EP5 share the same register, and
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* the EP6 and EP7 share the same one, and the rest EPs are defined in the
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* same way.
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*/
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struct ep_ext_regs_9x {
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/* 0x95 Reserved */
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volatile uint8_t ep_ext_ctrl_95;
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/* 0x96 Reserved */
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volatile uint8_t ep_ext_ctrl_96;
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/* 0x97 Reserved */
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volatile uint8_t ep_ext_ctrl_97;
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/* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */
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volatile uint8_t epn0n1_ext_ctrl[6];
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/* 0x9E Reserved */
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volatile uint8_t ep_ext_ctrl_9e;
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/* 0x9F Reserved */
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volatile uint8_t ep_ext_ctrl_9f;
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};
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/* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
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* definitions as as follows:
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* B8h: EP_FIFO1_CONTROL0_REG
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* B9h: EP_FIFO1_CONTROL1_REG
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* BAh: EP_FIFO2_CONTROL0_REG
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* BBh: EP_FIFO2_CONTROL1_REG
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* BCh: EP_FIFO3_CONTROL0_REG
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* BDh: EP_FIFO3_CONTROL1_REG
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*
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* For each one, its bits definitions are as follows:
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* (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15)
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*
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* Bit Description
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*
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* 7 EP15 select FIFO1 as data buffer
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* 6 EP14 select FIFO1 as data buffer
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* 5 EP13 select FIFO1 as data buffer
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* 4 EP12 select FIFO1 as data buffer
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* 3 EP11 select FIFO1 as data buffer
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* 2 EP10 select FIFO1 as data buffer
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* 1 EP9 select FIFO1 as data buffer
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* 0 EP8 select FIFO1 as data buffer
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*
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* 1: Select
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* 0: Not select
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*/
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struct ep_ext_regs_bx {
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/* 0xB5 Reserved */
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volatile uint8_t ep_ext_ctrl_b5;
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/* 0xB6 Reserved */
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volatile uint8_t ep_ext_ctrl_b6;
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/* 0xB7 Reserved */
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volatile uint8_t ep_ext_ctrl_b7;
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/* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
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volatile uint8_t ep_fifo_ctrl[6];
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/* 0xBE Reserved */
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volatile uint8_t ep_ext_ctrl_be;
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/* 0xBF Reserved */
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volatile uint8_t ep_ext_ctrl_bf;
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};
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/* From D6h to DDh are EP Extended Control Registers, and their
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* definitions as as follows:
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* D6h: EP0_EXT_CTRL1
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* D7h: EP0_EXT_CTRL2
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* D8h: EP1_EXT_CTRL1
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* D9h: EP1_EXT_CTRL2
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* DAh: EP2_EXT_CTRL1
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* DBh: EP2_EXT_CTRL2
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* DCh: EP3_EXT_CTRL1
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* DDh: EP3_EXT_CTRL2
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*
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* We classify them into 4 groups which each of them contains Control 1 and 2
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* according to the EP number as follows:
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*/
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struct epn_ext_ctrl_regs {
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/* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */
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volatile uint8_t epn_ext_ctrl1;
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/* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */
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volatile uint8_t epn_ext_ctrl2;
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};
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struct ep_ext_regs_dx {
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/* 0xD5 Reserved */
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volatile uint8_t ep_ext_ctrl_d5;
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/* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */
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struct epn_ext_ctrl_regs epn_ext_ctrl[4];
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/* 0xDE Reserved */
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volatile uint8_t ep_ext_ctrl_de;
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/* 0xDF Reserved */
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volatile uint8_t ep_ext_ctrl_df;
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};
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/* The USB EPx FIFO Registers Definitions
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* EP0: 60h ~ 74h
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* EP1: 80h ~ 94h
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* EP2: A0h ~ B4h
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* EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage)
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*/
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struct it82xx2_usb_ep_fifo_regs {
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/* 0x60 + ep * 0x20 : EP RX FIFO Data Register */
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volatile uint8_t ep_rx_fifo_data;
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/* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */
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volatile uint8_t ep_rx_fifo_dma_count;
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/* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */
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volatile uint8_t ep_rx_fifo_dcnt_msb;
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/* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */
|
||||
volatile uint8_t ep_rx_fifo_dcnt_lsb;
|
||||
/* 0x64 + ep * 0x20 : EP RX FIFO Control Register */
|
||||
volatile uint8_t ep_rx_fifo_ctrl;
|
||||
/* (0x65 ~ 0x6F) + ep * 0x20 */
|
||||
volatile uint8_t reserved_65_6f_add_20[11];
|
||||
/* 0x70 + ep * 0x20 : EP TX FIFO Data Register */
|
||||
volatile uint8_t ep_tx_fifo_data;
|
||||
/* (0x71 ~ 0x73) + ep * 0x20 */
|
||||
volatile uint8_t reserved_71_73_add_20[3];
|
||||
/* 0x74 + ep * 0x20 : EP TX FIFO Control Register */
|
||||
volatile uint8_t ep_tx_fifo_ctrl;
|
||||
/* (0x75 ~ 0x7F) + ep * 0x20 */
|
||||
union {
|
||||
struct ep_ext_regs_7x ep_res;
|
||||
struct ep_ext_regs_9x ext_4_15;
|
||||
struct ep_ext_regs_bx fifo_ctrl;
|
||||
struct ep_ext_regs_dx ext_0_3;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
struct usb_it82xx2_regs {
|
||||
/* 0x00: Host TX Contrl Register */
|
||||
volatile uint8_t host_tx_ctrl;
|
||||
/* 0x01: Host TX Transaction Type Register */
|
||||
volatile uint8_t host_tx_trans_type;
|
||||
/* 0x02: Host TX Line Control Register */
|
||||
volatile uint8_t host_tx_line_ctrl;
|
||||
/* 0x03: Host TX SOF Enable Register */
|
||||
volatile uint8_t host_tx_sof_enable;
|
||||
/* 0x04: Host TX Address Register */
|
||||
volatile uint8_t host_tx_addr;
|
||||
/* 0x05: Host TX EP Number Register */
|
||||
volatile uint8_t host_tx_endp;
|
||||
/* 0x06: Host Frame Number MSP Register */
|
||||
volatile uint8_t host_frame_num_msp;
|
||||
/* 0x07: Host Frame Number LSP Register */
|
||||
volatile uint8_t host_frame_num_lsp;
|
||||
/* 0x08: Host Interrupt Status Register */
|
||||
volatile uint8_t host_interrupt_status;
|
||||
/* 0x09: Host Interrupt Mask Register */
|
||||
volatile uint8_t host_interrupt_mask;
|
||||
/* 0x0A: Host RX Status Register */
|
||||
volatile uint8_t host_rx_status;
|
||||
/* 0x0B: Host RX PID Register */
|
||||
volatile uint8_t host_rx_pid;
|
||||
/* 0x0C: MISC Control Register */
|
||||
volatile uint8_t misc_control;
|
||||
/* 0x0D: MISC Status Register */
|
||||
volatile uint8_t misc_status;
|
||||
/* 0x0E: Host RX Connect State Register */
|
||||
volatile uint8_t host_rx_connect_state;
|
||||
/* 0x0F: Host SOF Timer MSB Register */
|
||||
volatile uint8_t host_sof_timer_msb;
|
||||
/* 0x10 ~ 0x1F: Reserved Registers 10h - 1Fh */
|
||||
volatile uint8_t reserved_10_1f[16];
|
||||
/* 0x20: Host RX FIFO Data Port Register */
|
||||
volatile uint8_t host_rx_fifo_data;
|
||||
/* 0x21: Host RX FIFO DMA Input Data Count Register */
|
||||
volatile uint8_t host_rx_fifo_dma_data_count;
|
||||
/* 0x22: Host TX FIFO Data Count MSB Register */
|
||||
volatile uint8_t host_rx_fifo_data_count_msb;
|
||||
/* 0x23: Host TX FIFO Data Count LSB Register */
|
||||
volatile uint8_t host_rx_fifo_data_count_lsb;
|
||||
/* 0x24: Host RX FIFO Data Port Register */
|
||||
volatile uint8_t host_rx_fifo_control;
|
||||
/* 0x25 ~ 0x2F: Reserved Registers 25h - 2Fh */
|
||||
volatile uint8_t reserved_25_2f[11];
|
||||
/* 0x30: Host TX FIFO Data Port Register */
|
||||
volatile uint8_t host_tx_fifo_data;
|
||||
/* 0x31 ~ 0x3F: Reserved Registers 31h - 3Fh */
|
||||
volatile uint8_t reserved_31_3f[15];
|
||||
/* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
|
||||
struct it82xx2_usb_ep_regs usb_ep_regs[4];
|
||||
/* 0x50: Device Controller Control Register */
|
||||
volatile uint8_t dc_control;
|
||||
/* 0x51: Device Controller LINE Status Register */
|
||||
volatile uint8_t dc_line_status;
|
||||
/* 0x52: Device Controller Interrupt Status Register */
|
||||
volatile uint8_t dc_interrupt_status;
|
||||
/* 0x53: Device Controller Interrupt Mask Register */
|
||||
volatile uint8_t dc_interrupt_mask;
|
||||
/* 0x54: Device Controller Address Register */
|
||||
volatile uint8_t dc_address;
|
||||
/* 0x55: Device Controller Frame Number MSP Register */
|
||||
volatile uint8_t dc_frame_num_msp;
|
||||
/* 0x56: Device Controller Frame Number LSP Register */
|
||||
volatile uint8_t dc_frame_num_lsp;
|
||||
/* 0x57 ~ 0x5F: Reserved Registers 57h - 5Fh */
|
||||
volatile uint8_t reserved_57_5f[9];
|
||||
/* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
|
||||
struct it82xx2_usb_ep_fifo_regs fifo_regs[4];
|
||||
/* 0xE0: Host/Device Control Register */
|
||||
volatile uint8_t host_device_control;
|
||||
/* 0xE1 ~ 0xE3: Reserved Registers E1h - E3h */
|
||||
volatile uint8_t reserved_e1_e3[3];
|
||||
/* 0xE4: Port0 MISC Control Register */
|
||||
volatile uint8_t port0_misc_control;
|
||||
/* 0xE5 ~ 0xE7: Reserved Registers E5h - E7h */
|
||||
volatile uint8_t reserved_e5_e7[3];
|
||||
/* 0xE8: Port1 MISC Control Register */
|
||||
volatile uint8_t port1_misc_control;
|
||||
};
|
||||
#endif /* #ifndef __ASSEMBLER__ */
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
@ -1123,70 +1412,74 @@ enum chip_pll_mode {
|
|||
|
||||
#ifndef __ASSEMBLER__
|
||||
struct gctrl_it8xxx2_regs {
|
||||
/* 0x00-0x01: Reserved1 */
|
||||
volatile uint8_t reserved1[2];
|
||||
/* 0x00-0x01: Reserved_00_01 */
|
||||
volatile uint8_t reserved_00_01[2];
|
||||
/* 0x02: Chip Version */
|
||||
volatile uint8_t GCTRL_ECHIPVER;
|
||||
/* 0x03-0x05: Reserved2 */
|
||||
volatile uint8_t reserved2[3];
|
||||
/* 0x03-0x05: Reserved_03_05 */
|
||||
volatile uint8_t reserved_03_05[3];
|
||||
/* 0x06: Reset Status */
|
||||
volatile uint8_t GCTRL_RSTS;
|
||||
/* 0x07-0x09: Reserved3 */
|
||||
volatile uint8_t reserved3[3];
|
||||
/* 0x07-0x09: Reserved_07_09 */
|
||||
volatile uint8_t reserved_07_09[3];
|
||||
/* 0x0A: Base Address Select */
|
||||
volatile uint8_t GCTRL_BADRSEL;
|
||||
/* 0x0B: Wait Next Clock Rising */
|
||||
volatile uint8_t GCTRL_WNCKR;
|
||||
/* 0x0C: Reserved4 */
|
||||
volatile uint8_t reserved4;
|
||||
/* 0x0C: reserved_0c */
|
||||
volatile uint8_t reserved_0c;
|
||||
/* 0x0D: Special Control 1 */
|
||||
volatile uint8_t GCTRL_SPCTRL1;
|
||||
/* 0x0E-0x0F: Reserved5 */
|
||||
volatile uint8_t reserved5[2];
|
||||
/* 0x0E-0x0F: reserved_0e_0f */
|
||||
volatile uint8_t reserved_0e_0f[2];
|
||||
/* 0x10: Reset Control DMM */
|
||||
volatile uint8_t GCTRL_RSTDMMC;
|
||||
/* 0x11: Reset Control 4 */
|
||||
volatile uint8_t GCTRL_RSTC4;
|
||||
/* 0x12-0x1B: Reserved6 */
|
||||
volatile uint8_t reserved6[10];
|
||||
/* 0x12-0x1B: reserved_12_1b */
|
||||
volatile uint8_t reserved_12_1b[10];
|
||||
/* 0x1C: Special Control 4 */
|
||||
volatile uint8_t GCTRL_SPCTRL4;
|
||||
/* 0x1D-0x1F: Reserved7 */
|
||||
volatile uint8_t reserved7[3];
|
||||
/* 0x1D-0x1F: reserved_1d_1f */
|
||||
volatile uint8_t reserved_1d_1f[3];
|
||||
/* 0x20: Memory Controller Configuration 3 */
|
||||
volatile uint8_t GCTRL_MCCR3;
|
||||
/* 0x21: Reset Control 5 */
|
||||
volatile uint8_t GCTRL_RSTC5;
|
||||
/* 0x22-0x2F: Reserved8 */
|
||||
volatile uint8_t reserved8[14];
|
||||
/* 0x22-0x2F: reserved_22_2f */
|
||||
volatile uint8_t reserved_22_2f[14];
|
||||
/* 0x30: Memory Controller Configuration */
|
||||
volatile uint8_t GCTRL_MCCR;
|
||||
/* 0x31: Externel ILM/DLM Size */
|
||||
volatile uint8_t GCTRL_EIDSR;
|
||||
/* 0x32-0x36: Reserved9 */
|
||||
volatile uint8_t reserved9[5];
|
||||
/* 0x32: Reserved_32 */
|
||||
volatile uint8_t reserved_32;
|
||||
/* 0x33: Pin Multi-function Enable 2 */
|
||||
volatile uint8_t gctrl_pmer2;
|
||||
/* 0x34-0x36: Reserved_34_36 */
|
||||
volatile uint8_t reserved_34_36[3];
|
||||
/* 0x37: Eflash Protect Lock */
|
||||
volatile uint8_t GCTRL_EPLR;
|
||||
/* 0x38-0x40: Reserved10 */
|
||||
volatile uint8_t reserved10[9];
|
||||
/* 0x38-0x40: Reserved_38_40 */
|
||||
volatile uint8_t reserved_38_40[9];
|
||||
/* 0x41: Interrupt Vector Table Base Address */
|
||||
volatile uint8_t GCTRL_IVTBAR;
|
||||
/* 0x42-0x43: Reserved11 */
|
||||
volatile uint8_t reserved11[2];
|
||||
/* 0x42-0x43: Reserved_42_43 */
|
||||
volatile uint8_t reserved_42_43[2];
|
||||
/* 0x44: Memory Controller Configuration 2 */
|
||||
volatile uint8_t GCTRL_MCCR2;
|
||||
/* 0x45: Reserved12 */
|
||||
volatile uint8_t reserved12;
|
||||
/* 0x45: Reserved_45 */
|
||||
volatile uint8_t reserved_45;
|
||||
/* 0x46: Pin Multi-function Enable 3 */
|
||||
volatile uint8_t GCTRL_PMER3;
|
||||
/* 0x47-0x4A: Reserved13 */
|
||||
volatile uint8_t reserved13[4];
|
||||
/* 0x47-0x4A: reserved_47_4a */
|
||||
volatile uint8_t reserved_47_4a[4];
|
||||
/* 0x4B: ETWD and UART Control */
|
||||
volatile uint8_t GCTRL_ETWDUARTCR;
|
||||
/* 0x4C: Wakeup MCU Control */
|
||||
volatile uint8_t GCTRL_WMCR;
|
||||
/* 0x4D-0x4F: Reserved14 */
|
||||
volatile uint8_t reserved14[3];
|
||||
/* 0x4D-0x4F: reserved_4d_4f */
|
||||
volatile uint8_t reserved_4d_4f[3];
|
||||
/* 0x50: Port 80h/81h Status Register */
|
||||
volatile uint8_t GCTRL_P80H81HSR;
|
||||
/* 0x51: Port 80h Data Register */
|
||||
|
|
@ -1195,12 +1488,12 @@ struct gctrl_it8xxx2_regs {
|
|||
volatile uint8_t GCTRL_P81HDR;
|
||||
/* 0x53: H2RAM Offset Register */
|
||||
volatile uint8_t GCTRL_H2ROFSR;
|
||||
/* 0x54-0x5C: Reserved15 */
|
||||
volatile uint8_t reserved15[9];
|
||||
/* 0x54-0x5C: reserved_54_5c */
|
||||
volatile uint8_t reserved_54_5c[9];
|
||||
/* 0x5D: RISCV ILM Configuration 0 */
|
||||
volatile uint8_t GCTRL_RVILMCR0;
|
||||
/* 0x5E-0x84: Reserved16 */
|
||||
volatile uint8_t reserved16[39];
|
||||
/* 0x5E-0x84: reserved_5e_84 */
|
||||
volatile uint8_t reserved_5e_84[39];
|
||||
/* 0x85: Chip ID Byte 1 */
|
||||
volatile uint8_t GCTRL_ECHIPID1;
|
||||
/* 0x86: Chip ID Byte 2 */
|
||||
|
|
@ -1239,6 +1532,10 @@ struct gctrl_it8xxx2_regs {
|
|||
#define IT8XXX2_GCTRL_ILM0_ENABLE BIT(0)
|
||||
/* Accept Port 80h Cycle */
|
||||
#define IT8XXX2_GCTRL_ACP80 BIT(6)
|
||||
/* USB Debug Enable */
|
||||
#define IT8XXX2_GCTRL_MCCR_USB_EN BIT(7)
|
||||
/* USB Pad Power-On Enable */
|
||||
#define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7)
|
||||
|
||||
/*
|
||||
* VCC Detector Option.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue