riscv: Rename Kconfig symbol to *_PRIVILEGED

Rename SOC_FAMILY_RISCV_PRIVILEGE to SOC_FAMILY_RISCV_PRIVILEGED because
the spec is "privileged".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

arch/riscv/Kconfig

@@ -280,7 +280,7 @@ config ARCH_IRQ_VECTOR_TABLE_ALIGN
 	default 256
 
 config GEN_IRQ_VECTOR_TABLE
-	select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGE
+	select RISCV_MTVEC_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGED
 
 config ARCH_HAS_SINGLE_THREAD_SUPPORT
 	default y if !SMP

drivers/interrupt_controller/intc_plic.c

@@ -40,7 +40,7 @@ static int save_irq;
  * @brief Enable a riscv PLIC-specific interrupt line
  *
  * This routine enables a RISCV PLIC-specific interrupt line.
- * riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGE
+ * riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGED
  * arch_irq_enable function to enable external interrupts for
  * IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
  *
@@ -61,7 +61,7 @@ void riscv_plic_irq_enable(uint32_t irq)
  * @brief Disable a riscv PLIC-specific interrupt line
  *
  * This routine disables a RISCV PLIC-specific interrupt line.
- * riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGE
+ * riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGED
  * arch_irq_disable function to disable external interrupts, for
  * IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
  *

include/zephyr/arch/riscv/arch.h

@@ -300,7 +300,7 @@ static inline uint64_t arch_k_cycle_get_64(void)
 
 #endif /*_ASMLANGUAGE */
 
-#if defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGE)
+#if defined(CONFIG_SOC_FAMILY_RISCV_PRIVILEGED)
 #include <zephyr/arch/riscv/riscv-privilege/asm_inline.h>
 #endif
 

include/zephyr/arch/riscv/riscv-privilege/asm_inline.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_
-#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_H_
+#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_H_
 
 /*
  * The file must not be included directly
@@ -19,4 +19,4 @@
 #error "Supports only GNU C compiler"
 #endif
 
-#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_H_ */

include/zephyr/arch/riscv/riscv-privilege/asm_inline_gcc.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_
-#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_GCC_H_
+#define ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_GCC_H_
 
 /*
  * The file must not be included directly
@@ -19,4 +19,4 @@
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGE_ASM_INLINE_GCC_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_RISCV_PRIVILEGED_ASM_INLINE_GCC_H_ */

soc/riscv/riscv-privilege/Kconfig

@@ -6,27 +6,31 @@
 
 config SOC_FAMILY_RISCV_PRIVILEGE
 	bool
+	select DEPRECATED
+
+config SOC_FAMILY_RISCV_PRIVILEGED
+	bool
 
 config SOC_FAMILY
 	string
 	default "riscv-privilege"
-	depends on SOC_FAMILY_RISCV_PRIVILEGE
+	depends on SOC_FAMILY_RISCV_PRIVILEGED
 
 config RISCV_HAS_PLIC
 	bool "Does the SOC provide support for a Platform Level Interrupt Controller (PLIC)"
-	depends on SOC_FAMILY_RISCV_PRIVILEGE
+	depends on SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Does the SOC provide support for a Platform Level Interrupt Controller (PLIC).
 
 config RISCV_HAS_CLIC
 	bool "Does the SOC provide support for a Core-Local Interrupt Controller (CLIC)"
-	depends on SOC_FAMILY_RISCV_PRIVILEGE
+	depends on SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Does the SOC provide support for a Core-Local Interrupt Controller (CLIC).
 
 config RISCV_MTVEC_VECTORED_MODE
 	bool "Should the SOC use mtvec in vectored mode"
-	depends on SOC_FAMILY_RISCV_PRIVILEGE
+	depends on SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Should the SOC use mtvec in vectored mode
 

soc/riscv/riscv-privilege/andes_v5/Kconfig.series

@@ -4,6 +4,6 @@
 config SOC_SERIES_RISCV_ANDES_V5
 	bool "Andes V5 SoC Series Implementation"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for Andes V5 SoC Series

soc/riscv/riscv-privilege/common/nuclei/nuclei_csr.h

@@ -13,8 +13,8 @@
  * Use arch/riscv/csr.h for RISC-V standard CSR and definitions.
  */
 
-#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_COMMON_NUCLEI_NUCLEI_CSR_H_
-#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_COMMON_NUCLEI_NUCLEI_CSR_H_
+#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_
+#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_
 
 #include <zephyr/sys/util_macro.h>
 
@@ -239,4 +239,4 @@ extern "C" {
 }
 #endif
 
-#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_COMMON_NUCLEI_NUCLEI_CSR_H_ */
+#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_COMMON_NUCLEI_NUCLEI_CSR_H_ */

soc/riscv/riscv-privilege/gd32vf103/Kconfig.series

@@ -6,7 +6,7 @@
 config SOC_SERIES_GD32VF103
 	bool "GigaDevice GD32VF103 series SoC implementation"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select BUILD_OUTPUT_HEX

soc/riscv/riscv-privilege/gd32vf103/pinctrl_soc.h

@@ -9,9 +9,9 @@
  * Gigadevice SoC specific helpers for pinctrl driver
  */
 
-#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
-#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
+#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_
 
 #include <zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h>
 
-#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ */
+#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ */

soc/riscv/riscv-privilege/miv/Kconfig.series

@@ -6,6 +6,6 @@
 config SOC_SERIES_RISCV32_MIV
 	bool "Microchip Mi-V implementation"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for Microchip Mi-V

soc/riscv/riscv-privilege/mpfs/Kconfig.series

@@ -6,6 +6,6 @@
 config SOC_SERIES_RISCV64_MIV
 	bool "Microchip RV64 implementation"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for Microchip RISCV 64bit

soc/riscv/riscv-privilege/neorv32/Kconfig.series

@@ -9,7 +9,7 @@ config SOC_SERIES_NEORV32
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for the NEORV32 Processor (SoC).
 

soc/riscv/riscv-privilege/niosv/Kconfig.series

@@ -4,6 +4,6 @@
 config SOC_SERIES_NIOSV
 	bool "INTEL FPGA NIOSV"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for the INTEL FPGA NIOSV.

soc/riscv/riscv-privilege/opentitan/Kconfig.series

@@ -4,7 +4,7 @@
 config SOC_SERIES_RISCV_OPENTITAN
 	bool "OpenTitan implementation"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
 	select RISCV_MTVEC_VECTORED_MODE
 	select GEN_IRQ_VECTOR_TABLE

soc/riscv/riscv-privilege/sifive-freedom/Kconfig.series

@@ -6,6 +6,6 @@
 config SOC_SERIES_RISCV_SIFIVE_FREEDOM
 	bool "SiFive Freedom SOC implementation"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for SiFive Freedom SOC

soc/riscv/riscv-privilege/sifive-freedom/pinctrl_soc.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_SIFIVE_FREEDOM_PINCTRL_H_
-#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_SIFIVE_FREEDOM_PINCTRL_H_
+#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_SIFIVE_FREEDOM_PINCTRL_H_
+#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_SIFIVE_FREEDOM_PINCTRL_H_
 
 #include <zephyr/types.h>
 
@@ -26,4 +26,4 @@ typedef struct pinctrl_soc_pin_t {
 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)		\
 	{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
 
-#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGE_SIFIVE_FREEDOM_PINCTRL_H_ */
+#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_SIFIVE_FREEDOM_PINCTRL_H_ */

soc/riscv/riscv-privilege/starfive_jh71xx/Kconfig.series

@@ -4,6 +4,6 @@
 config SOC_SERIES_STARFIVE_JH71XX
 	bool "Starfive JH71XX series"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	help
 	  Enable support for Starfive JH71XX SoC Series.

soc/riscv/riscv-privilege/telink_b91/Kconfig.series

@@ -10,7 +10,7 @@ config SOC_SERIES_RISCV_TELINK_B91
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED
 	select HAS_TELINK_DRIVERS
 	help
 	  Enable support for Telink B91 SoC

soc/riscv/riscv-privilege/virt/Kconfig.series

@@ -4,4 +4,4 @@
 config SOC_SERIES_RISCV_VIRT
 	bool "QEMU RISC-V VirtIO Board"
 	select RISCV
-	select SOC_FAMILY_RISCV_PRIVILEGE
+	select SOC_FAMILY_RISCV_PRIVILEGED

tests/kernel/gen_isr_table/testcase.yaml

@@ -51,7 +51,7 @@ tests:
       - riscv32
       - riscv64
     platform_exclude: m2gl025_miv
-    filter: CONFIG_SOC_FAMILY_RISCV_PRIVILEGE
+    filter: CONFIG_SOC_FAMILY_RISCV_PRIVILEGED
     extra_configs:
       - CONFIG_GEN_IRQ_VECTOR_TABLE=y
   arch.interrupt.gen_isr_table.riscv_no_direct:
@@ -59,6 +59,6 @@ tests:
     arch_allow:
       - riscv32
       - riscv64
-    filter: CONFIG_SOC_FAMILY_RISCV_PRIVILEGE
+    filter: CONFIG_SOC_FAMILY_RISCV_PRIVILEGED
     extra_configs:
       - CONFIG_GEN_IRQ_VECTOR_TABLE=n