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soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache

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Detect the L2 cache at runtime and removed unused Kconfig
CONFIG_SOC_ANDES_V5_L2_CACHE.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
This commit is contained in:
Jimmy Zheng 2022-07-12 15:59:40 +08:00 • committed by Fabio Baltieri
commit 97fa8407cf
3 changed files with 30 additions and 16 deletions
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2
soc/riscv/riscv-privilege/andes_v5/CMakeLists.txt
View file

@ -5,10 +5,10 @@ zephyr_include_directories(${CONFIG_SOC})
zephyr_sources(
start.S
soc_irq.S
l2_cache.c
)
zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_PMA pma.c)
zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_L2_CACHE l2_cache.c)
# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
if(CONFIG_SOC_ANDES_V5_HWDSP)

5
soc/riscv/riscv-privilege/andes_v5/Kconfig.soc
View file

@ -52,11 +52,6 @@ config CACHE_ENABLE
bool "Cache"
default n
config SOC_ANDES_V5_L2_CACHE
bool "Andes V5 L2 cache controller"
depends on CACHE_ENABLE
default y
config SOC_ANDES_V5_HWDSP
bool "AndeStar V5 DSP ISA"
select RISCV_SOC_CONTEXT_SAVE

39
soc/riscv/riscv-privilege/andes_v5/l2_cache.c
View file

@ -15,22 +15,27 @@
#include <zephyr/arch/cpu.h>
#include <soc.h>
#if DT_NODE_EXISTS(DT_INST(0, andestech_l2c))
/*
* L2C Register Base Address
*/
#define AMDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
#define ANDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
/*
* L2C Register Offset
*/
#define L2C_CONFIG 0x00
#define L2C_CTRL 0x08
/*
* L2C Helper Constant
*/
/* L2 cache version */
#define L2C_CONFIG_VERSION_SHIFT 24
/* enable L2C */
#define L2C_CTRL_CEN BIT(0)
@ -50,17 +55,28 @@
static void andes_v5_l2c_enable(void)
{
ulong_t mcache_ctl;
volatile uint64_t *l2c_ctrl =
INT_TO_POINTER(AMDES_V5_L2C_BASE + L2C_CTRL);
INT_TO_POINTER(ANDES_V5_L2C_BASE + L2C_CTRL);
/* Use largest instr/data prefetch depth by default */
uint64_t l2c_config = L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8;
__asm__ volatile ("csrr %0, %1"
: "=r" (mcache_ctl) : "i" (NDS_MCACHE_CTL));
/* Configure L2 cache */
*l2c_ctrl = l2c_config;
/* Enable L2 cache if L1 I/D cache enabled */
if (mcache_ctl & (BIT(1) | BIT(0))) {
volatile uint64_t *l2c_config =
INT_TO_POINTER(ANDES_V5_L2C_BASE + L2C_CONFIG);
/* Enable L2 cache */
*l2c_ctrl = (l2c_config | L2C_CTRL_CEN);
*l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
/* Enable L2 cache manually if device version less than 0xF0 */
if (!((*l2c_config >> L2C_CONFIG_VERSION_SHIFT) & 0xF0)) {
*l2c_ctrl |= L2C_CTRL_CEN;
}
} else {
/* Disable L2 cache */
*l2c_ctrl &= ~L2C_CTRL_CEN;
}
}
static int andes_v5_l2c_init(const struct device *dev)
@ -68,11 +84,12 @@ static int andes_v5_l2c_init(const struct device *dev)
ARG_UNUSED(dev);
#ifdef SMU_BASE
volatile uint32_t *system_cfg = INT_TO_POINTER(SMU_BASE + SMU_SYSTEMCFG);
volatile uint32_t *system_cfg =
INT_TO_POINTER(SMU_BASE + SMU_SYSTEMCFG);
if (!(*system_cfg & SMU_SYSTEMCFG_L2C)) {
/* This SoC doesn't have L2 cache */
return -1;
return -ENODEV;
}
#endif /* SMU_BASE */
@ -81,3 +98,5 @@ static int andes_v5_l2c_init(const struct device *dev)
}
SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /* DT_NODE_EXISTS(DT_INST(0, andestech_l2c)) */