soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache
Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
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500fafa921
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3 changed files with 30 additions and 16 deletions
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@ -5,10 +5,10 @@ zephyr_include_directories(${CONFIG_SOC})
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zephyr_sources(
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start.S
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soc_irq.S
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l2_cache.c
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)
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zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_PMA pma.c)
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zephyr_sources_ifdef(CONFIG_SOC_ANDES_V5_L2_CACHE l2_cache.c)
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# Note: AndeStar V5 DSP needs custom Andes V5 toolchain
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if(CONFIG_SOC_ANDES_V5_HWDSP)
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@ -52,11 +52,6 @@ config CACHE_ENABLE
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bool "Cache"
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default n
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config SOC_ANDES_V5_L2_CACHE
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bool "Andes V5 L2 cache controller"
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depends on CACHE_ENABLE
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default y
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config SOC_ANDES_V5_HWDSP
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bool "AndeStar V5 DSP ISA"
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select RISCV_SOC_CONTEXT_SAVE
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@ -15,22 +15,27 @@
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#include <zephyr/arch/cpu.h>
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#include <soc.h>
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#if DT_NODE_EXISTS(DT_INST(0, andestech_l2c))
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/*
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* L2C Register Base Address
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*/
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#define AMDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
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#define ANDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
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/*
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* L2C Register Offset
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*/
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#define L2C_CONFIG 0x00
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#define L2C_CTRL 0x08
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/*
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* L2C Helper Constant
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*/
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/* L2 cache version */
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#define L2C_CONFIG_VERSION_SHIFT 24
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/* enable L2C */
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#define L2C_CTRL_CEN BIT(0)
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@ -50,17 +55,28 @@
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static void andes_v5_l2c_enable(void)
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{
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ulong_t mcache_ctl;
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volatile uint64_t *l2c_ctrl =
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INT_TO_POINTER(AMDES_V5_L2C_BASE + L2C_CTRL);
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INT_TO_POINTER(ANDES_V5_L2C_BASE + L2C_CTRL);
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/* Use largest instr/data prefetch depth by default */
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uint64_t l2c_config = L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8;
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__asm__ volatile ("csrr %0, %1"
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: "=r" (mcache_ctl) : "i" (NDS_MCACHE_CTL));
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/* Configure L2 cache */
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*l2c_ctrl = l2c_config;
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/* Enable L2 cache if L1 I/D cache enabled */
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if (mcache_ctl & (BIT(1) | BIT(0))) {
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volatile uint64_t *l2c_config =
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INT_TO_POINTER(ANDES_V5_L2C_BASE + L2C_CONFIG);
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/* Enable L2 cache */
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*l2c_ctrl = (l2c_config | L2C_CTRL_CEN);
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*l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
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/* Enable L2 cache manually if device version less than 0xF0 */
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if (!((*l2c_config >> L2C_CONFIG_VERSION_SHIFT) & 0xF0)) {
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*l2c_ctrl |= L2C_CTRL_CEN;
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}
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} else {
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/* Disable L2 cache */
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*l2c_ctrl &= ~L2C_CTRL_CEN;
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}
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}
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static int andes_v5_l2c_init(const struct device *dev)
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@ -68,11 +84,12 @@ static int andes_v5_l2c_init(const struct device *dev)
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ARG_UNUSED(dev);
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#ifdef SMU_BASE
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volatile uint32_t *system_cfg = INT_TO_POINTER(SMU_BASE + SMU_SYSTEMCFG);
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volatile uint32_t *system_cfg =
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INT_TO_POINTER(SMU_BASE + SMU_SYSTEMCFG);
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if (!(*system_cfg & SMU_SYSTEMCFG_L2C)) {
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/* This SoC doesn't have L2 cache */
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return -1;
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return -ENODEV;
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}
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#endif /* SMU_BASE */
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@ -81,3 +98,5 @@ static int andes_v5_l2c_init(const struct device *dev)
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}
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SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* DT_NODE_EXISTS(DT_INST(0, andestech_l2c)) */
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