soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions

The RISC-V machine timer base addresses and IRQ are now obtained from
Devicetree.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

soc/riscv/riscv-privilege/andes_v5/ae350/soc.h

@@ -13,10 +13,6 @@
 
 #include <soc_common.h>
 
-/* Machine timer memory-mapped registers */
-#define RISCV_MTIME_BASE             0xE6000000
-#define RISCV_MTIMECMP_BASE          0xE6000008
-
 /* Include CSRs available for Andes V5 SoCs */
 #include "soc_v5.h"
 

soc/riscv/riscv-privilege/common/soc_common.h

@@ -14,7 +14,6 @@
 
 /* IRQ numbers */
 #define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
-#define RISCV_MACHINE_TIMER_IRQ      7  /* Machine Timer Interrupt */
 #define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
 
 /* ECALL Exception numbers */

soc/riscv/riscv-privilege/gd32vf103/soc.h

@@ -12,10 +12,5 @@
 #define RISCV_GD32VF103_SOC_H_
 
 #include <soc_common.h>
-#include <zephyr/devicetree.h>
-
-/* Timer configuration */
-#define RISCV_MTIME_BASE      DT_REG_ADDR(DT_NODELABEL(systimer))
-#define RISCV_MTIMECMP_BASE   (RISCV_MTIME_BASE + 8)
 
 #endif  /* RISCV_GD32VF103_SOC_H */

soc/riscv/riscv-privilege/miv/soc.h

@@ -9,8 +9,4 @@
 /* UART Configuration */
 #define MIV_UART_0_LINECFG           0x1
 
-/* Timer configuration */
-#define RISCV_MTIME_BASE             0x4400bff8
-#define RISCV_MTIMECMP_BASE          0x44004000
-
 #endif /* __RISCV32_MIV_SOC_H_ */

soc/riscv/riscv-privilege/mpfs/soc.h

@@ -11,8 +11,6 @@
 
 
 /* Timer configuration */
-#define RISCV_MTIME_BASE				0x0200BFF8ULL
-#define RISCV_MTIMECMP_BASE				(0x02004000ULL + (8ULL * 0))
 #define RISCV_MTIMECMP_BY_HART(h)		(0x02004000ULL + (8ULL * (h)))
 #define RISCV_MSIP_BASE					0x02000000
 

soc/riscv/riscv-privilege/neorv32/soc.h

@@ -9,10 +9,6 @@
 
 #include <soc_common.h>
 
-/* Machine System Timer (MTIME) registers */
-#define RISCV_MTIME_BASE    0xffffff90U
-#define RISCV_MTIMECMP_BASE 0xffffff98U
-
 /* System information (SYSINFO) register offsets */
 #define NEORV32_SYSINFO_CLK         0x00U
 #define NEORV32_SYSINFO_CPU         0x04U

soc/riscv/riscv-privilege/sifive-freedom/soc.h

@@ -50,8 +50,4 @@
 
 #endif
 
-/* Timer configuration */
-#define RISCV_MTIME_BASE             0x0200BFF8
-#define RISCV_MTIMECMP_BASE          0x02004000
-
 #endif /* __RISCV_SIFIVE_FREEDOM_SOC_H_ */

soc/riscv/riscv-privilege/starfive_jh71xx/soc.h

@@ -9,7 +9,4 @@
 
 #include <soc_common.h>
 
-#define RISCV_MTIME_BASE 0x0200BFF8
-#define RISCV_MTIMECMP_BASE 0x02004000
-
 #endif

soc/riscv/riscv-privilege/telink_b91/soc.h

@@ -9,8 +9,4 @@
 
 #include <soc_common.h>
 
-/* Machine timer memory-mapped registers */
-#define RISCV_MTIME_BASE             0xE6000000
-#define RISCV_MTIMECMP_BASE          0xE6000008
-
 #endif /* RISCV_TELINK_B91_SOC_H */

soc/riscv/riscv-privilege/virt/soc.h

@@ -10,8 +10,6 @@
 #include <soc_common.h>
 
 #define SIFIVE_SYSCON_TEST           0x00100000
-#define RISCV_MTIME_BASE             0x0200BFF8
-#define RISCV_MTIMECMP_BASE          0x02004000
 #define RISCV_MSIP_BASE              0x02000000
 
 #endif