soc: riscv: remove unused RISCV_MTIME(CMP)_BASE and IRQ definitions
The RISC-V machine timer base addresses and IRQ are now obtained from Devicetree. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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10 changed files with 0 additions and 33 deletions
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@ -13,10 +13,6 @@
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#include <soc_common.h>
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/* Machine timer memory-mapped registers */
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#define RISCV_MTIME_BASE 0xE6000000
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#define RISCV_MTIMECMP_BASE 0xE6000008
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/* Include CSRs available for Andes V5 SoCs */
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#include "soc_v5.h"
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@ -14,7 +14,6 @@
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/* IRQ numbers */
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#define RISCV_MACHINE_SOFT_IRQ 3 /* Machine Software Interrupt */
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#define RISCV_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
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#define RISCV_MACHINE_EXT_IRQ 11 /* Machine External Interrupt */
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/* ECALL Exception numbers */
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@ -12,10 +12,5 @@
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#define RISCV_GD32VF103_SOC_H_
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#include <soc_common.h>
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#include <zephyr/devicetree.h>
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/* Timer configuration */
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#define RISCV_MTIME_BASE DT_REG_ADDR(DT_NODELABEL(systimer))
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#define RISCV_MTIMECMP_BASE (RISCV_MTIME_BASE + 8)
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#endif /* RISCV_GD32VF103_SOC_H */
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@ -9,8 +9,4 @@
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/* UART Configuration */
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#define MIV_UART_0_LINECFG 0x1
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/* Timer configuration */
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#define RISCV_MTIME_BASE 0x4400bff8
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#define RISCV_MTIMECMP_BASE 0x44004000
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#endif /* __RISCV32_MIV_SOC_H_ */
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@ -11,8 +11,6 @@
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/* Timer configuration */
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#define RISCV_MTIME_BASE 0x0200BFF8ULL
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#define RISCV_MTIMECMP_BASE (0x02004000ULL + (8ULL * 0))
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#define RISCV_MTIMECMP_BY_HART(h) (0x02004000ULL + (8ULL * (h)))
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#define RISCV_MSIP_BASE 0x02000000
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@ -9,10 +9,6 @@
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#include <soc_common.h>
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/* Machine System Timer (MTIME) registers */
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#define RISCV_MTIME_BASE 0xffffff90U
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#define RISCV_MTIMECMP_BASE 0xffffff98U
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/* System information (SYSINFO) register offsets */
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#define NEORV32_SYSINFO_CLK 0x00U
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#define NEORV32_SYSINFO_CPU 0x04U
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@ -50,8 +50,4 @@
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#endif
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/* Timer configuration */
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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#endif /* __RISCV_SIFIVE_FREEDOM_SOC_H_ */
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@ -9,7 +9,4 @@
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#include <soc_common.h>
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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#endif
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#include <soc_common.h>
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/* Machine timer memory-mapped registers */
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#define RISCV_MTIME_BASE 0xE6000000
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#define RISCV_MTIMECMP_BASE 0xE6000008
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#endif /* RISCV_TELINK_B91_SOC_H */
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#include <soc_common.h>
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#define SIFIVE_SYSCON_TEST 0x00100000
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#define RISCV_MTIME_BASE 0x0200BFF8
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#define RISCV_MTIMECMP_BASE 0x02004000
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#define RISCV_MSIP_BASE 0x02000000
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#endif
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