soc: riscv: riscv-privilege: Add support for OpenTitan SOC

Add support for OpenTitan, an open source silicon root of trust.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>

soc/riscv/riscv-privilege/opentitan/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c rom_header.S)
+
+zephyr_linker_sources(ROM_START SORT_KEY 000romheader rom_header.ld)

soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series

@@ -0,0 +1,34 @@
+# Copyright (c) 2023 Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RISCV_OPENTITAN
+
+config SOC_SERIES
+	default "opentitan"
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1000000
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+config RISCV_HAS_CPU_IDLE
+	default y
+
+config RISCV_HAS_PLIC
+	default y
+
+config RISCV_GP
+	default y
+
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 32
+
+config NUM_IRQS
+	default 216
+
+config FLASH_BASE_ADDRESS
+	hex
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+endif # SOC_SERIES_RISCV_OPENTITAN

soc/riscv/riscv-privilege/opentitan/Kconfig.series

@@ -0,0 +1,12 @@
+# Copyright (c) 2023 Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RISCV_OPENTITAN
+	bool "OpenTitan implementation"
+	select RISCV
+	select SOC_FAMILY_RISCV_PRIVILEGE
+	# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
+	select RISCV_MTVEC_VECTORED_MODE
+	select GEN_IRQ_VECTOR_TABLE
+	help
+	  Enable support for OpenTitan

soc/riscv/riscv-privilege/opentitan/Kconfig.soc

@@ -0,0 +1,22 @@
+# Copyright (c) 2023 Rivos Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+choice
+	prompt "OpenTitan implementation"
+	depends on SOC_SERIES_RISCV_OPENTITAN
+
+config SOC_RISCV_OPENTITAN
+	bool "OpenTitan implementation"
+	select ATOMIC_OPERATIONS_C
+	select INCLUDE_RESET_VECTOR
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ISA_EXT_ZBA
+	select RISCV_ISA_EXT_ZBB
+	select RISCV_ISA_EXT_ZBC
+	select RISCV_ISA_EXT_ZBS
+
+endchoice

soc/riscv/riscv-privilege/opentitan/linker.ld

@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <zephyr/arch/riscv/common/linker.ld>

soc/riscv/riscv-privilege/opentitan/rom_header.S

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2023 Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+/* imports */
+GTEXT(__start)
+
+/* OpenTitan manifest consists of 896 bytes (224 words) containing signature,
+ * device ID, version info, etc. The test ROM ignores all of these fields
+ * except for entry point (final word in manifest).
+ */
+SECTION_FUNC(rom_header, __rom_header)
+	.rept(223)
+	.word 0
+	.endr
+	/* Entry point is relative to the beginning of manifest. */
+	.word(__start - __rom_header)

soc/riscv/riscv-privilege/opentitan/rom_header.ld

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2023 Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+KEEP(*(.rom_header.*))

soc/riscv/riscv-privilege/opentitan/soc.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2023 Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+
+#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
+
+static int soc_opentitan_init(const struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* Initialize the Machine Timer, so it behaves as a regular one. */
+	sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
+	/* Enable timer interrupts. */
+	sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
+	return 0;
+}
+SYS_INIT(soc_opentitan_init, PRE_KERNEL_1, 0);

soc/riscv/riscv-privilege/opentitan/soc.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023 Rivos Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV_OPENTITAN_SOC_H_
+#define __RISCV_OPENTITAN_SOC_H_
+
+#include <soc_common.h>
+#include <zephyr/devicetree.h>
+
+/* Ibex timer registers. */
+#define RV_TIMER_CTRL_REG_OFFSET        0x004
+#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
+#define RV_TIMER_CFG0_REG_OFFSET        0x10c
+#define RV_TIMER_CFG0_PRESCALE_MASK     0xfff
+#define RV_TIMER_CFG0_PRESCALE_OFFSET   0
+#define RV_TIMER_CFG0_STEP_MASK         0xff
+#define RV_TIMER_CFG0_STEP_OFFSET       16
+#define RV_TIMER_LOWER0_OFFSET          0x110
+#define RV_TIMER_COMPARE_LOWER0_OFFSET  0x118
+
+#endif /* __RISCV_OPENTITAN_SOC_H_ */