soc: riscv: riscv-privilege: Add support for OpenTitan SOC
Add support for OpenTitan, an open source silicon root of trust. Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
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9 changed files with 151 additions and 0 deletions
5
soc/riscv/riscv-privilege/opentitan/CMakeLists.txt
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soc/riscv/riscv-privilege/opentitan/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c rom_header.S)
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zephyr_linker_sources(ROM_START SORT_KEY 000romheader rom_header.ld)
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34
soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
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soc/riscv/riscv-privilege/opentitan/Kconfig.defconfig.series
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# Copyright (c) 2023 Rivos Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RISCV_OPENTITAN
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config SOC_SERIES
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default "opentitan"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 1000000
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_HAS_CPU_IDLE
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default y
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config RISCV_HAS_PLIC
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default y
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config RISCV_GP
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default y
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config 2ND_LVL_ISR_TBL_OFFSET
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default 32
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config NUM_IRQS
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default 216
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config FLASH_BASE_ADDRESS
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hex
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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endif # SOC_SERIES_RISCV_OPENTITAN
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12
soc/riscv/riscv-privilege/opentitan/Kconfig.series
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soc/riscv/riscv-privilege/opentitan/Kconfig.series
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# Copyright (c) 2023 Rivos Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RISCV_OPENTITAN
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bool "OpenTitan implementation"
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select RISCV
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select SOC_FAMILY_RISCV_PRIVILEGE
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# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
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select RISCV_MTVEC_VECTORED_MODE
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select GEN_IRQ_VECTOR_TABLE
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help
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Enable support for OpenTitan
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soc/riscv/riscv-privilege/opentitan/Kconfig.soc
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soc/riscv/riscv-privilege/opentitan/Kconfig.soc
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# Copyright (c) 2023 Rivos Inc.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "OpenTitan implementation"
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depends on SOC_SERIES_RISCV_OPENTITAN
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config SOC_RISCV_OPENTITAN
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bool "OpenTitan implementation"
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select ATOMIC_OPERATIONS_C
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZBA
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select RISCV_ISA_EXT_ZBB
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select RISCV_ISA_EXT_ZBC
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select RISCV_ISA_EXT_ZBS
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endchoice
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3
soc/riscv/riscv-privilege/opentitan/linker.ld
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soc/riscv/riscv-privilege/opentitan/linker.ld
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/* SPDX-License-Identifier: Apache-2.0 */
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#include <zephyr/arch/riscv/common/linker.ld>
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soc/riscv/riscv-privilege/opentitan/rom_header.S
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soc/riscv/riscv-privilege/opentitan/rom_header.S
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/*
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* Copyright (c) 2023 Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/toolchain.h>
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/* imports */
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GTEXT(__start)
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/* OpenTitan manifest consists of 896 bytes (224 words) containing signature,
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* device ID, version info, etc. The test ROM ignores all of these fields
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* except for entry point (final word in manifest).
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*/
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SECTION_FUNC(rom_header, __rom_header)
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.rept(223)
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.word 0
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.endr
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/* Entry point is relative to the beginning of manifest. */
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.word(__start - __rom_header)
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soc/riscv/riscv-privilege/opentitan/rom_header.ld
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soc/riscv/riscv-privilege/opentitan/rom_header.ld
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/*
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* Copyright (c) 2023 Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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KEEP(*(.rom_header.*))
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soc/riscv/riscv-privilege/opentitan/soc.c
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soc/riscv/riscv-privilege/opentitan/soc.c
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/*
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* Copyright (c) 2023 Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/init.h>
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#define RV_TIMER_BASE (DT_REG_ADDR(DT_NODELABEL(mtimer)))
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static int soc_opentitan_init(const struct device *arg)
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{
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ARG_UNUSED(arg);
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/* Initialize the Machine Timer, so it behaves as a regular one. */
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sys_write32(1u, RV_TIMER_BASE + RV_TIMER_CTRL_REG_OFFSET);
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/* Enable timer interrupts. */
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sys_write32(1u, RV_TIMER_BASE + RV_TIMER_INTR_ENABLE_REG_OFFSET);
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return 0;
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}
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SYS_INIT(soc_opentitan_init, PRE_KERNEL_1, 0);
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soc/riscv/riscv-privilege/opentitan/soc.h
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soc/riscv/riscv-privilege/opentitan/soc.h
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/*
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* Copyright (c) 2023 Rivos Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __RISCV_OPENTITAN_SOC_H_
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#define __RISCV_OPENTITAN_SOC_H_
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#include <soc_common.h>
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#include <zephyr/devicetree.h>
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/* Ibex timer registers. */
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#define RV_TIMER_CTRL_REG_OFFSET 0x004
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#define RV_TIMER_INTR_ENABLE_REG_OFFSET 0x100
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#define RV_TIMER_CFG0_REG_OFFSET 0x10c
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#define RV_TIMER_CFG0_PRESCALE_MASK 0xfff
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#define RV_TIMER_CFG0_PRESCALE_OFFSET 0
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#define RV_TIMER_CFG0_STEP_MASK 0xff
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#define RV_TIMER_CFG0_STEP_OFFSET 16
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#define RV_TIMER_LOWER0_OFFSET 0x110
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#define RV_TIMER_COMPARE_LOWER0_OFFSET 0x118
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#endif /* __RISCV_OPENTITAN_SOC_H_ */
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