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soc: remove intel_adsp_cavs15

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Remove SoC for cavs15.
Support for this platform was removed in SOF.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2023-04-05 21:33:00 +00:00 • committed by Carles Cufí
commit d2cf740e68
3 changed files with 1 additions and 64 deletions
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48
soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15
View file

@ -1,48 +0,0 @@
# Copyright (c) 2020 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_CAVS_V15
config SOC_TOOLCHAIN_NAME
string
default "intel_apl_adsp"
config SOC
default "intel_apl_adsp"
# For backward compatibility, to be removed
config SOC_SERIES_INTEL_CAVS_V15
def_bool y
config HP_SRAM_RESERVE
default 32768
config MP_MAX_NUM_CPUS
default 2
config SCHED_IPI_SUPPORTED
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if XTENSA_TIMER
default 19200000 if INTEL_ADSP_TIMER
if DAI_INTEL_SSP
config DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING
default y
config DAI_INTEL_SSP_NUM_BASE
default 4
config DAI_INTEL_SSP_NUM_EXT
default 2
endif # DAI_INTEL_SSP
config ADSP_INIT_HPSRAM
default n
config ADSP_DISABLE_L2CACHE_AT_BOOT
default y
endif

3
soc/xtensa/intel_adsp/cavs/Kconfig.soc
View file

@ -5,9 +5,6 @@ choice
prompt "Intel CAVS SoC Selection"
depends on SOC_SERIES_INTEL_ADSP_CAVS
config SOC_INTEL_CAVS_V15
bool "Intel Apollo Lake"
config SOC_INTEL_CAVS_V18
bool "Intel Cannon Lake"
select XTENSA_WAITI_BUG

14
soc/xtensa/intel_adsp/cavs/multiprocessing.c
View file

@ -19,8 +19,6 @@
#define IDC_CORE_MASK(num_cpus) (BIT(num_cpus) - 1)
#define CAVS15_ROM_IDC_DELAY 500
__imr void soc_mp_startup(uint32_t cpu)
{
/* We got here via an IDC interrupt. Clear the TFC high bit
@ -93,19 +91,9 @@ void soc_start_core(int cpu_num)
* turn itself off when it gets to the WAITI instruction in
* the idle thread.
*/
if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V15)) {
CAVS_SHIM.clkctl |= CAVS_CLKCTL_TCPLCG(cpu_num);
}
CAVS_SHIM.clkctl |= CAVS_CLKCTL_TCPLCG(cpu_num);
CAVS_SHIM.pwrctl |= CAVS_PWRCTL_TCPDSPPG(cpu_num);
/* Older devices boot from a ROM and needs some time to
* complete initialization and be waiting for the IDC we're
* about to send.
*/
if (!IS_ENABLED(CONFIG_SOC_INTEL_CAVS_V25)) {
k_busy_wait(CAVS15_ROM_IDC_DELAY);
}
/* We set the interrupt controller up already, but the ROM on
* some platforms will mess it up.
*/