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soc: arm: nxp_imx: use CMSIS SystemInit for all NXP iMX.RT SOCs

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Use CMSIS SystemInit for all NXP iMX.RT SOCs, to simplify initialization
flow, and remove redundant code where possible.

Introduce Kconfigs to disable Cache at boot, since SystemInit will enable
code cache on these platforms, which may be undesirable behavior.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-11-30 16:08:08 -06:00 • committed by Carles Cufí
commit 24b66b30eb
8 changed files with 68 additions and 76 deletions
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13
soc/arm/nxp_imx/rt/Kconfig.soc
View file

@ -614,6 +614,7 @@ config SOC_SERIES_IMX_RT10XX
config SOC_SERIES_IMX_RT11XX
bool "i.MX RT 11XX Series"
select PLATFORM_SPECIFIC_INIT
config INIT_ARM_PLL
bool "Initialize ARM PLL"
@ -749,4 +750,16 @@ config SECOND_CORE_MCUX
generated header specifying the VMA and LMA of each memory section
to load
config IMXRT1XXX_CODE_CACHE
bool "Code cache"
default y
help
Enable Code cache at boot for IMXRT1xxx series
config IMXRT1XXX_DATA_CACHE
bool "Data cache"
default y
help
Enable Data cache at boot for IMXRT1xxx series
endif # SOC_SERIES_IMX_RT

13
soc/arm/nxp_imx/rt/soc_rt10xx.c
View file

@ -290,8 +290,17 @@ static int imxrt_init(const struct device *arg)
/* disable interrupts */
oldLevel = irq_lock();
if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
SCB_EnableDCache();
#ifndef CONFIG_IMXRT1XXX_CODE_CACHE
/* SystemInit enables code cache, disable it here */
SCB_DisableICache();
#endif
if (IS_ENABLED(CONFIG_IMXRT1XXX_DATA_CACHE)) {
if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
SCB_EnableDCache();
}
} else {
SCB_DisableDCache();
}
/* Initialize system clock */

51
soc/arm/nxp_imx/rt/soc_rt11xx.c
View file

@ -631,10 +631,6 @@ static int imxrt_init(const struct device *arg)
/* disable interrupts */
oldLevel = irq_lock();
/* Disable Systick which might be enabled by bootrom */
if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0) {
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
}
#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7)
/**
@ -659,47 +655,19 @@ static int imxrt_init(const struct device *arg)
MU_SetFlags(MU_BASE, BOOT_FLAG);
#endif
#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7)
if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
SCB_EnableICache();
}
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
SCB_EnableDCache();
}
#ifndef CONFIG_IMXRT1XXX_CODE_CACHE
/* SystemInit enables code cache, disable it here */
SCB_DisableICache();
#endif
#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4)
/* Initialize Cache */
/* Enable Code Bus Cache */
if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) {
/*
* set command to invalidate all ways,
* and write GO bit to initiate command
*/
LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK
| LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_GO_MASK;
/* Wait until the command completes */
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
if (IS_ENABLED(CONFIG_IMXRT1XXX_DATA_CACHE)) {
if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
SCB_EnableDCache();
}
/* Enable cache, enable write buffer */
LMEM->PCCCR |= (LMEM_PCCCR_ENWRBUF_MASK
| LMEM_PCCCR_ENCACHE_MASK);
}
/* Enable System Bus Cache */
if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK)) {
/*
* set command to invalidate all ways,
* and write GO bit to initiate command
*/
LMEM->PSCCR |= LMEM_PSCCR_INVW1_MASK
| LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_GO_MASK;
/* Wait until the command completes */
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
}
/* Enable cache, enable write buffer */
LMEM->PSCCR |= (LMEM_PSCCR_ENWRBUF_MASK
| LMEM_PSCCR_ENCACHE_MASK);
} else {
SCB_DisableDCache();
}
#endif
@ -728,6 +696,7 @@ void z_arm_platform_init(void)
/* Zero BSS region */
memset(&__ocram_bss_start, 0, (&__ocram_bss_end - &__ocram_bss_start));
#endif
SystemInit();
}
#endif

4
soc/arm/nxp_imx/rt5xx/Kconfig.soc
View file

@ -103,8 +103,8 @@ config IMAGE_VECTOR_TABLE_OFFSET
endif # NXP_IMX_RT5XX_BOOT_HEADER
config IMXRT5XX_ENABLE_CODE_CACHE
bool "Enable code cache"
config IMXRT5XX_CODE_CACHE
bool "Code cache"
default y
help
Enable code cache for FlexSPI region at boot. If this Kconfig is

2
soc/arm/nxp_imx/rt5xx/soc.c
View file

@ -375,7 +375,7 @@ static int nxp_rt500_init(const struct device *arg)
*/
NMI_INIT();
#ifndef CONFIG_IMXRT5XX_ENABLE_CODE_CACHE
#ifndef CONFIG_IMXRT5XX_CODE_CACHE
CACHE64_DisableCache(CACHE64_CTRL0);
#endif

1
soc/arm/nxp_imx/rt6xx/Kconfig.series
View file

@ -11,5 +11,6 @@ config SOC_SERIES_IMX_RT6XX
select SOC_FAMILY_IMX
select CLOCK_CONTROL
select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP
select PLATFORM_SPECIFIC_INIT
help
Enable support for i.MX RT6XX Series MCU series

4
soc/arm/nxp_imx/rt6xx/Kconfig.soc
View file

@ -109,8 +109,8 @@ config IMAGE_VECTOR_TABLE_OFFSET
endif # NXP_IMX_RT6XX_BOOT_HEADER
config IMXRT6XX_ENABLE_CODE_CACHE
bool "Enable code cache"
config IMXRT6XX_CODE_CACHE
bool "Code cache"
default y
help
Enable code cache for FlexSPI region at boot. If this Kconfig is

56
soc/arm/nxp_imx/rt6xx/soc.c
View file

@ -77,11 +77,11 @@ const clock_audio_pll_config_t g_audioPllConfig = {
/* System clock frequency. */
extern uint32_t SystemCoreClock;
/* Main stack pointer */
extern char z_main_stack[];
#ifdef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
extern char z_main_stack[];
extern char _flash_used[];
extern void z_arm_reset(void);
extern void z_arm_nmi(void);
extern void z_arm_hard_fault(void);
@ -352,31 +352,6 @@ static int nxp_rt600_init(const struct device *arg)
/* disable interrupts */
oldLevel = irq_lock();
/* Enable cache to accelerate boot. */
if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL->POLSEL == 0)) {
/*
* Set command to invalidate all ways and write GO bit
* to initiate command
*/
CACHE64->CCR = (CACHE64_CTRL_CCR_INVW1_MASK |
CACHE64_CTRL_CCR_INVW0_MASK);
CACHE64->CCR |= CACHE64_CTRL_CCR_GO_MASK;
/* Wait until the command completes */
while (CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) {
}
/* Enable cache, enable write buffer */
CACHE64->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK |
CACHE64_CTRL_CCR_ENCACHE_MASK);
/* Set whole FlexSPI0 space to write through. */
CACHE64_POLSEL->REG0_TOP = 0x07FFFC00U;
CACHE64_POLSEL->REG1_TOP = 0x0U;
CACHE64_POLSEL->POLSEL = 0x1U;
__ISB();
__DSB();
}
/* Initialize clock */
clock_init();
@ -386,7 +361,7 @@ static int nxp_rt600_init(const struct device *arg)
*/
NMI_INIT();
#ifndef CONFIG_IMXRT6XX_ENABLE_CODE_CACHE
#ifndef CONFIG_IMXRT6XX_CODE_CACHE
CACHE64_DisableCache(CACHE64);
#endif
@ -396,4 +371,29 @@ static int nxp_rt600_init(const struct device *arg)
return 0;
}
#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
void z_arm_platform_init(void)
{
#ifndef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER
/*
* If boot did not proceed using a boot header, we should not assume
* the core is in reset state. Disable the MPU and correctly
* set the stack pointer, since we are about to push to
* the stack when we call SystemInit
*/
/* Clear stack limit registers */
__set_MSPLIM(0);
__set_PSPLIM(0);
/* Disable MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
/* Set stack pointer */
__set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE));
#endif /* !CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */
/* This is provided by the SDK */
SystemInit();
}
#endif
SYS_INIT(nxp_rt600_init, PRE_KERNEL_1, 0);