Revert "xtensa: remove ELF section address rewriting"
This reverts commit 7a85983ebc
.
This commit was merged prematurely and is causing issues on multiple
platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
b0e6a6f8a7
commit
0f2a352cbd
2 changed files with 55 additions and 0 deletions
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@ -30,6 +30,7 @@ zephyr_library_link_libraries(INTEL_ADSP_COMMON)
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target_include_directories(INTEL_ADSP_COMMON INTERFACE include)
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target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common)
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set(ELF_FIX ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/fix_elf_addrs.py)
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set(KERNEL_REMAPPED ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}-remapped.elf)
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set(EXTMAN ${CMAKE_BINARY_DIR}/zephyr/extman.bin)
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@ -73,6 +74,9 @@ add_custom_command(
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COMMAND ${CMAKE_COMMAND} -E
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copy ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${KERNEL_REMAPPED}
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COMMAND ${ELF_FIX} ${CMAKE_OBJCOPY} ${KERNEL_REMAPPED}
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${CONFIG_XTENSA_CACHED_REGION} ${CONFIG_XTENSA_UNCACHED_REGION}
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# Extract modules for rimage
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COMMAND ${CMAKE_OBJCOPY}
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--only-section .imr
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51
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
Executable file
51
soc/xtensa/intel_adsp/common/fix_elf_addrs.py
Executable file
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@ -0,0 +1,51 @@
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#!/usr/bin/env python3
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#
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# Copyright (c) 2020-2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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# ADSP devices have their RAM regions mapped twice. The first mapping
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# is set in the CPU to bypass the L1 cache, and so access through
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# pointers in that region is coherent between CPUs (but slow). The
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# second region accesses the same memory through the L1 cache and
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# requires careful flushing when used with shared data.
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#
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# This distinction is exposed in the linker script, where some symbols
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# (e.g. stack regions) are linked into cached memory, but others
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# (general kernel memory) are not. But the rimage signing tool
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# doesn't understand that and fails if regions aren't contiguous.
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#
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# Walk the sections in the ELF file, changing the VMA/LMA of each
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# uncached section to the equivalent address in the cached area of
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# memory.
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import os
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import sys
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from elftools.elf.elffile import ELFFile
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objcopy_bin = sys.argv[1]
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elffile = sys.argv[2]
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cached_reg = int(sys.argv[3])
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uncached_reg = int(sys.argv[4])
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uc_min = uncached_reg << 29
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uc_max = uc_min | 0x1fffffff
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cache_off = "0x%x" % ((cached_reg - uncached_reg) << 29)
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fixup =[]
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with open(elffile, "rb") as fd:
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elf = ELFFile(fd)
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for s in elf.iter_sections():
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addr = s.header.sh_addr
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if uc_min <= addr <= uc_max and s.header.sh_size != 0:
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print(f"fix_elf_addrs.py: Moving section {s.name} to cached SRAM region")
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fixup.append(s.name)
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for s in fixup:
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# Note redirect: the sof-derived linker scripts currently emit
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# some zero-length sections at address zero. This is benign, and
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# the linker is happy, but objcopy will emit an unsilenceable
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# error (no --quiet option, no -Werror=no-whatever, nothing).
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# Just swallow the error stream for now pending rework to the
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# linker framework.
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cmd = f"{objcopy_bin} --change-section-address {s}+{cache_off} {elffile} 2>{os.devnull}"
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os.system(cmd)
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