The various linker scripts on arc would include autoconf.h in the arch
linker script but might have CONFIG_ symbols referenced in the soc
specific linker script. Move autoconf.h inclusion to top of the soc
specific linker script out of the arch specific one so we know
autoconf.h is seen before any CONFIG_ references.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The early boot watchdog init for kinetis was incorrectly disabling and
reenabling interrupts to preserve timing during the unlock sequence.
However, interrupts are already disabled before this routine executes
and the kernel is not yet ready to enable them when this routine exits.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adds a flash driver for the STM32F7x series, inspired from
the STM32F4x one. It has been tested on the STM32F723, but should also
work on other SoCs of the family.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This patch cleans up the code in the recently added dts_fixup.h,
restoring the original alignment of the file.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
The dts.fixup for v2m_beetle contains a wrong setting for the IRQ fixup
for the Dual Timer IRQ.
This patch fixes the symbol included in the generated header.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This commit simplifies Kconfig options related to handling SoC series,
part numbers. This is a first step required to add remaining part
numbers to the existing configuration.
This change is possible since all SiLabs SoCs within a single series
have a very uniform structure.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
All text, data and bss sections are all mapped to the same physical
memory (SRAM). This patch removes the individual section limits
and defines a common limit for the sum of text, data and bss sections.
This would make it more flexible for application developers.
Fixes#11268.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
CONFIG_TEXT_SECTION_OFFSET allows the entire image to be moved
in memory to allow space for some type of header. The mcubootloader
can boot only such images which reserve some space for the header.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
RISC-V permits myriad extensions to the ISA, any of which may imply
additional context that must be saved and restored on ISR entry and
exit. The current in-tree example is the Pulpino core, which has extra
registers used by ISA extensions for running loops that shouldn't get
clobbered by an ISR.
This is currently supported by including pulpino-specific definitions
in the generic architecture code. This works, but it's a bit inelegant
and is something of a layering violation. A more generic mechanism is
required to support other RISC-V SoCs with similar requirements
without cluttering the arch code too much.
Provide that by extending the semantics of the existing
CONFIG_RISCV_SOC_CONTEXT_SAVE option to allow other SoCs to allocate
space for saving and restoring their own state, promoting the
currently pulpino-specific __soc_save_context / __soc_restore_context
routines to a RISC-V arch API.
The cost of making this generic is two more instructions in each ISR
to pass the SoC specific context to these routines in a0 rather than
just assuming the stack points to the right place. This is minimal,
and should have been done anyway to keep with the ABI.
As a first (and currently only in-tree) customer, convert the Pulpino
SoC code to this new mechanism.
Signed-off-by: Marti Bolivar <marti@foundries.io>
The driver can be tested using different networking emulation
approaches.
This approach will work across multiple Qemu instances. There can be
more than one Qemu instance, run using the following command. They
would appear to be on the same Ethernet network.
$ qemu-system-arm -M lm3s6965evb \
-serial stdio \
-net nic \
-net socket,mcast=230.0.0.1:1234 \
-kernel zephyr.elf
This approach will work with other virtualization technologies that
support connecting to a VDE switch, like VirtualBox and User Mode
Linux. The switch can be started using the following command.
$ vde_switch --sock /tmp/switch
Qemu can be connected to the switch using the following command.
$ qemu-system-arm -M lm3s6965evb \
-serial stdio \
-net nic \
-net vde,sock=/tmp/switch \
-kernel zephyr.elf
Signed-off-by: Fadhel Habeeb <fadhel@zilogic.com>
Signed-off-by: Nirav Parmar <niravparmar@zilogic.com>
Signed-off-by: Vijay Kumar B <vijaykumar@zilogic.com>
Add configuration values for HAS_HW_NRF_BPROT and HAS_HW_NRF_MPU.
Select these configurations where applicable.
Signed-off-by: Håkon Øye Amundsen <haakon.amundsen@nordicsemi.no>
Since pinmux configuration is board dependent and is now under
boards/xtensa/intel_s1000, the configuration in soc.c is removed.
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
Within a single series pin mapping between location setting and pin name
is uniform. The only difference is availability of the module, i.e. i2c1
may be missing on some part numbers, or availability of the pin, i.e.
32 pin package will not provide all the pins available on 48 pin
package. It's better to manage these differences at the DTS/Kconfig
level.
This commit removes dependency of soc_pinmap.h files on part numbers.
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
There were many platforms where this function was doing nothing. Just
merging its functionality with _PrepC function.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Implementation taken from Nordic nrfx version 1.3.1 soc/nrfx_coredep.h,
modified to remove material from other series and to conform to Zephyr
coding standards.
Note that unlike standard k_busy_wait this is susceptible to
longer-than-intended delays due to the impact of interrupt handling.
Fixes#11626
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The Cortex-M7 CPU included in the SAM e70 SoCs has a data cache that
significantly boost the performances. However the SAM GMAC Ethernet
driver is using a scatter-gather technique to exchange data with the
Ethernet driver. This requires the use use of a non-cached memory area.
This is currently not supported on Zephyr, but support for it is being
discussed in PR#11199.
In the meantime, enable the data cache during the SoC initialization,
unless the SAM GMAC Ethernet driver is enabled.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The Cortex-M7 CPU included in the SAM e70 SoCs has an instruction cache
that significantly boost the performances. Enable it during the SoC
initialization.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The Silicon Labs EFM32 Pearl Gecko MCU includes:
* Cortex-M4F core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* multiple low power peripherals
Ported from EFM32WG:
https://www.silabs.com/documents/public/application-notes/an0918.0-efm32_to_efm32jgpg_migration_guide.pdf
Signed-off-by: Gil Benkö <gil.benkoe@pm.me>
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Declare and define nxp_mpu_config and nxp_mpu_regions
structs as const, as they are not modified in run-time.
Fixes#10320
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Declare and define arm_mpu_config and arm_mpu_regions
structs as const, as they are not modified in run-time.
Fixes#10320
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When users are configuring applications they are given the option
to enable the DesignWare SPI driver. But they should not be given this
option on SoCs that don't have the DesignWare SPI HW.
This commit hides the driver by default by introducing the config
option HAS_SPI_DW.
Fixes: #10825
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds support for STM32L471xG. Since STM32L475 only adds
USB, stm32l475.dtsi now includes stm32l471.dtsi
Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
This patch adds a flash driver for the Atmel SAM E70 SoC. The driver has
been kept simple by considering that the flash is only composed of 8-KiB
blocks. Indeed an area at the beginning of the flash might be erased
with a smaller granularity, and the other blocks can also be erased with
a higher granularity. It also only handles the global read/write
protection, not the 128-KiB lock regions. A write error is returned if
a region is locked.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Enables Networking hardware on i.MX-RT 1050-EVKB board.
Pinout enabled board specific etherenet connection, also pin
initialization was moved later to PRE_KERNEL_2 in order to have
sysclock initialized before.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Convert the Atmel SAM0 watchdog driver to the new watchdog API and
enable DTS support.
This fixes#10914.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Add Messaging Unit B peripheral support for i.MX6SoloX soc so it can
use IMX IPM.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
When the WNC-14A2A modem binding was originally introduced, I thought
the base_label would shorten the define keeping the result short and
easily portable. Turns out with the latest changes, it has a side
effect of removing the "DT_*" prefix which is breaking the build.
Let's remove "base_label" from the modem binding and adjust all of
the dts_fixups referring to the WNC14A2A defines.
NOTE: This commit moves the left-over WNC14A2A dts_fixup defines from
the nRF52 soc into samples/net/lwm2m_client as the new values.
They will stay there until the modem can be re-configured as a shield.
Signed-off-by: Michael Scott <mike@foundries.io>
Kinetis device K64F's PTP interrupt crashed the system becase it was not
generated from dts. Device interrupt correctly set now.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
All drivers require DTS for their primary SPI settings.
Removing SPI_[0-9]_NAME config option added some more samples changes.
Usage of these options there was anyway not relevant.
Fixes#11064
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that all SPI controllers support DTS we can remove the Kconfig
support for non-DTS options. We also cleanup some defines that should
have be DT_MCR20A_ instead of CONFIG_MCR20A_.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The majority of cases of CONFIG_I2C_x_IRQ_PRI should be
DT_I2C_x_IRQ_PRI. So go ahead and fix them up. Only the i2c_nios
driver still uses Kconfig for getting priority.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The majority of bits where already in place, but some minor support
get the driver name from DTS was needed. Now we select HAS_DTS_WDT
for the driver.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
If we just had the kernel's implementation, we could
just move this to lib/, but possible arch-specific
implementations dictate that we just make this a
syscall.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Move to using Kconfig (like other Atmel SAM drivers do) to specify the
pinmux setting for SAMe70 SoCs. Updated the sam_e70_xplained board to
set the default in Kconfig.defconfig instead of via board.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The firmware starts us with an already-initialized UART and a simple
ROM hook. Use that as the default printk handler so we can log in
very early boot. It will be overriden later (as it happens, by
another handler based on the same firmware hooks).
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
With the DT_ prefix change we missed adding prefixes in dts_fixup.h
on snps_emsk & snps_nsim for ARC_ICCM_0_BASE_ADDRESS and
ARC_ICCM_0_SIZE.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This can help find unused symbols. Those end up without a type if
'default' is used instead of 'def_bool', which generates a warning.
Search for "Kconfig.defconfig" in
https://docs.zephyrproject.org/latest/application/kconfig-tips.html for
a longer explanation.
Keep the 'def_bool' for the following symbols, which seem to be
deliberately defined only in Kconfig.defconfig files:
- ALTERA_AVALON_I2C
- ALTERA_AVALON_MSGDMA
- ALTERA_AVALON_PIO
- ALTERA_AVALON_QSPI
- ALTERA_AVALON_SYSID
- CLOCK_CONTROL_IMX_CCM
- CPU_EM4_DMIPS
- CPU_EM4_FPUDA
- CPU_EM4_FPUS
- FP_FPU_DA
- I2C_GECKO
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Update a couple of labels generated from DTS used directly (not through
dts_fixups) in TI CC2650 system initialization code and a few drivers
for this SoC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
All labels containing "_<8-hex-digits>_" or "16550_<3or6-hex-digits>_"
in their names, assumed to be generated by the extracting script,
are updated with the DT_ prefix, to reflect the recent changes made
to the script.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Now that Cortex-M7 cache issues have been fixed in commits 828ae6b8 and
13972693, it is possible to safely enable the MPU on the STM32F7 SoC
series.
Note that the ITCM area is not mapped into an MPU region. This should
not be an issue for now, as Zephyr does not provide yet a way to
populate and use this area.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
STM32F103 micros starting from 64-pin (xE) packages upward have
available port G. This patch defines a dts binding for them.
Signed-off-by: Pavel Kral <pavel.kral@omsquare.com>
Provide CONFIG macros for clocks bits and bus properties in fixup
files and use them to simplify logic in uart devices instanciation
code
Fixes#10448
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
We now place the linker directives for the SW ISR table
in the common linker scripts, instead of repeating it
everywhere.
The table will be placed in RAM if dynamic interrupts are
enabled.
A dedicated section is used, as this data must not move
in between build phases.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The information extracted from the device tree is now used to initialize
GPIO device instances. Up until now the GPIO device driver made no use
of this information. Actual instance creation is still controlled using
the Kconfig method. Missing GPIO device tree nodes were added in the
process for STM32L073, STM32F413 and STM32F373.
The information for gpio instance initialization has already been
present for supported STM32 SoCs but remained unused. Changes in the
device tree had no effect on GPIO functionality and was essentially
redundant. Using the device tree for hardware description seems
plausible and less painful than a myriad of defines in some SoC
description header.
The change was implemented under the assumption that current device
trees provide a correct description of the SoCs. Base register addresses
and RCC register bits were not explicitly checked for each device.
Manual tests were executed on:
- NUCLEO-F103RB
- STM32F429I-DISCO
- STM32F746G-DISCO
- NUCLEO-F767ZI
Manual tests consisted of blinky on different GPIOs and pins on each
board.
sanitycheck was executed for all STM32 based boards
Fixes: #10629
Signed-off-by: Martin Bertsche <martin72216@googlemail.com>
Add a linker script entry for embedding a GNA model at a
4KB page aligned address in .data section
Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
The only difference between the F413xH and F413xG is flash memory size.
STMF413xH: 1536 Kbytes
STMF413xG: 1024 Kbytes
Signed-off-by: Benoit Leforestier <benoit.leforestier@gmail.com>
This patch adds a USB device driver for the USBHS device that can be
found on Atmel SAM E70 SoC family. Only the FIFO mode is supported
(as opposed to DMA). It supports LS, FS and HS modes, but defaults to
FS mode as Zephyr does not fully support HS mode yet.
Tested examples on an Atmel SMART SAM E70 Xplained Board:
* usb/cdc_acm
* usb/hid-mouse
* usb/mass
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add dts binding and info for TRNG device and enable basic support to
get the device name from DTS. We leave for now the base addresses
coming from the MCUX HAL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add dts binding and info for RNGA device and enable basic support to
get the device name from DTS. We leave for now the base addresses
coming from the MCUX HAL.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert gpio_cc32xx driver over to using device tree. Added binding
files, updates to dts for various SoCs that use cc32xx.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The define NRF51822 has no in-tree users and is believed to have been
added by accident. The define NRF51 should be referenced in it's
place.
To avoid users accidentally referencing NRF51822 instead of NRF51, and
to avoid confusing users into believing that NRF51822 has semantics we
remove it.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The build script ext/hal/nordic/CMakeLists.txt manages the MDK
dependency. The MDK is not aware of Zephyr and uses it's own defines
to indicate what HW we are building for.
This commit moves these MDK-specific defines out of the 'soc' build
scripts and into the MDK build script where they belong.
This is expected to be a pure refactoring without side-effects.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Update the uart_miv driver to get params like name, addr, baud-rate,
clock freq from DTS generated defines. Fixup related board and soc code
as needed.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add minimal DTS support for the m2gl025_miv. The dts just has the core,
SoC, PLIC, and UART described. We still get memory related info from
Kconfig.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The DTS changes introduced in 7ae220c845
changes the naming of GPIO related macros. This updates the usage
of previous macros via DTS fixup.
Fixes#10993
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fix misspellings in Kconfig files that show up in the configuration
documentation (and make menuconfig screens).
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Adding watchdog driver for sam SoC. The current implemntation just
diables the watchdog on device boot.
This PR adds the following support for SAM3X, SAM4S and SAME70
1. Activate processor reset
2. Activate all reset
3. Generate interrupt on watchdog timer expiration.
Signed-off-by: Subramanian Meenakshi Sundaram <subbu147@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
XCC does not support the "-undef" flag so set NOSYSDEF_CFLAGS to
empty string to fix compile warning.
Also, XCC does not supply the macro __SIZEOF_LONG__ which breaks
the build. So define it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Remove the auto-generated `handle_irq` label for the unneeded cases
to get rid of a compile warning.
Fixes#10801.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
When users are configuring nRF applications they are given the option
to enable the DesignWare I2C driver. But they should not be given this
option because nRF SoCs do not have DesignWare I2C HW.
This commit hides the driver by default by introducing the config
option HAS_I2C_DW.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This commit contributes a Kconfig symbol hierarchy which allows
the user to build Zephyr Secure and Non-Secure images on ARMv8-M
MCUs with support for Trusted Execution. However, the high-level
configuration structure is generic, thus, can be potentially
used for any platform that supports Trusted Execution.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This adds the necessary bits to support ASM2 with XCC
for Intel S1000 SoC. With ASM2 enabled, xcc is now
required to build for Intel S1000 SoC.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
(Previous patch set was reverted due to issue with priv_stack.
Resubmitting after fixing the faults caused by priv_stack.noinit
not at the end of RAM.)
This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.
Relates to #5534.
Fixes#10473, #10474, #10515.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Cypress PSoC6 specifies some input sections in the startup
scripts. These sections (.heap, .stack, etc.) need to be placed
at correct location.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.
For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.
POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Silicon Labs EFR32MG12P Mighty Gecko MCU includes:
* Cortex-M4F core at 40MHz
* up to 1024KB of flash and 256KB of RAM
* integrated Sub-GHz and/or 2.4GHz radio
* multiple low power peripherals
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Signed-off-by: Endre Karlson <endre.karslon@gmail.com>
Partially replaces Kinetis MCUX driver configuration from Kconfig to
Device Tree. Interrputs moved from defines configuration to DT.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Introduces the location property and adds the ability to use values
generated by the device tree configuration.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Simulated NRF boards based on the POSIX ARCH cannot directly
use the current SOC_*NRF options as these pull options from
the ARM CPU and other peripherals.
This commit adds a new set of hidden SOC_COMPATIBLE_* options to
be selected both by the real SOCs and the simulated ones.
In this manner we can have the common code depend on the
SOC_COMPATIBLE* options instead of the current ones where
neccessary.
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
(f) arm kconfig
patch adds the device binding for qmsi watchdog and device node
for socs which are using wdt qmsi driver.
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Call to soc_get_ref_clk_freq function is redundant in soc.c as it
simply returns a global static variable. Hence removed that call.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Mux configuration for I2C and GPIO are now done in SYS_INIT
which were earlier done in the respective tests.
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
* Add usbd_dc_nrfx shim
The shim is based on the previous one usbd_dc_nrf5.
For handling the USBD hardware, tested nrfx_usbd driver from nRF SDK
was used.
Briefly tested examples:
* usb/cdc_acm
* usb/dfu (USB communication only due to flash handling issues)
* usb/hid-mouse
* bluetooth/hci_usb
Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
For the stm32f4xx family the SPI and I2S are sharing same
controller, so we can reuse same definitions.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
stm32f4xx_ll_spi.h include file is shared between I2S and SPI
(controller is same). So we need to include it even when I2S_STM32
is enabled.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The USART fixup in the board dir really are SoC level fixup's. So move
them there and remove the board fixup file since there isn't anything in
it now.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Silicon Labs EFM32 Happy Gecko MCU includes:
* Cortex-M0+ core at 24MHz
* Up to 64KB of flash and 8KB of RAM
* Full speed (12 MHz) USB 2.0 Device
* Multiple low power peripherals
Signed-off-by: Marcio Montenegro <mtuxpe@gmail.com>
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
This patch adds a driver for Intel PRO/1000 Gigabit Ethernet controller.
The driver currently supports only a single instance of the NIC.
Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
Convert gpio_gecko driver over to using device tree. Added binding
files, updates to dts for various SoCs that use gpio_gecko.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds a linker flag and necessary changes to linker scripts
so that linker will warn about orphan sections.
Relates to #5534.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Cypress PSoC6 specifies some input sections in the startup
scripts. These sections (.heap, .stack, etc.) need to be placed
at correct location.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows the SoC to specify some additional linker script
fragments into the bss, data and read-only data sections.
For example, the Cypress PSOC6 has a few input sections that
must be put into bss and data sections. Without specifying
these in the linker script, they are consider orphan sections
and the placement is based on linker heuristic which is
arbitrary.
POSIX is not supported as the main linker script is
provided by the host system's binutils and we have no control
over it. Also, currently Xtensa SoCs have their own linker
scripts so there is no need to this feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr configuration system uses many different files in many
different formats. It makes it a lot easier for users to understand
what these files do if when we use the correct file extensions.
To this end we rename the dts.fixup files to the correct file
extension '.h'.
This is a breaking change for out-of-tree fixup files. Such files will
be detected and given an appropriate error message.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The dts.fixup for the hifive1 board was not board specific but related
to the SoC. Move the dts.fixup into the SoC dir so any other boards
using this same SoC will take advantage of it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add the needed bits to get device tree support for the GPIO controller
on the Zedboard-Pulpino. This will allow us to move LED & button info
into the board.dts.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add simple device tree support for the Pulpino SoC and Zedboard-Pulpino
board port. This gets the UART info from device tree instead of soc.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
added sam4s16b, sam4s8c, sam4s8b, sam4s4c, sam4s4b,
sam4s4a, sam4s2c, sam4s2b and sam4s2a.
Used the same order as in the data sheet and code structure
equal to same70. Updated the sam4s_xplained board to match
the altered .dtsi location of the specific SoC.
Signed-off-by: Vincent van der Locht <vincent@vlotech.nl>
This patch adds timers and PWM nodes to STM32 F7 series, as well as the
corresponding dts fixup entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Every board that uses dts-enabled spi drivers has a board-level dts, so
there is no need to have separate configs HAS_DTS_SPI_DEVICE and
HAS_DTS_SPI.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Every board that uses dts-enabled i2c drivers has a board-level dts, so
there is no need to have separate configs HAS_DTS_I2C_DEVICE and
HAS_DTS_I2C.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that we get the spi base address and irq numbers from dts, we can
remove the preprocessor macros from soc.h
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Makes the designware spi driver consistent with other spi drivers by
selecting HAS_DTS_SPI in the driver. This required adding spi nodes and
dts fixups to several arc and x86 socs, as well as enabling those nodes
in associated boards.
Also refactors the driver to use the base address, interrupt number, and
interrupt priority from dts.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Enables instance 3 of the lpuart driver, adds dts fixups, and configures
pinmuxes to use bluetooth hci on the mimxrt1050_evk board. Updates board
documentation accordingly.
Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as
an arduino shield running the nxp hci controller application.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Use the generated "_CLOCK_CONTROLLER" macro for the lpuart clock name.
This change is similar to commit
e81d9b98fe, but applied to nxp_imx.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Remove the selection of MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
in SOC_MPS2_AN3385, as this is selected automatically by
ARM_MPU option (for ARMv7-M MCUs).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Added initial support and created the corresponding device tree part for
building PSoC6 SoC as part of Zephyr.
Signed-off-by: Nazar Chornenkyy <nazar.chornenkyy@cypress.com>
Signed-off-by: Oleg Kapshii <oleg.kapshii@cypress.com>
Commit introduces support for ARM TrustZone CryptoCell 310
for Nordic Semiconductor nRF SoCs in device tree.
Signed-off-by: Dominik Kilian <Dominik.Kilian@nordicsemi.no>
This patch will enable the MPU in MPS2_AN385 soc.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added required files/support for the MPU in MPS2-AN358 (Cortex-M3).
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Enable UART 16550 driver for Nios-II QEMU platform.
Note: This PR is tested with patched version Qemu 3.0.0 which
adds support for altera_10m50_zephyr machine type.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
This commit removes all MPU-related (ARM_CORE_MPU and NXP_MPU)
options exept ARM_MPU, which becomes master switch controlling
MPU support on ARM.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options,
which indicate which flavour of MPU is supported by given SoC family.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The HAS_SYSMPU option is just selecting NXP_MPU option,
which could be also controlled through menuconfig.
This commit removes the HAS_SYSMPU option and replaces
its usage by NXP_MPU option.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The ARM_MPU_IMX_RT option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.
This commit removes the ARM_MPU_IMX_RT option and replaces
its usage by ARM_MPU option.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The ARM_MPU_NRF52X option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.
This commit removes the ARM_MPU_NRF52X option and replaces
its usage by ARM_MPU option.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The ARM_MPU_ENABLE option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.
This commit removes the ARM_MPU_ENABLE option and replaces
its usage by ARM_MPU option.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The STM32_ARM_MPU_ENABLE option is just selecting ARM_MPU option,
which could be also controlled through menuconfig.
This commit removes the STM32_ARM_MPU_ENABLE option and replaces
its usage by ARM_MPU option.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
We get several warnings of the form:
Warning (unit_address_format): /soc/uart@000003f8:
unit name should not have leading 0s
Fix these by remove the leading 0s.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The differentiation between the MCUs is handled in the HAL from Silabs.
So all EXX32 MCUs should use the same soc.c file.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.
The only directory excluded directory was ext/* since it contains
only imported code.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
As far as possible SoC-specific code should be contained to it's
directory and core systems should not be referencing specific
SoCs. This keeps the common code clean and makes it easier to maintain
out-of-tree SoCs.
To this end we move CONFIG_SOC_TI_LM3S6965_QEMU's soft-reset related
code out of arch/arm/core/cortex_m and into arch/arm/soc/ti_lm3s6965.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rather than do that for each architecture, source SoC Kconfigs where the
code is maintained, under ZEPHYR_BASE/soc.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
