riscv: Add min dts support for miv SoC & m2gl025_miv board
Add minimal DTS support for the m2gl025_miv. The dts just has the core, SoC, PLIC, and UART described. We still get memory related info from Kconfig. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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5 changed files with 123 additions and 0 deletions
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config BOARD_M2GL025_MIV
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bool "Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU"
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depends on SOC_RISCV32_MIV
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select HAS_DTS
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26
boards/riscv32/m2gl025_miv/m2gl025_miv.dts
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26
boards/riscv32/m2gl025_miv/m2gl025_miv.dts
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/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <microsemi-miv.dtsi>
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/ {
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model = "SiFive HiFive 1";
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compatible = "sifive,hifive1";
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aliases {
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};
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chosen {
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zephyr,console = &uart0;
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};
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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clock-frequency = <66000000>;
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};
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36
dts/bindings/serial/microsemi,coreuart.yaml
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36
dts/bindings/serial/microsemi,coreuart.yaml
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#
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# Copyright (c) 2018 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: SIFIVE UART
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version: 0.1
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description: >
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This binding gives a base representation of the SIFIVE UART
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inherits:
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!include uart.yaml
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "microsemi,coreuart"
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generation: define
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reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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...
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53
dts/riscv32/microsemi-miv.dtsi
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53
dts/riscv32/microsemi-miv.dtsi
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/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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clock-frequency = <0>;
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compatible = "microsemi,miv", "riscv";
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device_type = "cpu";
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reg = <0>;
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riscv,isa = "rv32imac";
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hlic: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "microsemi,miv-soc", "simple-bus";
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ranges;
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plic: interrupt-controller@40000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0x40000000 0x4000000>;
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reg-names = "control";
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riscv,max-priority = <1>;
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};
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uart0: uart@70001000 {
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compatible = "microsemi,coreuart";
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reg = <0x70001000 0x1000>;
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label = "uart_0";
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status = "disabled";
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current-speed = <0>;
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clock-frequency = <0>;
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};
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};
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};
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7
soc/riscv32/riscv-privilege/miv/dts_fixup.h
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7
soc/riscv32/riscv-privilege/miv/dts_fixup.h
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/* UART 0 */
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#define CONFIG_MIV_UART_0_BASE_ADDR MICROSEMI_COREUART_70001000_BASE_ADDRESS
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#define CONFIG_MIV_UART_0_CLOCK_FREQUENCY MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY
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#define CONFIG_MIV_UART_0_BAUD_RATE MICROSEMI_COREUART_70001000_CURRENT_SPEED
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#define CONFIG_MIV_UART_0_NAME MICROSEMI_COREUART_70001000_LABEL
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