riscv: Add min dts support for miv SoC & m2gl025_miv board

Add minimal DTS support for the m2gl025_miv.  The dts just has the core,
SoC, PLIC, and UART described.  We still get memory related info from
Kconfig.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2018-11-02 13:28:20 -05:00 committed by Kumar Gala
commit 11cb8778c7
5 changed files with 123 additions and 0 deletions

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@ -1,3 +1,4 @@
config BOARD_M2GL025_MIV
bool "Microsemi M2GL025 IGLOO2 dev board with Mi-V CPU"
depends on SOC_RISCV32_MIV
select HAS_DTS

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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <microsemi-miv.dtsi>
/ {
model = "SiFive HiFive 1";
compatible = "sifive,hifive1";
aliases {
};
chosen {
zephyr,console = &uart0;
};
};
&uart0 {
status = "ok";
current-speed = <115200>;
clock-frequency = <66000000>;
};

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#
# Copyright (c) 2018 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: SIFIVE UART
version: 0.1
description: >
This binding gives a base representation of the SIFIVE UART
inherits:
!include uart.yaml
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "microsemi,coreuart"
generation: define
reg:
type: array
description: mmio register space
generation: define
category: required
interrupts:
type: array
category: required
description: required interrupts
generation: define
...

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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
clock-frequency = <0>;
compatible = "microsemi,miv", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac";
hlic: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "microsemi,miv-soc", "simple-bus";
ranges;
plic: interrupt-controller@40000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0x40000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <1>;
};
uart0: uart@70001000 {
compatible = "microsemi,coreuart";
reg = <0x70001000 0x1000>;
label = "uart_0";
status = "disabled";
current-speed = <0>;
clock-frequency = <0>;
};
};
};

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/* UART 0 */
#define CONFIG_MIV_UART_0_BASE_ADDR MICROSEMI_COREUART_70001000_BASE_ADDRESS
#define CONFIG_MIV_UART_0_CLOCK_FREQUENCY MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY
#define CONFIG_MIV_UART_0_BAUD_RATE MICROSEMI_COREUART_70001000_CURRENT_SPEED
#define CONFIG_MIV_UART_0_NAME MICROSEMI_COREUART_70001000_LABEL