soc: intel_s1000: remove pinmux configuration
Since pinmux configuration is board dependent and is now under boards/xtensa/intel_s1000, the configuration in soc.c is removed. Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
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4a2ffea65c
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1b656beb84
2 changed files with 0 additions and 37 deletions
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@ -147,24 +147,6 @@ void _soc_irq_disable(u32_t irq)
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}
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}
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void soc_config_iomux_ctsrts(void)
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{
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volatile struct soc_io_mux_regs *regs =
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(volatile struct soc_io_mux_regs *)IOMUX_BASE;
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/* Configure the MUX to select GPIO functionality for GPIO 23 and 24 */
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regs->io_mux_ctl0 |= SOC_UART_RTS_CTS_MS;
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}
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void soc_config_iomux_i2c(void)
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{
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volatile struct soc_io_mux_regs *regs =
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(volatile struct soc_io_mux_regs *)IOMUX_BASE;
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/* Configure the MUX to select the correct I2C port (I2C1) */
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regs->io_mux_ctl2 |= SOC_I2C_I0_I1_MS;
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}
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static inline void soc_set_resource_ownership(void)
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{
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volatile struct soc_resource_alloc_regs *regs =
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@ -244,14 +226,6 @@ static int soc_init(struct device *dev)
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soc_set_resource_ownership();
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soc_set_power_and_clock();
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#ifdef CONFIG_I2C
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soc_config_iomux_i2c();
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#endif
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#ifdef CONFIG_GPIO
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soc_config_iomux_ctsrts();
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#endif
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return 0;
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}
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@ -92,17 +92,6 @@
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#define SOC_NUM_LPGPDMAC 3
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#define SOC_NUM_CHANNELS_IN_DMAC 8
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#define IOMUX_BASE 0x00081C00
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#define SOC_I2C_I0_I1_MS BIT(0)
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#define SOC_UART_RTS_CTS_MS BIT(16)
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struct soc_io_mux_regs {
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u32_t reserved[12];
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u32_t io_mux_ctl0;
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u32_t io_mux_ctl1;
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u32_t io_mux_ctl2;
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};
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/* SOC Resource Allocation Registers */
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#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
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/* bit field definition for LP GPDMA ownership register */
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