soc: intel_s1000: remove pinmux configuration

Since pinmux configuration is board dependent and is now under
boards/xtensa/intel_s1000, the configuration in soc.c is removed.

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan 2018-11-24 22:10:05 -08:00 committed by Anas Nashif
commit 1b656beb84
2 changed files with 0 additions and 37 deletions

View file

@ -147,24 +147,6 @@ void _soc_irq_disable(u32_t irq)
}
}
void soc_config_iomux_ctsrts(void)
{
volatile struct soc_io_mux_regs *regs =
(volatile struct soc_io_mux_regs *)IOMUX_BASE;
/* Configure the MUX to select GPIO functionality for GPIO 23 and 24 */
regs->io_mux_ctl0 |= SOC_UART_RTS_CTS_MS;
}
void soc_config_iomux_i2c(void)
{
volatile struct soc_io_mux_regs *regs =
(volatile struct soc_io_mux_regs *)IOMUX_BASE;
/* Configure the MUX to select the correct I2C port (I2C1) */
regs->io_mux_ctl2 |= SOC_I2C_I0_I1_MS;
}
static inline void soc_set_resource_ownership(void)
{
volatile struct soc_resource_alloc_regs *regs =
@ -244,14 +226,6 @@ static int soc_init(struct device *dev)
soc_set_resource_ownership();
soc_set_power_and_clock();
#ifdef CONFIG_I2C
soc_config_iomux_i2c();
#endif
#ifdef CONFIG_GPIO
soc_config_iomux_ctsrts();
#endif
return 0;
}

View file

@ -92,17 +92,6 @@
#define SOC_NUM_LPGPDMAC 3
#define SOC_NUM_CHANNELS_IN_DMAC 8
#define IOMUX_BASE 0x00081C00
#define SOC_I2C_I0_I1_MS BIT(0)
#define SOC_UART_RTS_CTS_MS BIT(16)
struct soc_io_mux_regs {
u32_t reserved[12];
u32_t io_mux_ctl0;
u32_t io_mux_ctl1;
u32_t io_mux_ctl2;
};
/* SOC Resource Allocation Registers */
#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
/* bit field definition for LP GPDMA ownership register */