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soc/miv: Use DTS to generate PLIC addresses

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Describe the MMIO register regions for the PLIC in the DTS instead of
hardcoded in soc.h.

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
This commit is contained in:
Nathaniel Graff 2018-11-30 15:16:00 -08:00 • committed by Kumar Gala
commit 8907c09fee
3 changed files with 14 additions and 10 deletions
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6
dts/riscv32/microsemi-miv.dtsi
View file

@ -36,8 +36,10 @@
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0x40000000 0x4000000>;
reg-names = "control";
reg = <0x40000000 0x2000
0x40002000 0x1fe000
0x40200000 0x2000000>;
reg-names = "prio", "irq_en", "reg";
riscv,max-priority = <1>;
};

10
soc/riscv32/riscv-privilege/miv/dts_fixup.h
View file

@ -1,4 +1,14 @@
/* PLIC */
#define DT_PLIC_MAX_PRIORITY \
DT_RISCV_PLIC0_40000000_RISCV_MAX_PRIORITY
#define DT_PLIC_PRIO_BASE_ADDR \
DT_RISCV_PLIC0_40000000_PRIO_BASE_ADDRESS
#define DT_PLIC_IRQ_EN_BASE_ADDR \
DT_RISCV_PLIC0_40000000_IRQ_EN_BASE_ADDRESS
#define DT_PLIC_REG_BASE_ADDR \
DT_RISCV_PLIC0_40000000_REG_BASE_ADDRESS
/* UART 0 */
#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS
#define DT_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY

8
soc/riscv32/riscv-privilege/miv/soc.h
View file

@ -43,14 +43,6 @@
/* GPIO Configuration */
#define MIV_GPIO_0_BASE_ADDR 0x70002000
/* Platform Level Interrupt Controller Configuration */
#define MIV_PLIC_BASE_ADDR 0x40000000
#define MIV_PLIC_PRIO_BASE_ADDR MIV_PLIC_BASE_ADDR
#define MIV_PLIC_IRQ_EN_BASE_ADDR (MIV_PLIC_BASE_ADDR + 0x2000)
#define MIV_PLIC_REG_BASE_ADDR (MIV_PLIC_BASE_ADDR + 0x200000)
#define MIV_PLIC_MAX_PRIORITY 7
/* Clock controller. */
#define PRCI_BASE_ADDR 0x44000000