soc/miv: Use DTS to generate PLIC addresses
Describe the MMIO register regions for the PLIC in the DTS instead of hardcoded in soc.h. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
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c48c94c9e6
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8907c09fee
3 changed files with 14 additions and 10 deletions
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@ -36,8 +36,10 @@
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&hlic 11>;
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reg = <0x40000000 0x4000000>;
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reg-names = "control";
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reg = <0x40000000 0x2000
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0x40002000 0x1fe000
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0x40200000 0x2000000>;
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reg-names = "prio", "irq_en", "reg";
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riscv,max-priority = <1>;
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};
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@ -1,4 +1,14 @@
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/* PLIC */
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#define DT_PLIC_MAX_PRIORITY \
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DT_RISCV_PLIC0_40000000_RISCV_MAX_PRIORITY
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#define DT_PLIC_PRIO_BASE_ADDR \
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DT_RISCV_PLIC0_40000000_PRIO_BASE_ADDRESS
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#define DT_PLIC_IRQ_EN_BASE_ADDR \
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DT_RISCV_PLIC0_40000000_IRQ_EN_BASE_ADDRESS
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#define DT_PLIC_REG_BASE_ADDR \
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DT_RISCV_PLIC0_40000000_REG_BASE_ADDRESS
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/* UART 0 */
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#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS
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#define DT_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY
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@ -43,14 +43,6 @@
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/* GPIO Configuration */
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#define MIV_GPIO_0_BASE_ADDR 0x70002000
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/* Platform Level Interrupt Controller Configuration */
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#define MIV_PLIC_BASE_ADDR 0x40000000
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#define MIV_PLIC_PRIO_BASE_ADDR MIV_PLIC_BASE_ADDR
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#define MIV_PLIC_IRQ_EN_BASE_ADDR (MIV_PLIC_BASE_ADDR + 0x2000)
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#define MIV_PLIC_REG_BASE_ADDR (MIV_PLIC_BASE_ADDR + 0x200000)
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#define MIV_PLIC_MAX_PRIORITY 7
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/* Clock controller. */
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#define PRCI_BASE_ADDR 0x44000000
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