drivers: eth: e1000: Add driver for Intel PRO/1000 Ethernet controller
This patch adds a driver for Intel PRO/1000 Gigabit Ethernet controller. The driver currently supports only a single instance of the NIC. Signed-off-by: Oleg Zhurakivskyy <oleg.zhurakivskyy@intel.com>
This commit is contained in:
Oleg Zhurakivskyy
Kumar Gala
parent
6ebc766043
commit
65ea181c92
6 changed files with 380 additions and 0 deletions
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@ -5,6 +5,7 @@ zephyr_sources_ifdef(CONFIG_ETH_SAM_GMAC
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phy_sam_gmac.c
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)
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zephyr_sources_ifdef(CONFIG_ETH_DW eth_dw.c)
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zephyr_sources_ifdef(CONFIG_ETH_E1000 eth_e1000.c)
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zephyr_sources_ifdef(CONFIG_ETH_ENC28J60 eth_enc28j60.c)
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zephyr_sources_ifdef(CONFIG_ETH_MCUX eth_mcux.c)
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zephyr_sources_ifdef(CONFIG_ETH_STM32_HAL eth_stm32_hal.c)
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@ -29,6 +29,7 @@ config ETH_INIT_PRIORITY
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source "drivers/ethernet/Kconfig.enc28j60"
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source "drivers/ethernet/Kconfig.mcux"
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source "drivers/ethernet/Kconfig.dw"
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source "drivers/ethernet/Kconfig.e1000"
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source "drivers/ethernet/Kconfig.sam_gmac"
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source "drivers/ethernet/Kconfig.stm32_hal"
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source "drivers/ethernet/Kconfig.native_posix"
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14
drivers/ethernet/Kconfig.e1000
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14
drivers/ethernet/Kconfig.e1000
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@ -0,0 +1,14 @@
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# Kconfig - Intel(R) PRO/1000 Gigabit Ethernet driver configuration options
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#
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# Copyright (c) 2018 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig ETH_E1000
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bool
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prompt "Intel(R) PRO/1000 Gigabit Ethernet driver"
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depends on NET_L2_ETHERNET && PCI_ENUMERATION
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help
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Enable Intel(R) PRO/1000 Gigabit Ethernet driver.
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253
drivers/ethernet/eth_e1000.c
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253
drivers/ethernet/eth_e1000.c
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@ -0,0 +1,253 @@
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/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOG_MODULE_NAME eth_e1000
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#include <zephyr.h>
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#include <net/ethernet.h>
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#include <pci/pci.h>
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#include "eth_e1000_priv.h"
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#define dev_dbg(fmt, args...) LOG_DBG("%s() " fmt, __func__, ## args)
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#define dev_err(fmt, args...) LOG_ERR("%s() " "Error: " fmt, __func__, ## args)
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static const char *e1000_reg_to_string(enum e1000_reg_t r)
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{
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#define _(_x) case _x: return #_x
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switch (r) {
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_(CTRL);
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_(ICR);
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_(ICS);
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_(IMS);
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_(RCTL);
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_(TCTL);
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_(RDBAL);
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_(RDBAH);
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_(RDLEN);
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_(RDH);
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_(RDT);
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_(TDBAL);
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_(TDBAH);
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_(TDLEN);
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_(TDH);
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_(TDT);
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_(RAL);
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_(RAH);
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}
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#undef _
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dev_err("Unsupported register: 0x%x", r);
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k_oops();
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return NULL;
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}
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static enum ethernet_hw_caps e1000_caps(struct device *dev)
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{
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return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T | \
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ETHERNET_LINK_1000BASE_T;
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}
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static size_t e1000_linearize(struct net_pkt *pkt, void *buf, size_t bufsize)
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{
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size_t len = net_pkt_ll_reserve(pkt) + pkt->frags->len;
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struct net_buf *nb;
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/* First fragment contains link layer (Ethernet) header */
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memcpy(buf, net_pkt_ll(pkt), len);
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for (nb = pkt->frags->frags; nb; nb = nb->frags) {
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memcpy((u8_t *) buf + len, nb->data, nb->len);
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len += nb->len;
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}
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return len;
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}
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static int e1000_tx(struct e1000_dev *dev, void *data, size_t data_len)
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{
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dev->tx.addr = POINTER_TO_INT(data);
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dev->tx.len = data_len;
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dev->tx.cmd = TDESC_EOP | TDESC_RS;
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iow32(dev, TDT, 1);
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while (!(dev->tx.sta)) {
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k_yield();
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}
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dev_dbg("tx.sta: 0x%02hx", dev->tx.sta);
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return (dev->tx.sta & TDESC_STA_DD) ? 0 : -EIO;
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}
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static int e1000_send(struct net_if *iface, struct net_pkt *pkt)
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{
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struct e1000_dev *dev = net_if_get_device(iface)->driver_data;
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size_t len = e1000_linearize(pkt, dev->txb, sizeof(dev->txb));
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int err = e1000_tx(dev, dev->txb, len);
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if (err) {
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net_pkt_unref(pkt);
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}
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return err;
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}
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static struct net_pkt *e1000_rx(struct e1000_dev *dev)
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{
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struct net_pkt *pkt = NULL;
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dev_dbg("rx.sta: 0x%02hx", dev->rx.sta);
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if (!(dev->rx.sta & RDESC_STA_DD)) {
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dev_err("RX descriptor not ready");
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goto out;
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}
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pkt = net_pkt_get_reserve_rx(0, K_NO_WAIT);
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if (!pkt) {
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dev_err("Out of RX buffers");
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goto out;
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}
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if (!net_pkt_append_all(pkt, dev->rx.len - 4,
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INT_TO_POINTER((u32_t) dev->rx.addr),
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K_NO_WAIT)) {
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dev_err("Out of memory for received frame");
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net_pkt_unref(pkt);
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pkt = NULL;
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}
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out:
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return pkt;
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}
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static void e1000_isr(struct device *device)
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{
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struct e1000_dev *dev = device->driver_data;
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u32_t icr = ior32(dev, ICR); /* Cleared upon read */
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icr &= ~(ICR_TXDW | ICR_TXQE);
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if (icr & ICR_RXO) {
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struct net_pkt *pkt = e1000_rx(dev);
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icr &= ~ICR_RXO;
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if (pkt) {
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net_recv_data(dev->iface, pkt);
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}
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}
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if (icr) {
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dev_err("Unhandled interrupt, ICR: 0x%x", icr);
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}
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}
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int e1000_probe(struct device *device)
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{
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struct e1000_dev *dev = device->driver_data;
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bool found = false;
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pci_bus_scan_init();
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if (pci_bus_scan(&dev->pci)) {
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pci_enable_regs(&dev->pci);
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pci_enable_bus_master(&dev->pci);
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pci_show(&dev->pci);
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found = true;
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}
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return found;
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}
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static struct device DEVICE_NAME_GET(eth_e1000);
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static void e1000_init(struct net_if *iface)
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{
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struct e1000_dev *dev = net_if_get_device(iface)->driver_data;
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u32_t ral, rah;
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dev->iface = iface;
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/* Setup TX descriptor */
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iow32(dev, TDBAL, (u32_t) &dev->tx);
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iow32(dev, TDBAH, 0);
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iow32(dev, TDLEN, 1*16);
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iow32(dev, TDH, 0);
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iow32(dev, TDT, 0);
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iow32(dev, TCTL, TCTL_EN);
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/* Setup RX descriptor */
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dev->rx.addr = POINTER_TO_INT(dev->rxb);
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dev->rx.len = sizeof(dev->rxb);
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iow32(dev, RDBAL, (u32_t) &dev->rx);
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iow32(dev, RDBAH, 0);
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iow32(dev, RDLEN, 1*16);
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iow32(dev, RDH, 0);
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iow32(dev, RDT, 1);
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iow32(dev, RCTL, RCTL_EN);
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iow32(dev, IMS, IMS_RXO);
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ral = ior32(dev, RAL);
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rah = ior32(dev, RAH);
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memcpy(dev->mac, &ral, 4);
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memcpy(dev->mac + 4, &rah, 2);
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net_if_set_link_addr(iface, dev->mac, sizeof(dev->mac),
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NET_LINK_ETHERNET);
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iow32(dev, CTRL, CTRL_SLU); /* Set link up */
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IRQ_CONNECT(CONFIG_ETH_E1000_IRQ, CONFIG_ETH_E1000_IRQ_PRIORITY,
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e1000_isr, DEVICE_GET(eth_e1000),
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CONFIG_ETH_E1000_IRQ_FLAGS);
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irq_enable(CONFIG_ETH_E1000_IRQ);
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dev_dbg("done");
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}
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_DEVICE_ID_I82540EM 0x100e
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static struct e1000_dev e1000_dev = {
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.pci.vendor_id = PCI_VENDOR_ID_INTEL,
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.pci.device_id = PCI_DEVICE_ID_I82540EM,
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};
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static const struct ethernet_api e1000_api = {
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.iface_api.init = e1000_init,
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.iface_api.send = e1000_send,
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.get_capabilities = e1000_caps,
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};
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NET_DEVICE_INIT(eth_e1000,
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"ETH_0",
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e1000_probe,
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&e1000_dev,
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NULL,
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CONFIG_ETH_INIT_PRIORITY,
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&e1000_api,
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ETHERNET_L2,
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NET_L2_GET_CTX_TYPE(ETHERNET_L2),
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E1000_MTU);
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106
drivers/ethernet/eth_e1000_priv.h
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106
drivers/ethernet/eth_e1000_priv.h
Normal file
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@ -0,0 +1,106 @@
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/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ETH_E1000_PRIV_H
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#define ETH_E1000_PRIV_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CTRL_SLU (1 << 6) /* Set Link Up */
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#define TCTL_EN (1 << 1)
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#define RCTL_EN (1 << 1)
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#define ICR_TXDW (1) /* Transmit Descriptor Written Back */
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#define ICR_TXQE (1 << 1) /* Transmit Queue Empty */
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#define ICR_RXO (1 << 6) /* Receiver Overrun */
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#define IMS_RXO (1 << 6) /* Receiver FIFO Overrun */
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#define TDESC_EOP (1) /* End Of Packet */
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#define TDESC_RS (1 << 3) /* Report Status */
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#define RDESC_STA_DD (1) /* Descriptor Done */
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#define TDESC_STA_DD (1) /* Descriptor Done */
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#define E1000_MTU 1500
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#define ETH_ALEN 6 /* TODO: Add a global reusable definition in OS */
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enum e1000_reg_t {
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CTRL = 0x0000, /* Device Control */
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ICR = 0x00C0, /* Interrupt Cause Read */
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ICS = 0x00C8, /* Interrupt Cause Set */
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IMS = 0x00D0, /* Interrupt Mask Set */
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RCTL = 0x0100, /* Receive Control */
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TCTL = 0x0400, /* Transmit Control */
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RDBAL = 0x2800, /* Rx Descriptor Base Address Low */
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RDBAH = 0x2804, /* Rx Descriptor Base Address High */
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RDLEN = 0x2808, /* Rx Descriptor Length */
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RDH = 0x2810, /* Rx Descriptor Head */
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RDT = 0x2818, /* Rx Descriptor Tail */
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TDBAL = 0x3800, /* Tx Descriptor Base Address Low */
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TDBAH = 0x3804, /* Tx Descriptor Base Address High */
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TDLEN = 0x3808, /* Tx Descriptor Length */
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TDH = 0x3810, /* Tx Descriptor Head */
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TDT = 0x3818, /* Tx Descriptor Tail */
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RAL = 0x5400, /* Receive Address Low */
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RAH = 0x5404, /* Receive Address High */
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};
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/* Legacy TX Descriptor */
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struct e1000_tx {
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u64_t addr;
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u16_t len;
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u8_t cso;
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u8_t cmd;
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u8_t sta;
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u8_t css;
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u16_t special;
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};
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/* Legacy RX Descriptor */
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struct e1000_rx {
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u64_t addr;
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u16_t len;
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u16_t csum;
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u8_t sta;
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u8_t err;
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u16_t special;
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};
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struct e1000_dev {
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volatile struct e1000_tx tx __aligned(16);
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volatile struct e1000_rx rx __aligned(16);
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struct pci_dev_info pci;
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struct net_if *iface;
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u8_t mac[ETH_ALEN];
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u8_t txb[E1000_MTU];
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u8_t rxb[E1000_MTU];
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};
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static const char *e1000_reg_to_string(enum e1000_reg_t r)
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__attribute__((unused));
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#define iow32(_dev, _reg, _val) do { \
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dev_dbg("iow32 %s 0x%08x", e1000_reg_to_string(_reg), _val); \
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sys_write32(_val, (_dev)->pci.addr + _reg); \
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} while (0)
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#define ior32(_dev, _reg) \
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({ \
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u32_t val = sys_read32((_dev)->pci.addr + (_reg)); \
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dev_dbg("ior32 %s 0x%08x", e1000_reg_to_string(_reg), val); \
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val; \
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})
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#ifdef __cplusplus
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}
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#endif
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#endif /* ETH_E1000_PRIV_H_ */
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@ -26,4 +26,9 @@ MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE);
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#ifdef CONFIG_HPET_TIMER
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MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE);
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#endif
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#ifdef CONFIG_ETH_E1000
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MMU_BOOT_REGION(CONFIG_ETH_E1000_BASE_ADDRESS, KB(128), MMU_ENTRY_WRITE);
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#endif
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#endif /* CONFIG_X86_MMU*/
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