riscv: Add device tree support to pulpino
Add simple device tree support for the Pulpino SoC and Zedboard-Pulpino board port. This gets the UART info from device tree instead of soc.h Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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7 changed files with 132 additions and 25 deletions
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@ -2,4 +2,5 @@
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config BOARD_ZEDBOARD_PULPINO
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bool "Zedboard pulpino target"
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depends on SOC_RISCV32_PULPINO
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select HAS_DTS
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select BUILD_OUTPUT_S19
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28
boards/riscv32/zedboard_pulpino/zedboard_pulpino.dts
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28
boards/riscv32/zedboard_pulpino/zedboard_pulpino.dts
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/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <pulpino.dtsi>
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/ {
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model = "zedboard_pulpino";
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compatible = "pulp,zedboard-pulpino";
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aliases {
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uart-0 = &uart0;
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};
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chosen {
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zephyr,console = &uart0;
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};
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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};
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32
dts/bindings/interrupt-controller/pulpino,event-unit.yaml
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32
dts/bindings/interrupt-controller/pulpino,event-unit.yaml
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@ -0,0 +1,32 @@
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#
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# Copyright (c) 2018, Linaro Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: PULPINO Event Unit
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id: pulp,pulpino-event-unit
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version: 0.1
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description: >
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This binding describes the Pulpino Event Unit
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properties:
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compatible:
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category: required
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type: string
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description: compatible strings
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constraint: "pulp,pulpino-event-unit"
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generation: define
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reg:
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category: required
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type: int
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description: mmio register space
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generation: define
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base_label: PULPINO_EVENT_UNIT
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"#cells":
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- irq
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...
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54
dts/riscv32/pulpino.dtsi
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54
dts/riscv32/pulpino.dtsi
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@ -0,0 +1,54 @@
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/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "pulp,ri5cy", "riscv";
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reg = <0>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "pulp,pulpino-soc", "simple-bus";
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ranges;
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itim: itim@8000000 {
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compatible = "pulp,pulpino0itim";
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reg = <0x0 0x8000>;
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};
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dtim: dtim@100000 {
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compatible = "pulp,pulpino-dtim";
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reg = <0x100000 0x8000>;
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};
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uart0: uart@1a100000 {
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compatible = "ns16550";
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reg = <0x1a100000 0x1000>;
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label = "UART_0";
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clock-frequency = <2500000>;
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interrupts = <24>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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intc: interrupt-controller@1a104000 {
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#interrupt-cells = <1>;
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compatible = "pulp,pulpino-event-unit";
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interrupt-controller;
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reg = <0x1a104000 0x1000>;
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};
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};
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};
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@ -58,26 +58,6 @@ config UART_NS16550_PORT_0
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bool
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default y
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if UART_NS16550_PORT_0
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config UART_NS16550_PORT_0_NAME
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string
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default "UART_0"
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config UART_NS16550_PORT_0_IRQ_PRI
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int
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default 0
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config UART_NS16550_PORT_0_BAUD_RATE
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int
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default 115200
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config UART_NS16550_PORT_0_OPTIONS
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int
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default 0
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endif # UART_NS16550_PORT_0
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endif # UART_NS16550
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endif # SOC_RISCV32_PULPINO
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16
soc/riscv32/pulpino/dts.fixup
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16
soc/riscv32/pulpino/dts.fixup
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@ -0,0 +1,16 @@
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/*
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* Copyright (c) 2018, Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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/*
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* UART configuration
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*/
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#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_1A100000_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_0_IRQ NS16550_1A100000_IRQ_0
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#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_1A100000_CLOCK_FREQUENCY
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_1A100000_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_1A100000_LABEL
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@ -22,7 +22,6 @@
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/* IRQ numbers */
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#define PULP_I2C_0_IRQ 23 /* I2C Controller */
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#define PULP_UART_0_IRQ 24 /* Uart Controller */
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#define PULP_GPIO_0_IRQ 25 /* GPIO Controller */
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#define PULP_SPI_0_IRQ 26 /* SPI Controller #0 */
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#define PULP_SPI_1_IRQ 27 /* SPI Controller #1 */
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#define SOC_ERET eret
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/* UART configuration */
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#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR 0x1A100000
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#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ 2500000
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#define CONFIG_UART_NS16550_PORT_0_IRQ PULP_UART_0_IRQ
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI 0
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#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0
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@ -72,7 +68,7 @@
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#define PULP_PAD_BASE 0x1A107000
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/* IRQ configuration */
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#define PULP_IRQ_BASE 0x1A104000
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#define PULP_IRQ_BASE PULPINO_EVENT_UNIT_BASE_ADDRESS
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#define PULP_IER_ADDR (PULP_IRQ_BASE + 0x00) /* IRQ Enable Register */
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#define PULP_IPR_ADDR (PULP_IRQ_BASE + 0x04) /* IRQ Pending Register */
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