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dts: spi: cleanup CONFIG_SPI_x_IRQ_PRI

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All of the cases of CONFIG_SPI_x_IRQ_PRI should be DT_SPI_x_IRQ_PRI.
So go ahead and fix them up.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2018-11-21 06:33:39 -06:00 • committed by Anas Nashif
commit 6d83738e33
19 changed files with 49 additions and 49 deletions
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8
drivers/spi/spi_dw.c
View file

@ -551,7 +551,7 @@ DEVICE_AND_API_INIT(spi_dw_port_0, DT_SPI_0_NAME, spi_dw_init,
void spi_config_0_irq(void)
{
#ifdef CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_0_IRQ);
_spi_int_unmask(SPI_DW_PORT_0_INT_MASK);
@ -599,7 +599,7 @@ DEVICE_AND_API_INIT(spi_dw_port_1, DT_SPI_1_NAME, spi_dw_init,
void spi_config_1_irq(void)
{
#ifdef CONFIG_SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_1_IRQ);
_spi_int_unmask(SPI_DW_PORT_1_INT_MASK);
@ -647,7 +647,7 @@ DEVICE_AND_API_INIT(spi_dw_port_2, DT_SPI_2_NAME, spi_dw_init,
void spi_config_2_irq(void)
{
#ifdef CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_2_IRQ);
_spi_int_unmask(SPI_DW_PORT_2_INT_MASK);
@ -695,7 +695,7 @@ DEVICE_AND_API_INIT(spi_dw_port_3, DT_SPI_3_NAME, spi_dw_init,
void spi_config_3_irq(void)
{
#ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
IRQ_CONNECT(DT_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI,
IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI,
spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS);
irq_enable(DT_SPI_3_IRQ);
_spi_int_unmask(SPI_DW_PORT_3_INT_MASK);

4
drivers/spi/spi_intel.c
View file

@ -439,7 +439,7 @@ DEVICE_DEFINE(spi_intel_port_0, DT_SPI_0_NAME, spi_intel_init,
void spi_config_0_irq(void)
{
IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
spi_intel_isr, DEVICE_GET(spi_intel_port_0),
DT_SPI_0_IRQ_FLAGS);
}
@ -475,7 +475,7 @@ DEVICE_DEFINE(spi_intel_port_1, DT_SPI_1_NAME, spi_intel_init,
void spi_config_1_irq(void)
{
IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
spi_intel_isr, DEVICE_GET(spi_intel_port_1),
DT_SPI_1_IRQ_FLAGS);
}

6
drivers/spi/spi_ll_stm32.c
View file

@ -512,7 +512,7 @@ DEVICE_AND_API_INIT(spi_stm32_1, DT_SPI_1_NAME, &spi_stm32_init,
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_1(struct device *dev)
{
IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
spi_stm32_isr, DEVICE_GET(spi_stm32_1), 0);
irq_enable(DT_SPI_1_IRQ);
}
@ -550,7 +550,7 @@ DEVICE_AND_API_INIT(spi_stm32_2, DT_SPI_2_NAME, &spi_stm32_init,
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_2(struct device *dev)
{
IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
spi_stm32_isr, DEVICE_GET(spi_stm32_2), 0);
irq_enable(DT_SPI_2_IRQ);
}
@ -588,7 +588,7 @@ DEVICE_AND_API_INIT(spi_stm32_3, DT_SPI_3_NAME, &spi_stm32_init,
#ifdef CONFIG_SPI_STM32_INTERRUPT
static void spi_stm32_irq_config_func_3(struct device *dev)
{
IRQ_CONNECT(DT_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI,
IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI,
spi_stm32_isr, DEVICE_GET(spi_stm32_3), 0);
irq_enable(DT_SPI_3_IRQ);
}

6
drivers/spi/spi_mcux_dspi.c
View file

@ -289,7 +289,7 @@ DEVICE_AND_API_INIT(spi_mcux_0, DT_SPI_0_NAME, &spi_mcux_init,
static void spi_mcux_config_func_0(struct device *dev)
{
IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
spi_mcux_isr, DEVICE_GET(spi_mcux_0), 0);
irq_enable(DT_SPI_0_IRQ);
@ -318,7 +318,7 @@ DEVICE_AND_API_INIT(spi_mcux_1, DT_SPI_1_NAME, &spi_mcux_init,
static void spi_mcux_config_func_1(struct device *dev)
{
IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
spi_mcux_isr, DEVICE_GET(spi_mcux_1), 0);
irq_enable(DT_SPI_1_IRQ);
@ -347,7 +347,7 @@ DEVICE_AND_API_INIT(spi_mcux_2, DT_SPI_2_NAME, &spi_mcux_init,
static void spi_mcux_config_func_2(struct device *dev)
{
IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
spi_mcux_isr, DEVICE_GET(spi_mcux_2), 0);
irq_enable(DT_SPI_2_IRQ);

4
soc/arc/snps_emsk/dts_fixup.h
View file

@ -86,12 +86,12 @@
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS
#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
#define DT_SPI_DW_IRQ_FLAGS 0

4
soc/arm/atmel_sam/same70/dts_fixup.h
View file

@ -58,13 +58,13 @@
#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS
#define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL
#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY
#define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID
#define DT_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS
#define DT_SPI_1_NAME DT_ATMEL_SAM_SPI_40058000_LABEL
#define DT_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY
#define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID
#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL

6
soc/arm/nxp_kinetis/k6x/dts_fixup.h
View file

@ -98,21 +98,21 @@
#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
#define DT_SPI_2_NAME DT_NXP_KINETIS_DSPI_400AC000_LABEL
#define DT_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS
#define DT_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0
#define CONFIG_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY
#define DT_SPI_2_CLOCK_NAME DT_NXP_KINETIS_DSPI_400AC000_CLOCK_CONTROLLER
#define DT_SPI_2_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_400AC000_CLOCK_NAME

8
soc/arm/nxp_kinetis/kwx/dts_fixup.h
View file

@ -84,14 +84,14 @@
#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
@ -134,14 +134,14 @@
#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME

4
soc/arm/st_stm32/stm32f0/dts_fixup.h
View file

@ -89,12 +89,12 @@
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0

6
soc/arm/st_stm32/stm32f1/dts_fixup.h
View file

@ -118,17 +118,17 @@
#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0

6
soc/arm/st_stm32/stm32f3/dts_fixup.h
View file

@ -111,17 +111,17 @@
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0

6
soc/arm/st_stm32/stm32f4/dts_fixup.h
View file

@ -164,17 +164,17 @@
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0

6
soc/arm/st_stm32/stm32f7/dts_fixup.h
View file

@ -196,17 +196,17 @@
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0

4
soc/arm/st_stm32/stm32l0/dts_fixup.h
View file

@ -107,12 +107,12 @@
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0

6
soc/arm/st_stm32/stm32l4/dts_fixup.h
View file

@ -178,17 +178,17 @@
#define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
#define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0

2
soc/x86/intel_quark/quark_d2000/dts_fixup.h
View file

@ -37,7 +37,7 @@
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI 0
#define DT_SPI_0_IRQ_PRI 0
#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL
#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0

6
soc/x86/intel_quark/quark_se/dts_fixup.h
View file

@ -50,17 +50,17 @@
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS
#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0
#define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS
#define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL
#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
#define CONFIG_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
#define DT_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL
#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0

4
soc/x86/intel_quark/quark_x1000/dts_fixup.h
View file

@ -33,11 +33,11 @@
#define DT_SPI_0_BASE_ADDRESS DT_INTEL_INTEL_SPI_90009000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0
#define DT_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE
#define CONFIG_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY
#define DT_SPI_0_NAME DT_INTEL_INTEL_SPI_90009000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0
#define DT_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE
#define CONFIG_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY
#define DT_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY
#define DT_SPI_1_NAME DT_INTEL_INTEL_SPI_90008000_LABEL

2
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -57,5 +57,5 @@
#define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
/* End of SoC Level DTS fixup file */