dts: spi: cleanup CONFIG_SPI_x_IRQ_PRI
All of the cases of CONFIG_SPI_x_IRQ_PRI should be DT_SPI_x_IRQ_PRI. So go ahead and fix them up. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
b904ad387f
commit
6d83738e33
19 changed files with 49 additions and 49 deletions
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@ -551,7 +551,7 @@ DEVICE_AND_API_INIT(spi_dw_port_0, DT_SPI_0_NAME, spi_dw_init,
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void spi_config_0_irq(void)
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{
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#ifdef CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS);
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irq_enable(DT_SPI_0_IRQ);
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_spi_int_unmask(SPI_DW_PORT_0_INT_MASK);
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@ -599,7 +599,7 @@ DEVICE_AND_API_INIT(spi_dw_port_1, DT_SPI_1_NAME, spi_dw_init,
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void spi_config_1_irq(void)
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{
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#ifdef CONFIG_SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS);
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irq_enable(DT_SPI_1_IRQ);
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_spi_int_unmask(SPI_DW_PORT_1_INT_MASK);
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@ -647,7 +647,7 @@ DEVICE_AND_API_INIT(spi_dw_port_2, DT_SPI_2_NAME, spi_dw_init,
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void spi_config_2_irq(void)
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{
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#ifdef CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS);
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irq_enable(DT_SPI_2_IRQ);
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_spi_int_unmask(SPI_DW_PORT_2_INT_MASK);
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@ -695,7 +695,7 @@ DEVICE_AND_API_INIT(spi_dw_port_3, DT_SPI_3_NAME, spi_dw_init,
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void spi_config_3_irq(void)
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{
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#ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE
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IRQ_CONNECT(DT_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI,
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spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS);
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irq_enable(DT_SPI_3_IRQ);
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_spi_int_unmask(SPI_DW_PORT_3_INT_MASK);
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@ -439,7 +439,7 @@ DEVICE_DEFINE(spi_intel_port_0, DT_SPI_0_NAME, spi_intel_init,
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void spi_config_0_irq(void)
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{
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IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
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spi_intel_isr, DEVICE_GET(spi_intel_port_0),
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DT_SPI_0_IRQ_FLAGS);
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}
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@ -475,7 +475,7 @@ DEVICE_DEFINE(spi_intel_port_1, DT_SPI_1_NAME, spi_intel_init,
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void spi_config_1_irq(void)
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{
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IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
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spi_intel_isr, DEVICE_GET(spi_intel_port_1),
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DT_SPI_1_IRQ_FLAGS);
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}
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@ -512,7 +512,7 @@ DEVICE_AND_API_INIT(spi_stm32_1, DT_SPI_1_NAME, &spi_stm32_init,
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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static void spi_stm32_irq_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
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spi_stm32_isr, DEVICE_GET(spi_stm32_1), 0);
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irq_enable(DT_SPI_1_IRQ);
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}
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@ -550,7 +550,7 @@ DEVICE_AND_API_INIT(spi_stm32_2, DT_SPI_2_NAME, &spi_stm32_init,
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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static void spi_stm32_irq_config_func_2(struct device *dev)
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{
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IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
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spi_stm32_isr, DEVICE_GET(spi_stm32_2), 0);
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irq_enable(DT_SPI_2_IRQ);
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}
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@ -588,7 +588,7 @@ DEVICE_AND_API_INIT(spi_stm32_3, DT_SPI_3_NAME, &spi_stm32_init,
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#ifdef CONFIG_SPI_STM32_INTERRUPT
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static void spi_stm32_irq_config_func_3(struct device *dev)
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{
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IRQ_CONNECT(DT_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI,
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spi_stm32_isr, DEVICE_GET(spi_stm32_3), 0);
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irq_enable(DT_SPI_3_IRQ);
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}
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@ -289,7 +289,7 @@ DEVICE_AND_API_INIT(spi_mcux_0, DT_SPI_0_NAME, &spi_mcux_init,
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static void spi_mcux_config_func_0(struct device *dev)
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{
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IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_0_IRQ, DT_SPI_0_IRQ_PRI,
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spi_mcux_isr, DEVICE_GET(spi_mcux_0), 0);
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irq_enable(DT_SPI_0_IRQ);
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@ -318,7 +318,7 @@ DEVICE_AND_API_INIT(spi_mcux_1, DT_SPI_1_NAME, &spi_mcux_init,
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static void spi_mcux_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_1_IRQ, DT_SPI_1_IRQ_PRI,
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spi_mcux_isr, DEVICE_GET(spi_mcux_1), 0);
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irq_enable(DT_SPI_1_IRQ);
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@ -347,7 +347,7 @@ DEVICE_AND_API_INIT(spi_mcux_2, DT_SPI_2_NAME, &spi_mcux_init,
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static void spi_mcux_config_func_2(struct device *dev)
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{
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IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI,
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IRQ_CONNECT(DT_SPI_2_IRQ, DT_SPI_2_IRQ_PRI,
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spi_mcux_isr, DEVICE_GET(spi_mcux_2), 0);
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irq_enable(DT_SPI_2_IRQ);
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@ -86,12 +86,12 @@
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#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS
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#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL
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#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0
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#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
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#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY
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#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS
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#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL
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#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0
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#define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY
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#define DT_SPI_DW_IRQ_FLAGS 0
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@ -58,13 +58,13 @@
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#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS
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#define DT_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL
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#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0
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#define CONFIG_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY
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#define DT_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY
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#define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID
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#define DT_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS
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#define DT_SPI_1_NAME DT_ATMEL_SAM_SPI_40058000_LABEL
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#define DT_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0
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#define CONFIG_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY
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#define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID
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#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL
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@ -98,21 +98,21 @@
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#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
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#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
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#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
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#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
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#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
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#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
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#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
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#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
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#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
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#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
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#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
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#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
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#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
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#define DT_SPI_2_NAME DT_NXP_KINETIS_DSPI_400AC000_LABEL
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#define DT_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS
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#define DT_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0
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#define CONFIG_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY
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#define DT_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY
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#define DT_SPI_2_CLOCK_NAME DT_NXP_KINETIS_DSPI_400AC000_CLOCK_CONTROLLER
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#define DT_SPI_2_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_400AC000_CLOCK_NAME
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@ -84,14 +84,14 @@
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#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
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#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
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#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
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#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
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#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
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#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
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#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
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#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
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#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
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#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
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#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
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#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
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#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
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@ -134,14 +134,14 @@
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#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
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#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
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#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
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#define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
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#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
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#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
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#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
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#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
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#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
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#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
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#define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
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#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
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#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
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@ -89,12 +89,12 @@
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS
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#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
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#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
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#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
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#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
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#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
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#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
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#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
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#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
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#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
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@ -118,17 +118,17 @@
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#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS
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#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
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#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
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#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
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#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
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#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
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#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
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#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
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#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
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#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
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#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
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#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
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#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
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#define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
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#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0
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#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
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#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
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#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
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#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
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#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
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#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
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#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
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#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
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#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
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#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
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#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
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#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
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#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
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#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
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#define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
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#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0
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@ -164,17 +164,17 @@
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#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS
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#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
|
||||
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
|
||||
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
|
||||
|
||||
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
|
||||
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
|
||||
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
|
||||
|
||||
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
|
||||
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
|
||||
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
|
||||
#define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
|
||||
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0
|
||||
|
||||
|
|
|
@ -196,17 +196,17 @@
|
|||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS
|
||||
|
||||
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
|
||||
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
|
||||
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
|
||||
|
||||
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
|
||||
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
|
||||
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
|
||||
|
||||
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS
|
||||
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
|
||||
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
|
||||
#define DT_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL
|
||||
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0
|
||||
|
||||
|
|
|
@ -107,12 +107,12 @@
|
|||
#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS
|
||||
|
||||
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS
|
||||
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL
|
||||
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0
|
||||
|
||||
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS
|
||||
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL
|
||||
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0
|
||||
|
||||
|
|
|
@ -178,17 +178,17 @@
|
|||
#define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER
|
||||
|
||||
#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS
|
||||
#define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL
|
||||
#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0
|
||||
|
||||
#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS
|
||||
#define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL
|
||||
#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0
|
||||
|
||||
#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS
|
||||
#define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
|
||||
#define DT_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY
|
||||
#define DT_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL
|
||||
#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0
|
||||
|
||||
|
|
|
@ -37,7 +37,7 @@
|
|||
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
|
||||
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
|
||||
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
|
||||
#define CONFIG_SPI_0_IRQ_PRI 0
|
||||
#define DT_SPI_0_IRQ_PRI 0
|
||||
|
||||
#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL
|
||||
#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
|
||||
|
|
|
@ -50,17 +50,17 @@
|
|||
#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS
|
||||
#define DT_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL
|
||||
#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
|
||||
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY
|
||||
|
||||
#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS
|
||||
#define DT_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL
|
||||
#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0
|
||||
#define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY
|
||||
|
||||
#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS
|
||||
#define DT_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL
|
||||
#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
|
||||
#define CONFIG_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
|
||||
#define DT_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
|
||||
|
||||
#define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL
|
||||
#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
|
||||
|
|
|
@ -33,11 +33,11 @@
|
|||
#define DT_SPI_0_BASE_ADDRESS DT_INTEL_INTEL_SPI_90009000_BASE_ADDRESS
|
||||
#define DT_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0
|
||||
#define DT_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE
|
||||
#define CONFIG_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_0_NAME DT_INTEL_INTEL_SPI_90009000_LABEL
|
||||
|
||||
#define DT_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS
|
||||
#define DT_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0
|
||||
#define DT_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE
|
||||
#define CONFIG_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_1_NAME DT_INTEL_INTEL_SPI_90008000_LABEL
|
||||
|
|
|
@ -57,5 +57,5 @@
|
|||
|
||||
#define DT_SPI_DW_IRQ_FLAGS DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
|
||||
|
||||
#define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
|
||||
#define DT_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue