mimxrt1050_evk: enabling networking hardware
Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
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35ba3aadc4
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9 changed files with 98 additions and 1 deletions
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@ -54,4 +54,14 @@ config TEXT_SECTION_OFFSET
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endif
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if NETWORKING
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config NET_L2_ETHERNET
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def_bool y
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config ETH_MCUX_0
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def_bool y if NET_L2_ETHERNET
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endif # NETWORKING
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endif # BOARD_MIMXRT1050_EVK
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@ -23,6 +23,7 @@
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led0 = &green_led;
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sw0 = &user_button;
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spi-3 = &spi3;
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eth = ð
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};
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chosen {
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@ -92,3 +93,10 @@ arduino_serial: &uart3 {};
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&spi3 {
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status = "ok";
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};
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ð {
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status = "ok";
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ptp {
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status = "ok";
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};
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};
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@ -15,3 +15,4 @@ ram: 128
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flash: 128
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supported:
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- spi
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- netif:eth
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@ -6,6 +6,15 @@
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#include <init.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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#ifdef CONFIG_ETH_MCUX_0
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static gpio_pin_config_t enet_gpio_config = {
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.direction = kGPIO_DigitalOutput,
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.outputLogic = 0,
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.interruptMode = kGPIO_NoIntmode
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};
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#endif
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static int mimxrt1050_evk_init(struct device *dev)
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{
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@ -85,7 +94,44 @@ static int mimxrt1050_evk_init(struct device *dev)
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_ETH_MCUX_0
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
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IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
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/* Intialize ENET_INT GPIO */
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GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
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GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
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/* pull up the ENET_INT before RESET. */
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GPIO_WritePinOutput(GPIO1, 10, 1);
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/* RESET PHY chip. */
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GPIO_WritePinOutput(GPIO1, 9, 0);
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k_busy_wait(10 * USEC_PER_MSEC);
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GPIO_WritePinOutput(GPIO1, 9, 1);
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#endif
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return 0;
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}
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SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
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SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_2, 0);
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@ -65,6 +65,7 @@
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/*!@brief Defines the mask flag of operation mode in control two register*/
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#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
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#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
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#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
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#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
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#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
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@ -9,3 +9,4 @@ zephyr_include_directories(.)
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zephyr_sources_ifdef(CONFIG_GPIO_MCUX_IGPIO fsl_gpio.c)
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zephyr_sources_ifdef(CONFIG_SPI_MCUX_LPSPI fsl_lpspi.c)
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zephyr_sources_ifdef(CONFIG_UART_MCUX_LPUART fsl_lpuart.c)
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zephyr_sources_ifdef(CONFIG_ETH_MCUX fsl_enet.c)
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@ -51,4 +51,12 @@ config SPI_MCUX_LPSPI
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endif # SPI
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if NET_L2_ETHERNET
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config ETH_MCUX
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def_bool y
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endif # NET_L2_ETHERNET
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endif # SOC_MIMXRT1052
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@ -41,4 +41,13 @@
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#define DT_UART_MCUX_LPUART_3_CLOCK_NAME DT_NXP_KINETIS_LPUART_4018C000_CLOCK_CONTROLLER
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#define DT_UART_MCUX_LPUART_3_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_4018C000_CLOCK_NAME
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#define DT_ETH_MCUX_0_NAME DT_NXP_KINETIS_ETHERNET_402D8000_LABEL
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#define DT_ETH_MCUX_0_MAC3 DT_NXP_KINETIS_ETHERNET_402D8000_LOCAL_MAC_ADDRESS_3
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#define DT_ETH_MCUX_0_MAC4 DT_NXP_KINETIS_ETHERNET_402D8000_LOCAL_MAC_ADDRESS_4
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#define DT_ETH_MCUX_0_MAC5 DT_NXP_KINETIS_ETHERNET_402D8000_LOCAL_MAC_ADDRESS_5
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#define DT_IRQ_ETH_COMMON DT_NXP_KINETIS_ETHERNET_402D8000_IRQ_0
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#define DT_ETH_MCUX_0_IRQ_PRI DT_NXP_KINETIS_ETHERNET_402D8000_IRQ_0_PRIORITY
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/* End of SoC Level DTS fixup file */
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@ -34,6 +34,16 @@ const clock_usb_pll_config_t usb1PllConfig = {
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};
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#endif
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#ifdef CONFIG_ETH_MCUX_0
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const clock_enet_pll_config_t ethPllConfig = {
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.enableClkOutput0 = true,
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.enableClkOutput1 = false,
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.enableClkOutput2 = false,
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.loopDivider0 = 1,
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.loopDivider1 = 1
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};
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#endif
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/**
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*
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* @brief Initialize the system clock
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@ -73,6 +83,9 @@ static ALWAYS_INLINE void clkInit(void)
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#ifdef CONFIG_INIT_USB1_PLL
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CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
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#endif
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#ifdef CONFIG_ETH_MCUX_0
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CLOCK_InitEnetPll(ðPllConfig);
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#endif
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CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
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CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */
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