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mimxrt1050_evk: enabling networking hardware

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Enables Networking hardware on i.MX-RT 1050-EVKB board.
Pinout enabled board specific etherenet connection, also pin
initialization was moved later to PRE_KERNEL_2 in order to have
sysclock initialized before.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit is contained in:
Andrei Gansari 2018-11-15 18:28:47 +02:00 • committed by Kumar Gala
commit a5174be648
9 changed files with 98 additions and 1 deletions
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10
boards/arm/mimxrt1050_evk/Kconfig.defconfig
View file

@ -54,4 +54,14 @@ config TEXT_SECTION_OFFSET
endif
if NETWORKING
config NET_L2_ETHERNET
def_bool y
config ETH_MCUX_0
def_bool y if NET_L2_ETHERNET
endif # NETWORKING
endif # BOARD_MIMXRT1050_EVK

8
boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts
View file

@ -23,6 +23,7 @@
led0 = &green_led;
sw0 = &user_button;
spi-3 = &spi3;
eth = &eth;
};
chosen {
@ -92,3 +93,10 @@ arduino_serial: &uart3 {};
&spi3 {
status = "ok";
};
&eth {
status = "ok";
ptp {
status = "ok";
};
};

1
boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml
View file

@ -15,3 +15,4 @@ ram: 128
flash: 128
supported:
- spi
- netif:eth

48
boards/arm/mimxrt1050_evk/pinmux.c
View file

@ -6,6 +6,15 @@
#include <init.h>
#include <fsl_iomuxc.h>
#include <fsl_gpio.h>
#ifdef CONFIG_ETH_MCUX_0
static gpio_pin_config_t enet_gpio_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0,
.interruptMode = kGPIO_NoIntmode
};
#endif
static int mimxrt1050_evk_init(struct device *dev)
{
@ -85,7 +94,44 @@ static int mimxrt1050_evk_init(struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#ifdef CONFIG_ETH_MCUX_0
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0x31);
IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB829);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
/* Intialize ENET_INT GPIO */
GPIO_PinInit(GPIO1, 9, &enet_gpio_config);
GPIO_PinInit(GPIO1, 10, &enet_gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
/* RESET PHY chip. */
GPIO_WritePinOutput(GPIO1, 9, 0);
k_busy_wait(10 * USEC_PER_MSEC);
GPIO_WritePinOutput(GPIO1, 9, 1);
#endif
return 0;
}
SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_1, 0);
SYS_INIT(mimxrt1050_evk_init, PRE_KERNEL_2, 0);

1
ext/hal/nxp/mcux/components/phyksz8081/fsl_phy.h
View file

@ -65,6 +65,7 @@
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */

1
ext/hal/nxp/mcux/drivers/imx/CMakeLists.txt
View file

@ -9,3 +9,4 @@ zephyr_include_directories(.)
zephyr_sources_ifdef(CONFIG_GPIO_MCUX_IGPIO fsl_gpio.c)
zephyr_sources_ifdef(CONFIG_SPI_MCUX_LPSPI fsl_lpspi.c)
zephyr_sources_ifdef(CONFIG_UART_MCUX_LPUART fsl_lpuart.c)
zephyr_sources_ifdef(CONFIG_ETH_MCUX fsl_enet.c)

8
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052
View file

@ -51,4 +51,12 @@ config SPI_MCUX_LPSPI
endif # SPI
if NET_L2_ETHERNET
config ETH_MCUX
def_bool y
endif # NET_L2_ETHERNET
endif # SOC_MIMXRT1052

9
soc/arm/nxp_imx/rt/dts_fixup.h
View file

@ -41,4 +41,13 @@
#define DT_UART_MCUX_LPUART_3_CLOCK_NAME DT_NXP_KINETIS_LPUART_4018C000_CLOCK_CONTROLLER
#define DT_UART_MCUX_LPUART_3_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_4018C000_CLOCK_NAME
#define DT_ETH_MCUX_0_NAME DT_NXP_KINETIS_ETHERNET_402D8000_LABEL
#define DT_ETH_MCUX_0_MAC3 DT_NXP_KINETIS_ETHERNET_402D8000_LOCAL_MAC_ADDRESS_3
#define DT_ETH_MCUX_0_MAC4 DT_NXP_KINETIS_ETHERNET_402D8000_LOCAL_MAC_ADDRESS_4
#define DT_ETH_MCUX_0_MAC5 DT_NXP_KINETIS_ETHERNET_402D8000_LOCAL_MAC_ADDRESS_5
#define DT_IRQ_ETH_COMMON DT_NXP_KINETIS_ETHERNET_402D8000_IRQ_0
#define DT_ETH_MCUX_0_IRQ_PRI DT_NXP_KINETIS_ETHERNET_402D8000_IRQ_0_PRIORITY
/* End of SoC Level DTS fixup file */

13
soc/arm/nxp_imx/rt/soc.c
View file

@ -34,6 +34,16 @@ const clock_usb_pll_config_t usb1PllConfig = {
};
#endif
#ifdef CONFIG_ETH_MCUX_0
const clock_enet_pll_config_t ethPllConfig = {
.enableClkOutput0 = true,
.enableClkOutput1 = false,
.enableClkOutput2 = false,
.loopDivider0 = 1,
.loopDivider1 = 1
};
#endif
/**
*
* @brief Initialize the system clock
@ -73,6 +83,9 @@ static ALWAYS_INLINE void clkInit(void)
#ifdef CONFIG_INIT_USB1_PLL
CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
#endif
#ifdef CONFIG_ETH_MCUX_0
CLOCK_InitEnetPll(&ethPllConfig);
#endif
CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */