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drivers: watchdog: Add dts support for QMSI based watchdog.

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patch adds the device binding for qmsi watchdog and device node
for socs which are using wdt qmsi driver.

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Savinay Dharmappa 2018-09-20 18:53:13 +05:30 • committed by Anas Nashif
commit bf389e0853
12 changed files with 97 additions and 18 deletions
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7
drivers/watchdog/Kconfig.qmsi
View file

@ -8,17 +8,12 @@
config WDT_QMSI
bool "QMSI Watchdog driver"
select HAS_DTS_WDT
help
This option enables the QMSI watchdog driver.
This driver is simply a shim driver based on the watchdog
driver provided by the QMSI BSP.
config WDT_0_IRQ_PRI
int "Interrupt priority"
depends on WDT_QMSI
help
Watchdog interrupt priority
config WDT_QMSI_API_REENTRANCY
bool "WDT shim driver API reentrancy"
depends on WDT_QMSI

4
drivers/watchdog/wdt_qmsi.c
View file

@ -218,8 +218,8 @@ static int init(struct device *dev)
k_sem_init(RP_GET(dev), 1, UINT_MAX);
}
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_WDT_0_INT), CONFIG_WDT_0_IRQ_PRI,
qm_wdt_0_isr, 0, IOAPIC_EDGE | IOAPIC_HIGH);
IRQ_CONNECT(CONFIG_WDT_0_IRQ, CONFIG_WDT_0_IRQ_PRI,
qm_wdt_0_isr, 0, CONFIG_WDT_0_IRQ_FLAGS);
/* Unmask watchdog interrupt */
irq_enable(IRQ_GET_NUMBER(QM_IRQ_WDT_0_INT));

11
dts/arc/quark_se_c1000_ss.dtsi
View file

@ -213,5 +213,16 @@
status = "disabled";
};
wdog0: watchdog@b0000000 {
compatible = "intel,qmsi-watchdog";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xb0000000 0x400>;
interrupts = <48 0>;
interrupt-parent = <&core_intc>;
label = "WATCHDOG_0";
};
};
};

45
dts/bindings/watchdog/intel,qmsi-watchdog.yaml Normal file
View file

@ -0,0 +1,45 @@
#
# Copyright (c) 2018, Intel
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: QMSI watchdog driver
id: intel,qmsi-watchdog
version: 0.1
description: >
This is a representation of the QMSI watchdog
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "intel,qmsi-watchdog"
generation: define
reg:
type: int
description: mmio register space
generation: define
category: required
label:
type: string
category: required
description: Human readable string describing the device (used by Zephyr for API name)
generation: define
interrupts:
type: array
category: required
description: required interrupts
generation: define
clocks:
type: array
category: required
description: Clock gate control information
generation: structures
...

13
dts/x86/intel_curie.dtsi
View file

@ -170,5 +170,18 @@
label = "SPI_2";
status = "disabled";
};
wdog0: watchdog@b0000000 {
compatible = "intel,qmsi-watchdog";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xb0000000 0x400>;
interrupts = <12 IRQ_TYPE_EDGE_RISING 2>;
interrupt-parent = <&intc>;
label = "WATCHDOG_0";
};
};
};

11
dts/x86/intel_quark_d2000.dtsi
View file

@ -120,5 +120,16 @@
label = "SPI_0";
status = "disabled";
};
wdog0: watchdog@b0000000 {
compatible = "intel,qmsi-watchdog";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xb0000000 0x400>;
interrupts = <16 IRQ_TYPE_EDGE_RISING>;
interrupt-parent = <&intc>;
label = "WATCHDOG_0";
};
};
};

4
soc/arc/quark_se_c1000_ss/Kconfig.defconfig
View file

@ -210,10 +210,6 @@ if WATCHDOG
config WDT_QMSI
def_bool y
config WDT_0_IRQ_PRI
default 0
endif # WATCHDOG
if DMA

4
soc/arc/quark_se_c1000_ss/dts_fixup.h
View file

@ -92,4 +92,8 @@
#define CONFIG_SPI_1_IRQ_TX_REQ SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ
#define CONFIG_SPI_1_IRQ_TX_REQ_PRI SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ_PRIORITY
#define CONFIG_WDT_0_NAME INTEL_QMSI_WATCHDOG_B0000000_LABEL
#define CONFIG_WDT_0_IRQ INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
#define CONFIG_WDT_0_IRQ_PRI INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY
#define CONFIG_WDT_0_IRQ_FLAGS 0
/* End of SoC Level DTS fixup file */

3
soc/x86/intel_quark/quark_d2000/Kconfig.defconfig.series
View file

@ -54,9 +54,6 @@ endif # UART_QMSI
if WATCHDOG
config WDT_QMSI
def_bool y
config WDT_0_IRQ_PRI
default 0
endif # WATCHDOG
if RTC

5
soc/x86/intel_quark/quark_d2000/dts_fixup.h
View file

@ -38,3 +38,8 @@
#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_B0001000_LABEL
#define CONFIG_SPI_0_IRQ SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
#define CONFIG_SPI_0_IRQ_PRI 0
#define CONFIG_WDT_0_NAME INTEL_QMSI_WATCHDOG_B0000000_LABEL
#define CONFIG_WDT_0_IRQ INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
#define CONFIG_WDT_0_IRQ_PRI 0
#define CONFIG_WDT_0_IRQ_FLAGS INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE

3
soc/x86/intel_quark/quark_se/Kconfig.defconfig.series
View file

@ -146,9 +146,6 @@ endif
if WATCHDOG
config WDT_QMSI
def_bool y
config WDT_0_IRQ_PRI
default 2
endif # WATCHDOG
if RTC

5
soc/x86/intel_quark/quark_se/dts_fixup.h
View file

@ -62,4 +62,9 @@
#define CONFIG_SPI_2_IRQ SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
#define CONFIG_SPI_2_IRQ_PRI SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
#define CONFIG_WDT_0_NAME INTEL_QMSI_WATCHDOG_B0000000_LABEL
#define CONFIG_WDT_0_IRQ INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
#define CONFIG_WDT_0_IRQ_PRI INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY
#define CONFIG_WDT_0_IRQ_FLAGS INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE
/* End of SoC Level DTS fixup file */