drivers: watchdog: Add dts support for QMSI based watchdog.
patch adds the device binding for qmsi watchdog and device node for socs which are using wdt qmsi driver. Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
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020884c02c
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12 changed files with 97 additions and 18 deletions
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@ -8,17 +8,12 @@
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config WDT_QMSI
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bool "QMSI Watchdog driver"
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select HAS_DTS_WDT
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help
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This option enables the QMSI watchdog driver.
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This driver is simply a shim driver based on the watchdog
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driver provided by the QMSI BSP.
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config WDT_0_IRQ_PRI
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int "Interrupt priority"
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depends on WDT_QMSI
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help
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Watchdog interrupt priority
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config WDT_QMSI_API_REENTRANCY
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bool "WDT shim driver API reentrancy"
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depends on WDT_QMSI
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@ -218,8 +218,8 @@ static int init(struct device *dev)
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k_sem_init(RP_GET(dev), 1, UINT_MAX);
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}
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_WDT_0_INT), CONFIG_WDT_0_IRQ_PRI,
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qm_wdt_0_isr, 0, IOAPIC_EDGE | IOAPIC_HIGH);
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IRQ_CONNECT(CONFIG_WDT_0_IRQ, CONFIG_WDT_0_IRQ_PRI,
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qm_wdt_0_isr, 0, CONFIG_WDT_0_IRQ_FLAGS);
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/* Unmask watchdog interrupt */
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_WDT_0_INT));
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@ -213,5 +213,16 @@
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status = "disabled";
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};
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wdog0: watchdog@b0000000 {
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compatible = "intel,qmsi-watchdog";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0000000 0x400>;
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interrupts = <48 0>;
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interrupt-parent = <&core_intc>;
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label = "WATCHDOG_0";
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};
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};
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};
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45
dts/bindings/watchdog/intel,qmsi-watchdog.yaml
Normal file
45
dts/bindings/watchdog/intel,qmsi-watchdog.yaml
Normal file
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@ -0,0 +1,45 @@
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#
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# Copyright (c) 2018, Intel
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: QMSI watchdog driver
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id: intel,qmsi-watchdog
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version: 0.1
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description: >
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This is a representation of the QMSI watchdog
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properties:
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compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "intel,qmsi-watchdog"
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generation: define
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reg:
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type: int
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description: mmio register space
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generation: define
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category: required
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label:
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type: string
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category: required
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description: Human readable string describing the device (used by Zephyr for API name)
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generation: define
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interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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clocks:
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type: array
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category: required
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description: Clock gate control information
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generation: structures
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...
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@ -170,5 +170,18 @@
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label = "SPI_2";
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status = "disabled";
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};
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wdog0: watchdog@b0000000 {
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compatible = "intel,qmsi-watchdog";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0000000 0x400>;
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interrupts = <12 IRQ_TYPE_EDGE_RISING 2>;
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interrupt-parent = <&intc>;
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label = "WATCHDOG_0";
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};
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};
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};
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@ -120,5 +120,16 @@
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label = "SPI_0";
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status = "disabled";
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};
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wdog0: watchdog@b0000000 {
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compatible = "intel,qmsi-watchdog";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xb0000000 0x400>;
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interrupts = <16 IRQ_TYPE_EDGE_RISING>;
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interrupt-parent = <&intc>;
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label = "WATCHDOG_0";
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};
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};
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};
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@ -210,10 +210,6 @@ if WATCHDOG
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config WDT_QMSI
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def_bool y
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config WDT_0_IRQ_PRI
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default 0
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endif # WATCHDOG
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if DMA
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@ -92,4 +92,8 @@
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#define CONFIG_SPI_1_IRQ_TX_REQ SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ
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#define CONFIG_SPI_1_IRQ_TX_REQ_PRI SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ_PRIORITY
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#define CONFIG_WDT_0_NAME INTEL_QMSI_WATCHDOG_B0000000_LABEL
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#define CONFIG_WDT_0_IRQ INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
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#define CONFIG_WDT_0_IRQ_PRI INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY
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#define CONFIG_WDT_0_IRQ_FLAGS 0
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/* End of SoC Level DTS fixup file */
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@ -54,9 +54,6 @@ endif # UART_QMSI
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if WATCHDOG
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config WDT_QMSI
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def_bool y
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config WDT_0_IRQ_PRI
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default 0
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endif # WATCHDOG
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if RTC
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@ -38,3 +38,8 @@
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#define CONFIG_SPI_0_NAME SNPS_DESIGNWARE_SPI_B0001000_LABEL
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#define CONFIG_SPI_0_IRQ SNPS_DESIGNWARE_SPI_B0001000_IRQ_0
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#define CONFIG_SPI_0_IRQ_PRI 0
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#define CONFIG_WDT_0_NAME INTEL_QMSI_WATCHDOG_B0000000_LABEL
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#define CONFIG_WDT_0_IRQ INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
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#define CONFIG_WDT_0_IRQ_PRI 0
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#define CONFIG_WDT_0_IRQ_FLAGS INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE
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@ -146,9 +146,6 @@ endif
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if WATCHDOG
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config WDT_QMSI
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def_bool y
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config WDT_0_IRQ_PRI
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default 2
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endif # WATCHDOG
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if RTC
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@ -62,4 +62,9 @@
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#define CONFIG_SPI_2_IRQ SNPS_DESIGNWARE_SPI_B0001800_IRQ_0
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#define CONFIG_SPI_2_IRQ_PRI SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY
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#define CONFIG_WDT_0_NAME INTEL_QMSI_WATCHDOG_B0000000_LABEL
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#define CONFIG_WDT_0_IRQ INTEL_QMSI_WATCHDOG_B0000000_IRQ_0
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#define CONFIG_WDT_0_IRQ_PRI INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY
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#define CONFIG_WDT_0_IRQ_FLAGS INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE
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/* End of SoC Level DTS fixup file */
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