boards: mimxrt1050_evk: Enable lpuart3 for bluetooth hci
Enables instance 3 of the lpuart driver, adds dts fixups, and configures pinmuxes to use bluetooth hci on the mimxrt1050_evk board. Updates board documentation accordingly. Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as an arduino shield running the nxp hci controller application. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
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5 changed files with 44 additions and 1 deletions
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@ -41,6 +41,9 @@ if UART_MCUX_LPUART
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config UART_MCUX_LPUART_1
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def_bool y
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config UART_MCUX_LPUART_3
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def_bool y if BT_UART
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endif # UART_MCUX_LPUART
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if CODE_HYPERFLASH || CODE_QSPI
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@ -129,6 +129,10 @@ The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B0_13 | LPUART1_RX | UART Console |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI |
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+---------------+-----------------+---------------------------+
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| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI |
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+---------------+-----------------+---------------------------+
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| WAKEUP | GPIO | SW0 |
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+---------------+-----------------+---------------------------+
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@ -141,7 +145,8 @@ board with the on-chip PLL to generate a 600 MHz core clock.
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Serial Port
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===========
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The MIMXRT1050 SoC has eight UARTs. One is configured for the console and the
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The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console,
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``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the
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remaining are not used.
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Programming and Debugging
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@ -19,6 +19,7 @@
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gpio-4= &gpio4;
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gpio-5= &gpio5;
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uart-1 = &uart1;
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uart-3 = &uart3;
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led0 = &green_led;
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sw0 = &user_button;
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spi-3 = &spi3;
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@ -34,6 +35,9 @@
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#endif
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zephyr,sram = &dtcm0;
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zephyr,console = &uart1;
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#ifdef CONFIG_BT
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zephyr,bt-uart = &uart3;
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#endif
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};
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sdram0: memory@80000000 {
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@ -86,6 +90,13 @@
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current-speed = <115200>;
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};
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#ifdef CONFIG_BT
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&uart3 {
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status = "ok";
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current-speed = <115200>;
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};
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#endif
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&spi3 {
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status = "ok";
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};
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@ -41,6 +41,22 @@ static int mimxrt1050_evk_init(struct device *dev)
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART_3
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/* LPUART3 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#ifdef CONFIG_SPI_3
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/* LPSPI3 SCK, SDO, SDI, PCS0 */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0);
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@ -33,4 +33,12 @@
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#define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME NXP_KINETIS_LPUART_40184000_CLOCK_CONTROLLER
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#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS NXP_KINETIS_LPUART_40184000_CLOCK_NAME
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#define CONFIG_UART_MCUX_LPUART_3_BASE_ADDRESS NXP_KINETIS_LPUART_4018C000_BASE_ADDRESS
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#define CONFIG_UART_MCUX_LPUART_3_NAME NXP_KINETIS_LPUART_4018C000_LABEL
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#define CONFIG_UART_MCUX_LPUART_3_IRQ NXP_KINETIS_LPUART_4018C000_IRQ_0
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#define CONFIG_UART_MCUX_LPUART_3_IRQ_PRI NXP_KINETIS_LPUART_4018C000_IRQ_0_PRIORITY
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#define CONFIG_UART_MCUX_LPUART_3_BAUD_RATE NXP_KINETIS_LPUART_4018C000_CURRENT_SPEED
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#define CONFIG_UART_MCUX_LPUART_3_CLOCK_NAME NXP_KINETIS_LPUART_4018C000_CLOCK_CONTROLLER
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#define CONFIG_UART_MCUX_LPUART_3_CLOCK_SUBSYS NXP_KINETIS_LPUART_4018C000_CLOCK_NAME
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/* End of SoC Level DTS fixup file */
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