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boards: mimxrt1050_evk: Enable lpuart3 for bluetooth hci

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Enables instance 3 of the lpuart driver, adds dts fixups, and configures
pinmuxes to use bluetooth hci on the mimxrt1050_evk board. Updates board
documentation accordingly.

Tested with samples/bluetooth/peripheral_hr, with frdm_kw41z attached as
an arduino shield running the nxp hci controller application.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This commit is contained in:
Maureen Helm 2018-09-24 11:26:59 -05:00 • committed by Anas Nashif
commit c73d5c7880
5 changed files with 44 additions and 1 deletions
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3
boards/arm/mimxrt1050_evk/Kconfig.defconfig
View file

@ -41,6 +41,9 @@ if UART_MCUX_LPUART
config UART_MCUX_LPUART_1
def_bool y
config UART_MCUX_LPUART_3
def_bool y if BT_UART
endif # UART_MCUX_LPUART
if CODE_HYPERFLASH || CODE_QSPI

7
boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.rst
View file

@ -129,6 +129,10 @@ The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW0 |
+---------------+-----------------+---------------------------+
@ -141,7 +145,8 @@ board with the on-chip PLL to generate a 600 MHz core clock.
Serial Port
===========
The MIMXRT1050 SoC has eight UARTs. One is configured for the console and the
The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console,
``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the
remaining are not used.
Programming and Debugging

11
boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts
View file

@ -19,6 +19,7 @@
gpio-4= &gpio4;
gpio-5= &gpio5;
uart-1 = &uart1;
uart-3 = &uart3;
led0 = &green_led;
sw0 = &user_button;
spi-3 = &spi3;
@ -34,6 +35,9 @@
#endif
zephyr,sram = &dtcm0;
zephyr,console = &uart1;
#ifdef CONFIG_BT
zephyr,bt-uart = &uart3;
#endif
};
sdram0: memory@80000000 {
@ -86,6 +90,13 @@
current-speed = <115200>;
};
#ifdef CONFIG_BT
&uart3 {
status = "ok";
current-speed = <115200>;
};
#endif
&spi3 {
status = "ok";
};

16
boards/arm/mimxrt1050_evk/pinmux.c
View file

@ -41,6 +41,22 @@ static int mimxrt1050_evk_init(struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#ifdef CONFIG_UART_MCUX_LPUART_3
/* LPUART3 TX/RX */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#ifdef CONFIG_SPI_3
/* LPSPI3 SCK, SDO, SDI, PCS0 */
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK, 0);

8
soc/arm/nxp_imx/rt/dts.fixup
View file

@ -33,4 +33,12 @@
#define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME NXP_KINETIS_LPUART_40184000_CLOCK_CONTROLLER
#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS NXP_KINETIS_LPUART_40184000_CLOCK_NAME
#define CONFIG_UART_MCUX_LPUART_3_BASE_ADDRESS NXP_KINETIS_LPUART_4018C000_BASE_ADDRESS
#define CONFIG_UART_MCUX_LPUART_3_NAME NXP_KINETIS_LPUART_4018C000_LABEL
#define CONFIG_UART_MCUX_LPUART_3_IRQ NXP_KINETIS_LPUART_4018C000_IRQ_0
#define CONFIG_UART_MCUX_LPUART_3_IRQ_PRI NXP_KINETIS_LPUART_4018C000_IRQ_0_PRIORITY
#define CONFIG_UART_MCUX_LPUART_3_BAUD_RATE NXP_KINETIS_LPUART_4018C000_CURRENT_SPEED
#define CONFIG_UART_MCUX_LPUART_3_CLOCK_NAME NXP_KINETIS_LPUART_4018C000_CLOCK_CONTROLLER
#define CONFIG_UART_MCUX_LPUART_3_CLOCK_SUBSYS NXP_KINETIS_LPUART_4018C000_CLOCK_NAME
/* End of SoC Level DTS fixup file */