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soc: cc2650: Update DTS-derived labels with DT_ prefix

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Update a couple of labels generated from DTS used directly (not through
dts_fixups) in TI CC2650 system initialization code and a few drivers
for this SoC.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2018-11-08 11:03:32 +01:00 • committed by Kumar Gala
commit d4a17b4085
3 changed files with 16 additions and 16 deletions
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18
drivers/gpio/gpio_cc2650.c
View file

@ -41,19 +41,19 @@ static u32_t gpio_cc2650_get_pending_int(struct device *dev);
/* GPIO registers */
static const u32_t doutset31_0 =
REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
CC2650_GPIO_DOUTSET31_0);
static const u32_t doutclr31_0 =
REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
CC2650_GPIO_DOUTCLR31_0);
static const u32_t din31_0 =
REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
CC2650_GPIO_DIN31_0);
static const u32_t doe31_0 =
REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
CC2650_GPIO_DOE31_0);
static const u32_t evflags31_0 =
REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS,
CC2650_GPIO_EVFLAGS31_0);
static struct gpio_cc2650_data gpio_cc2650_data = {
@ -97,7 +97,7 @@ static void disconnect(const int pin, u32_t *gpiodoe31_0,
*/
static int gpio_cc2650_config_pin(int pin, int flags)
{
const u32_t iocfg = REG_ADDR(TI_CC2650_PINMUX_40081000_BASE_ADDRESS,
const u32_t iocfg = REG_ADDR(DT_TI_CC2650_PINMUX_40081000_BASE_ADDRESS,
CC2650_IOC_IOCFG0 + 0x4 * pin);
u32_t iocfg_config = sys_read32(iocfg);
u32_t gpio_doe31_0_config = sys_read32(doe31_0);
@ -209,11 +209,11 @@ static int gpio_cc2650_init(struct device *dev)
ARG_UNUSED(dev);
/* ISR setup */
IRQ_CONNECT(TI_CC2650_GPIO_40022000_IRQ_0,
TI_CC2650_GPIO_40022000_IRQ_0_PRIORITY,
IRQ_CONNECT(DT_TI_CC2650_GPIO_40022000_IRQ_0,
DT_TI_CC2650_GPIO_40022000_IRQ_0_PRIORITY,
gpio_cc2650_isr, DEVICE_GET(gpio_cc2650_0),
0);
irq_enable(TI_CC2650_GPIO_40022000_IRQ_0);
irq_enable(DT_TI_CC2650_GPIO_40022000_IRQ_0);
return 0;
}

4
drivers/pinmux/pinmux_cc2650.c
View file

@ -60,7 +60,7 @@
#define IOCFG_REG(Func) \
REG_ADDR(TI_CC2650_PINMUX_40081000_BASE_ADDRESS, \
REG_ADDR(DT_TI_CC2650_PINMUX_40081000_BASE_ADDRESS, \
CC2650_IOC_IOCFG0 + 0x4 * Func)
static int pinmux_cc2650_init(struct device *dev)
@ -122,7 +122,7 @@ static int pinmux_cc2650_input(struct device *dev, u32_t pin,
"I/O mode is invalid");
const u32_t iocfg = IOCFG_REG(pin);
const u32_t gpio_doe = TI_CC2650_GPIO_40022000_BASE_ADDRESS +
const u32_t gpio_doe = DT_TI_CC2650_GPIO_40022000_BASE_ADDRESS +
CC2650_GPIO_DOE31_0;
u32_t iocfg_conf = sys_read32(iocfg);
u32_t gpio_doe_conf = sys_read32(gpio_doe);

10
soc/arm/ti_simplelink/cc2650/soc.c
View file

@ -64,20 +64,20 @@ ti_ccfg[CCFG_SIZE / sizeof(u32_t)] = {
/* PRCM Registers */
static const u32_t clkloadctl =
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
CC2650_PRCM_CLKLOADCTL);
static const u32_t gpioclkgr =
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
CC2650_PRCM_GPIOCLKGR);
static const u32_t pdctl0 =
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
CC2650_PRCM_PDCTL0);
static const u32_t pdstat0 =
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
CC2650_PRCM_PDSTAT0);
#ifdef CONFIG_SERIAL
static const u32_t uartclkgr =
REG_ADDR(TI_CC2650_PRCM_40082000_BASE_ADDRESS,
REG_ADDR(DT_TI_CC2650_PRCM_40082000_BASE_ADDRESS,
CC2650_PRCM_UARTCLKGR);
#endif