xtensa: intel_s1000: Move some functions to SoC level SYS_INIT
Mux configuration for I2C and GPIO are now done in SYS_INIT which were earlier done in the respective tests. Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
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b5eb656142
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3 changed files with 38 additions and 47 deletions
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@ -146,6 +146,24 @@ void _soc_irq_disable(u32_t irq)
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}
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}
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void soc_config_iomux_ctsrts(void)
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{
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volatile struct soc_io_mux_regs *regs =
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(volatile struct soc_io_mux_regs *)IOMUX_BASE;
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/* Configure the MUX to select GPIO functionality for GPIO 23 and 24 */
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regs->io_mux_ctl0 |= SOC_UART_RTS_CTS_MS;
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}
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void soc_config_iomux_i2c(void)
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{
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volatile struct soc_io_mux_regs *regs =
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(volatile struct soc_io_mux_regs *)IOMUX_BASE;
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/* Configure the MUX to select the correct I2C port (I2C1) */
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regs->io_mux_ctl2 |= SOC_I2C_I0_I1_MS;
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}
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static inline void soc_set_resource_ownership(void)
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{
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volatile struct soc_resource_alloc_regs *regs =
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@ -225,6 +243,15 @@ static int soc_init(struct device *dev)
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soc_set_resource_ownership();
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soc_set_power_and_clock();
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#ifdef CONFIG_I2C
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soc_config_iomux_i2c();
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#endif
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#ifdef CONFIG_GPIO
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soc_config_iomux_ctsrts();
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#endif
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return 0;
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}
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@ -87,6 +87,17 @@
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#define SOC_NUM_LPGPDMAC 3
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#define SOC_NUM_CHANNELS_IN_DMAC 8
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#define IOMUX_BASE 0x00081C00
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#define SOC_I2C_I0_I1_MS BIT(0)
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#define SOC_UART_RTS_CTS_MS BIT(16)
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struct soc_io_mux_regs {
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u32_t reserved[12];
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u32_t io_mux_ctl0;
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u32_t io_mux_ctl1;
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u32_t io_mux_ctl2;
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};
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/* SOC Resource Allocation Registers */
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#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
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/* bit field definition for LP GPDMA ownership register */
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@ -10,60 +10,13 @@
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#include <logging/log.h>
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LOG_MODULE_REGISTER(main);
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#define IOMUX_BASE 0x00081C00
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#define IOMUX_CONTROL0 (IOMUX_BASE + 0x30)
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#define IOMUX_CONTROL2 (IOMUX_BASE + 0x38)
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#define TS_POWER_CONFIG 0x00071F90
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/* This semaphore is used to serialize the UART prints dumped by various
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* modules. This prevents mixing of UART prints across modules. This
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* semaphore starts off "available".
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*/
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K_SEM_DEFINE(thread_sem, 1, 1);
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/* Disable Tensilica power gating */
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void disable_ts_powergate(void)
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{
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volatile u16_t pwrcfg = *(volatile u16_t *)TS_POWER_CONFIG;
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/* Set the below bits to disable power gating:
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* BIT0 - Tensilica Core Prevent DSP Core Power Gating
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* BIT4 - Tensilica Core Prevent Controller Power Gating
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* BIT5 - Ignore D3 / D0i3 Power Gating
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* BIT6 - Tensilica Core Prevent DSP Common Power Gating
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*/
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pwrcfg |= BIT(0) | BIT(4) | BIT(5) | BIT(6);
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*(volatile u16_t *)TS_POWER_CONFIG = pwrcfg;
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}
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/* Configure the MUX to select GPIO functionality for GPIO 23 and 24 */
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void iomux_config_ctsrts(void)
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{
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volatile u32_t iomux_cntrl0 = *(volatile u32_t *)IOMUX_CONTROL0;
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/* Set bit 16 to convert the pins to normal GPIOs from UART_RTS_CTS */
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iomux_cntrl0 |= BIT(16);
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*(volatile u32_t *)IOMUX_CONTROL0 = iomux_cntrl0;
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}
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/* Configure the MUX to select the correct I2C port (I2C1) */
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void iomux_config_i2c(void)
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{
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volatile u32_t iomux_cntrl2 = *(volatile u32_t *)IOMUX_CONTROL2;
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/* Set bit 0 to select i2c1 */
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iomux_cntrl2 |= BIT(0);
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*(volatile u32_t *)IOMUX_CONTROL2 = iomux_cntrl2;
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}
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void main(void)
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{
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printk("Sample app running on: %s Intel S1000 CRB\n", CONFIG_ARCH);
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disable_ts_powergate();
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iomux_config_i2c();
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iomux_config_ctsrts();
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}
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