drivers: watchdog: wdt_sam0: Convert Atmel SAM0 driver to the new API
Convert the Atmel SAM0 watchdog driver to the new watchdog API and enable DTS support. This fixes #10914. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen
Kumar Gala
parent
7ca69b385d
commit
e5460c6bcc
4 changed files with 144 additions and 76 deletions
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@ -3,9 +3,10 @@
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# Copyright (c) 2017 Google LLC.
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# SPDX-License-Identifier: Apache-2.0
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menuconfig WDT_SAM0
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config WDT_SAM0
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bool "Atmel SAM0 series Watchdog (WDT) Driver"
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depends on SOC_FAMILY_SAM0
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select HAS_DTS_WDT
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default y
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help
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Enable WDT driver for Atmel SAM0 MCUs.
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@ -1,4 +1,5 @@
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/*
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* Copyright (c) 2018 Henrik Brix Andersen <henrik@brixandersen.dk>
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* Copyright (c) 2017 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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@ -7,138 +8,202 @@
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#include <soc.h>
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#include <watchdog.h>
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#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(wdt_sam0);
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#define WDT_REGS ((Wdt *)DT_WDT_SAM0_BASE_ADDRESS)
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struct wdt_sam0_dev_data {
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void (*cb)(struct device *dev);
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wdt_callback_t cb;
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bool timeout_valid;
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};
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static struct device DEVICE_NAME_GET(wdt_sam0);
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static struct wdt_sam0_dev_data wdt_sam0_data = { 0 };
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static void wdt_sam0_wait_synchronization(void)
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{
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while (WDT_REGS->STATUS.bit.SYNCBUSY) {
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}
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}
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static u32_t wdt_sam0_timeout_to_wdt_period(u32_t timeout_ms)
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{
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u32_t next_pow2;
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u32_t cycles;
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/* Calculate number of clock cycles @ 1.024 kHz input clock */
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cycles = (timeout_ms * 1024) / 1000;
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/* Minimum wdt period is 8 clock cycles (register value 0) */
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if (cycles <= 8)
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return 0;
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/* Round up to next pow2 and calculate the register value */
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next_pow2 = (1ULL << 32) >> __builtin_clz(cycles - 1);
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return find_msb_set(next_pow2 >> 4);
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}
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static void wdt_sam0_isr(struct device *dev)
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{
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struct wdt_sam0_dev_data *data = dev->driver_data;
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WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
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if (data->cb != NULL) {
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data->cb(dev);
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data->cb(dev, 0);
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}
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}
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static void wdt_sam0_enable(struct device *dev)
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static int wdt_sam0_setup(struct device *dev, u8_t options)
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{
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WDT_REGS->CTRL.reg = WDT_CTRL_ENABLE;
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struct wdt_sam0_dev_data *data = dev->driver_data;
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if (WDT_REGS->CTRL.reg == WDT_CTRL_ENABLE) {
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LOG_ERR("Watchdog already setup");
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return -EBUSY;
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}
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if (!data->timeout_valid) {
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LOG_ERR("No valid timeout installed");
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return -EINVAL;
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}
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if (options & WDT_OPT_PAUSE_IN_SLEEP) {
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LOG_ERR("Pause in sleep not supported");
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return -ENOTSUP;
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}
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if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
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LOG_ERR("Pause when halted by debugger not supported");
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return -ENOTSUP;
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}
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/* Enable watchdog */
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WDT_REGS->CTRL.bit.ENABLE = 1;
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wdt_sam0_wait_synchronization();
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return 0;
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}
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static int wdt_sam0_disable(struct device *dev)
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{
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WDT_REGS->CTRL.reg = 0;
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if (!WDT_REGS->CTRL.bit.ENABLE) {
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LOG_ERR("Watchdog not enabled");
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return -EFAULT;
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}
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WDT_REGS->CTRL.bit.ENABLE = 0;
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wdt_sam0_wait_synchronization();
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return 0;
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}
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static int wdt_sam0_set_config(struct device *dev, struct wdt_config *config)
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static int wdt_sam0_install_timeout(struct device *dev,
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const struct wdt_timeout_cfg *cfg)
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{
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struct wdt_sam0_dev_data *data = dev->driver_data;
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WDT_CTRL_Type ctrl = WDT_REGS->CTRL;
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int divisor;
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u32_t window, per;
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/* As per wdt_esp32.c, the Zephyr watchdog API is modeled
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* after the Quark MCU where:
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*
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* timeout_ms = 2**(config->timeout + 11) / 1000
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*
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* The SAM0 is also power-of-two based with a 1 kHz clock, so
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* 2**14 / 1kHz ~= 2**29 / 32 MHz.
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*/
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divisor = config->timeout + WDT_CONFIG_PER_16K_Val - WDT_2_29_CYCLES;
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/* Limit to 16x so that 8x is available for early warning. */
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if (divisor < WDT_CONFIG_PER_16_Val) {
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return -EINVAL;
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} else if (divisor > WDT_CONFIG_PER_16K_Val) {
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return -EINVAL;
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/* CONFIG is enable protected, error out if already enabled */
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if (WDT_REGS->CTRL.bit.ENABLE) {
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LOG_ERR("Watchdog already setup");
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return -EBUSY;
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}
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/* Disable the WDT to change the config. */
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wdt_sam0_disable(dev);
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switch (config->mode) {
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case WDT_MODE_RESET:
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WDT_REGS->INTENCLR.reg = WDT_INTENCLR_EW;
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wdt_sam0_wait_synchronization();
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break;
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case WDT_MODE_INTERRUPT_RESET:
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/* Fire the early warning earlier. */
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WDT_REGS->EWCTRL.bit.EWOFFSET = divisor - 1;
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wdt_sam0_wait_synchronization();
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/* Clear the pending interrupt, if any. */
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WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
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wdt_sam0_wait_synchronization();
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WDT_REGS->INTENSET.reg = WDT_INTENSET_EW;
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wdt_sam0_wait_synchronization();
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break;
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default:
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return -EINVAL;
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if (cfg->flags != WDT_FLAG_RESET_SOC) {
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LOG_ERR("Only SoC reset supported");
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return -ENOTSUP;
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}
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WDT_REGS->CONFIG.bit.PER = divisor;
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wdt_sam0_wait_synchronization();
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per = wdt_sam0_timeout_to_wdt_period(cfg->window.max);
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if (per > WDT_CONFIG_PER_16K_Val) {
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LOG_ERR("Upper limit timeout out of range");
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goto timeout_invalid;
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}
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data->cb = config->interrupt_fn;
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WDT_REGS->CTRL = ctrl;
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wdt_sam0_wait_synchronization();
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return 0;
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}
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static void wdt_sam0_get_config(struct device *dev, struct wdt_config *config)
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{
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struct wdt_sam0_dev_data *data = dev->driver_data;
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if (WDT_REGS->INTENSET.bit.EW) {
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config->mode = WDT_MODE_INTERRUPT_RESET;
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if (cfg->window.min) {
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/* Window mode */
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window = wdt_sam0_timeout_to_wdt_period(cfg->window.min);
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if (window > WDT_CONFIG_PER_8K_Val) {
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LOG_ERR("Lower limit timeout out of range");
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goto timeout_invalid;
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}
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if (per <= window) {
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/* Ensure we have a window */
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per = window + 1;
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}
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WDT_REGS->CTRL.bit.WEN = 1;
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wdt_sam0_wait_synchronization();
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} else {
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config->mode = WDT_MODE_RESET;
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/* Normal mode */
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if (cfg->callback) {
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if (per == WDT_CONFIG_PER_8_Val) {
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/* Ensure we have time for the early warning */
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per += 1;
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}
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WDT_REGS->EWCTRL.bit.EWOFFSET = per - 1;
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}
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window = WDT_CONFIG_PER_8_Val;
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WDT_REGS->CTRL.bit.WEN = 0;
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wdt_sam0_wait_synchronization();
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}
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config->timeout = WDT_REGS->CONFIG.bit.PER
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+ WDT_2_29_CYCLES - WDT_CONFIG_PER_16K_Val;
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config->interrupt_fn = data->cb;
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WDT_REGS->CONFIG.reg = WDT_CONFIG_WINDOW(window) | WDT_CONFIG_PER(per);
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wdt_sam0_wait_synchronization();
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/* Only enable IRQ if a callback was provided */
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data->cb = cfg->callback;
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if (data->cb) {
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WDT_REGS->INTENSET.reg = WDT_INTENSET_EW;
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} else {
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WDT_REGS->INTENCLR.reg = WDT_INTENCLR_EW;
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WDT_REGS->INTFLAG.reg = WDT_INTFLAG_EW;
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}
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data->timeout_valid = true;
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return 0;
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timeout_invalid:
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data->timeout_valid = false;
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data->cb = NULL;
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return -EINVAL;
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}
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static void wdt_sam0_reload(struct device *dev)
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static int wdt_sam0_feed(struct device *dev, int channel_id)
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{
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WDT_REGS->CLEAR.bit.CLEAR = WDT_CLEAR_CLEAR_KEY_Val;
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struct wdt_sam0_dev_data *data = dev->driver_data;
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if (!data->timeout_valid) {
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LOG_ERR("No valid timeout installed");
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return -EINVAL;
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}
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WDT_REGS->CLEAR.reg = WDT_CLEAR_CLEAR_KEY_Val;
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return 0;
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}
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static const struct wdt_driver_api wdt_sam0_api = {
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.enable = wdt_sam0_enable,
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.setup = wdt_sam0_setup,
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.disable = wdt_sam0_disable,
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.get_config = wdt_sam0_get_config,
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.set_config = wdt_sam0_set_config,
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.reload = wdt_sam0_reload,
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.install_timeout = wdt_sam0_install_timeout,
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.feed = wdt_sam0_feed,
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};
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static int wdt_sam0_init(struct device *dev)
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{
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#ifdef CONFIG_WDT_DISABLE_AT_BOOT
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/* Ignore any errors */
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wdt_sam0_disable(dev);
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#endif
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/* Enable APB clock */
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PM->APBAMASK.bit.WDT_ = 1;
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/* Connect to GCLK2 (~1 kHz) */
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/* Connect to GCLK2 (~1.024 kHz) */
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID_WDT
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| GCLK_CLKCTRL_GEN_GCLK2
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| GCLK_CLKCTRL_CLKEN;
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@ -153,6 +218,6 @@ static int wdt_sam0_init(struct device *dev)
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static struct wdt_sam0_dev_data wdt_sam0_data;
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DEVICE_AND_API_INIT(wdt_sam0, CONFIG_WDT_0_NAME, wdt_sam0_init,
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DEVICE_AND_API_INIT(wdt_sam0, DT_WDT_SAM0_LABEL, wdt_sam0_init,
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&wdt_sam0_data, NULL, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_sam0_api);
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@ -91,6 +91,7 @@
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#define DT_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY
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#define DT_WDT_SAM0_LABEL DT_ATMEL_SAM0_WATCHDOG_40001000_LABEL
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#define DT_WDT_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS
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#define CONFIG_WDT_0_NAME DT_WDT_SAM0_LABEL
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#define DT_PINMUX_SAM0_A_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS
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#define DT_PINMUX_SAM0_A_LABEL DT_ATMEL_SAM0_PINMUX_41004400_LABEL
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@ -91,6 +91,7 @@
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#define DT_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY
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#define DT_WDT_SAM0_LABEL DT_ATMEL_SAM0_WATCHDOG_40001000_LABEL
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#define DT_WDT_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS
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#define CONFIG_WDT_0_NAME DT_WDT_SAM0_LABEL
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#define DT_PINMUX_SAM0_A_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS
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#define DT_PINMUX_SAM0_A_LABEL DT_ATMEL_SAM0_PINMUX_41004400_LABEL
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