xtensa: intel_s1000: turn on XTENSA_ASM2
This adds the necessary bits to support ASM2 with XCC for Intel S1000 SoC. With ASM2 enabled, xcc is now required to build for Intel S1000 SoC. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
Anas Nashif
parent
ecfc1b4ec1
commit
c229126f55
4 changed files with 270 additions and 0 deletions
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@ -7,3 +7,7 @@ board_finalize_runner_args(intel_s1000
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"--ocd-jtag-instr=dsp0_gdb.txt"
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"--gdb-flash-file=load_elf.txt"
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)
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if(NOT "${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc")
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message(FATAL_ERROR "ZEPHYR_TOOLCHAIN_VARIANT != xcc. This requires xcc to build!")
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endif()
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@ -12,4 +12,12 @@ config SOC
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config IRQ_OFFLOAD_INTNUM
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default 0
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config XTENSA_ASM2
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def_bool y
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# S1000 does not have MISC0.
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# Since EXCSAVE2 is unused by Zephyr, use it instead.
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config XTENSA_KERNEL_CPU_PTR_SR
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default "EXCSAVE2"
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endif
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257
soc/xtensa/intel_s1000/include/_soc_inthandlers.h
Normal file
257
soc/xtensa/intel_s1000/include/_soc_inthandlers.h
Normal file
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@ -0,0 +1,257 @@
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/*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* Functions here are designed to produce efficient code to
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* search an Xtensa bitmask of interrupts, inspecting only those bits
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* declared to be associated with a given interrupt level. Each
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* dispatcher will handle exactly one flagged interrupt, in numerical
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* order (low bits first) and will return a mask of that bit that can
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* then be cleared by the calling code. Unrecognized bits for the
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* level will invoke an error handler.
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*/
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#include <xtensa/config/core-isa.h>
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#include <sw_isr_table.h>
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#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7
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#error core-isa.h interrupt level does not match dispatcher!
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#endif
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static inline int _xtensa_handle_one_int1(unsigned int mask)
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{
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if (mask & 0x3) {
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if (mask & (1 << 0)) {
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struct _isr_table_entry *e = &_sw_isr_table[0];
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e->isr(e->arg);
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return 1 << 0;
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}
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if (mask & (1 << 1)) {
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struct _isr_table_entry *e = &_sw_isr_table[1];
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e->isr(e->arg);
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return 1 << 1;
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}
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} else {
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if (mask & (1 << 2)) {
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struct _isr_table_entry *e = &_sw_isr_table[2];
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e->isr(e->arg);
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return 1 << 2;
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}
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if (mask & (1 << 3)) {
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struct _isr_table_entry *e = &_sw_isr_table[3];
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e->isr(e->arg);
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return 1 << 3;
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}
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int2(unsigned int mask)
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{
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if (mask & 0x30) {
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if (mask & (1 << 4)) {
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struct _isr_table_entry *e = &_sw_isr_table[4];
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e->isr(e->arg);
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return 1 << 4;
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}
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if (mask & (1 << 5)) {
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struct _isr_table_entry *e = &_sw_isr_table[5];
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e->isr(e->arg);
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return 1 << 5;
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}
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} else {
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if (mask & (1 << 6)) {
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struct _isr_table_entry *e = &_sw_isr_table[6];
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e->isr(e->arg);
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return 1 << 6;
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}
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if (mask & (1 << 7)) {
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struct _isr_table_entry *e = &_sw_isr_table[7];
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e->isr(e->arg);
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return 1 << 7;
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}
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int3(unsigned int mask)
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{
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if (mask & 0x300) {
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if (mask & (1 << 8)) {
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struct _isr_table_entry *e = &_sw_isr_table[8];
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e->isr(e->arg);
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return 1 << 8;
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}
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if (mask & (1 << 9)) {
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struct _isr_table_entry *e = &_sw_isr_table[9];
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e->isr(e->arg);
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return 1 << 9;
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}
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} else {
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if (mask & (1 << 10)) {
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struct _isr_table_entry *e = &_sw_isr_table[10];
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e->isr(e->arg);
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return 1 << 10;
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}
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if (mask & (1 << 11)) {
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struct _isr_table_entry *e = &_sw_isr_table[11];
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e->isr(e->arg);
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return 1 << 11;
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}
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int4(unsigned int mask)
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{
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if (mask & (1 << 12)) {
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struct _isr_table_entry *e = &_sw_isr_table[12];
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e->isr(e->arg);
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return 1 << 12;
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}
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if (mask & (1 << 13)) {
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struct _isr_table_entry *e = &_sw_isr_table[13];
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e->isr(e->arg);
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return 1 << 13;
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}
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if (mask & (1 << 14)) {
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struct _isr_table_entry *e = &_sw_isr_table[14];
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e->isr(e->arg);
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return 1 << 14;
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int5(unsigned int mask)
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{
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if (mask & 0x18000) {
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if (mask & (1 << 15)) {
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struct _isr_table_entry *e = &_sw_isr_table[15];
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e->isr(e->arg);
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return 1 << 15;
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}
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if (mask & (1 << 16)) {
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struct _isr_table_entry *e = &_sw_isr_table[16];
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e->isr(e->arg);
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return 1 << 16;
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}
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} else {
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if (mask & (1 << 17)) {
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struct _isr_table_entry *e = &_sw_isr_table[17];
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e->isr(e->arg);
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return 1 << 17;
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}
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if (mask & (1 << 18)) {
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struct _isr_table_entry *e = &_sw_isr_table[18];
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e->isr(e->arg);
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return 1 << 18;
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}
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if (mask & (1 << 19)) {
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struct _isr_table_entry *e = &_sw_isr_table[19];
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e->isr(e->arg);
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return 1 << 19;
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}
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int7(unsigned int mask)
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{
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if (mask & (1 << 20)) {
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struct _isr_table_entry *e = &_sw_isr_table[20];
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e->isr(e->arg);
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return 1 << 20;
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}
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return 0;
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}
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static inline int _xtensa_handle_one_int0(unsigned int mask)
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{
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return 0;
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}
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static inline int _xtensa_handle_one_int6(unsigned int mask)
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{
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return 0;
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}
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@ -315,6 +315,7 @@ SECTIONS
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_text_start = ABSOLUTE(.);
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*(.entry.text)
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*(.init.literal)
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*(.iram0.text)
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KEEP(*(.init))
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.fini.literal)
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