soc: logging: move soc tree to new logger
Use the new logger framework for soc related code. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
parent
8e38670af3
commit
071c9dc0f3
7 changed files with 36 additions and 44 deletions
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@ -10,4 +10,9 @@ menu "Hardware Configuration"
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osource "$(SOC_DIR)/$(ARCH)/Kconfig"
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osource "$(SOC_DIR)/$(ARCH)/*/Kconfig"
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module = SOC
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module-str = SOC
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source "subsys/logging/Kconfig.template.log_config"
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endmenu
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@ -24,6 +24,9 @@ extern void _NmiInit(void);
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#endif
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#include <system_nrf51.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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static int nordicsemi_nrf51_init(struct device *arg)
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{
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@ -3,14 +3,14 @@
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SYS_LOG_LEVEL SYS_LOG_LEVEL_DEBUG
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#include <logging/sys_log.h>
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#include <zephyr.h>
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#include <soc_power.h>
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#include <nrf_power.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_DECLARE(soc);
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#if defined(CONFIG_SYS_POWER_DEEP_SLEEP)
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/* System_OFF is deepest Power state available, On exiting from this
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* state CPU including all peripherals reset
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@ -48,7 +48,7 @@ static void _low_power_mode(enum power_states state)
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default:
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/* Unsupported State */
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SYS_LOG_ERR("Unsupported State\n");
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LOG_ERR("Unsupported State");
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break;
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}
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@ -73,7 +73,7 @@ void _sys_soc_set_power_state(enum power_states state)
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#endif
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default:
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/* Unsupported State */
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SYS_LOG_ERR("Unsupported State\n");
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LOG_ERR("Unsupported State");
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break;
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}
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}
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@ -93,7 +93,7 @@ void _sys_soc_power_state_post_ops(enum power_states state)
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#endif
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default:
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/* Unsupported State */
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SYS_LOG_ERR("Unsupported State\n");
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LOG_ERR("Unsupported State");
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break;
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}
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}
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@ -109,7 +109,7 @@ bool _sys_soc_is_valid_power_state(enum power_states state)
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return true;
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break;
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default:
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SYS_LOG_DBG("Unsupported State\n");
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LOG_DBG("Unsupported State");
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break;
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}
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@ -36,6 +36,10 @@ extern void _NmiInit(void);
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#include <nrf.h>
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#include <hal/nrf_power.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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static int nordicsemi_nrf52_init(struct device *arg)
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{
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u32_t key;
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@ -27,26 +27,6 @@ config ARC_INIT
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help
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Allows x86 processor to kickoff the ARC slave processor.
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config SYS_LOG_ARC_INIT_LEVEL
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int "Quark SE Sensor Subsystem log level"
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depends on SYS_LOG
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default 0
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help
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Sets log level for the boot initialization and boot process of the sensor
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sub-system.
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Levels are:
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- 0 OFF, do not write
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- 1 ERROR, only write SYS_LOG_ERR
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- 2 WARNING, write SYS_LOG_WRN in addition to previous level
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- 3 INFO, write SYS_LOG_INF in addition to previous levels
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- 4 DEBUG, write SYS_LOG_DBG in addition to previous levels
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config ARC_GDB_ENABLE
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bool "Allows the usage of GDB with the ARC processor."
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depends on ARC_INIT
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@ -23,6 +23,9 @@
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#include "shared_mem.h"
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#include <mmustructs.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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#ifdef CONFIG_X86_MMU
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/* loapic */
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@ -50,9 +53,6 @@ MMU_BOOT_REGION(0xB0500000, 256*1024, MMU_ENTRY_WRITE);
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#define SCSS_REG_VAL(offset) \
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(*((volatile u32_t *)(SCSS_REGISTER_BASE+offset)))
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_ARC_INIT_LEVEL
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#include <logging/sys_log.h>
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/**
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*
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* @brief ARC Init
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@ -78,12 +78,12 @@ int _arc_init(struct device *arg)
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* we read the value and stick it in shared_mem->arc_start which is
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* the beginning of the address space at 0xA8000000 */
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reset_vector = (u32_t *)RESET_VECTOR;
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SYS_LOG_DBG("Reset vector address: %x", *reset_vector);
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LOG_DBG("Reset vector address: %x", *reset_vector);
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shared_data->arc_start = *reset_vector;
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shared_data->flags = 0;
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if (!shared_data->arc_start) {
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/* Reset vector points to NULL => skip ARC init. */
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SYS_LOG_DBG("Reset vector is NULL, skipping ARC init.");
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LOG_DBG("Reset vector is NULL, skipping ARC init.");
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goto skip_arc_init;
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}
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@ -92,14 +92,14 @@ int _arc_init(struct device *arg)
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SCSS_REG_VAL(SCSS_SS_CFG) |= ARC_RUN_REQ_A;
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#endif
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SYS_LOG_DBG("Waiting for arc to start...");
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LOG_DBG("Waiting for arc to start...");
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/* Block until the ARC core actually starts up */
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while (SCSS_REG_VAL(SCSS_SS_STS) & 0x4000) {
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}
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/* Block until ARC's quark_se_init() sets a flag indicating it is ready,
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* if we get stuck here ARC has run but has exploded very early */
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SYS_LOG_DBG("Waiting for arc to init...");
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LOG_DBG("Waiting for arc to init...");
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while (!(shared_data->flags & ARC_READY)) {
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}
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@ -4,18 +4,18 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SYS_LOG_LEVEL SYS_LOG_LEVEL_INFO
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#define SYS_LOG_DOMAIN "soc/s1000"
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#include <device.h>
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#include <xtensa_api.h>
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#include <xtensa/xtruntime.h>
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#include <logging/sys_log.h>
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#include <board.h>
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#include <irq_nextlevel.h>
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#include <xtensa/hal.h>
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#include <init.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(soc);
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static u32_t ref_clk_freq;
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void _soc_irq_enable(u32_t irq)
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@ -42,7 +42,7 @@ void _soc_irq_enable(u32_t irq)
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}
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if (!dev_cavs) {
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SYS_LOG_DBG("board: CAVS device binding failed\n");
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LOG_DBG("board: CAVS device binding failed");
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return;
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}
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@ -62,7 +62,7 @@ void _soc_irq_enable(u32_t irq)
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}
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if (!dev_ictl) {
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SYS_LOG_DBG("board: DW intr_control device binding failed\n");
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LOG_DBG("board: DW intr_control device binding failed");
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return;
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}
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@ -101,7 +101,7 @@ void _soc_irq_disable(u32_t irq)
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}
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if (!dev_cavs) {
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SYS_LOG_DBG("board: CAVS device binding failed\n");
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LOG_DBG("board: CAVS device binding failed");
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return;
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}
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@ -125,7 +125,7 @@ void _soc_irq_disable(u32_t irq)
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}
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if (!dev_ictl) {
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SYS_LOG_DBG("board: DW intr_control device binding failed\n");
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LOG_DBG("board: DW intr_control device binding failed");
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return;
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}
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@ -221,7 +221,7 @@ static int soc_init(struct device *dev)
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soc_read_bootstraps();
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ref_clk_freq = soc_get_ref_clk_freq();
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SYS_LOG_INF("Reference clock frequency: %u Hz", ref_clk_freq);
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LOG_INF("Reference clock frequency: %u Hz", ref_clk_freq);
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soc_set_resource_ownership();
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soc_set_power_and_clock();
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