Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Deprecate the advanced CAN timing devicetree properties in favor of setting
advanced timing parameters from application code.
The advanced timing properties are giving in number of time quanta (Tq) and
requires reverse-calculation to find a suitable CAN clock divider. The
resulting bitrate error is compared against a threshold in the driver
initialization code, but the application is not able to retrieve it.
Forcing applications to use the CAN timing APIs directly instead makes it
up to the application to determine if the bitrate error is acceptable or
not.
The deprecated properties are:
- prop-seg
- phase-seg1
- phase-seg2
- prop-seg-data
- phase-seg1-data
- phase-seg2-data
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add phandle prop to reference any regulator that must
be enabled in order for the LPADC to function as intended.
Change LPADC driver to use this property if present.
LPADC on LPC55S36 depends on VREF peripheral, enable for this platform.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add binding, include header, and driver for NXP VREF IP block.
NXP VREF is an internal voltage reference generator on some SOCs
that fits well with the regulator API in zephyr.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:
- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers
Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).
Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This platform (SOC_SERIES_EFM32PG1B) is also using SOC_GECKO_SERIES1 and
needs a pinctrl device defined to build the gecko-uart driver
successfully.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The gecko UART driver needs pinctrl support for SOC_GECKO_SERIES1
devices, this has been added to jg and pg 12b series in 40fa96506b but
is missing in others, causing some build failurse.
Add the device nodes for the gg11b and gg12b files since they contain
gecko-uart references and seems to be under the SERIES1 define.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Rework RAM disk driver to be configured using devicetree and
support multiple instances.
This patch also removes a copy of the RAM disk driver,
tests/subsys/fs/fat_fs_dual_drive/src/disk_access_test_drv.c,
that was there for testing multiple disk drivers support.
Bonus: one SYS_INIT() less and a memory region can be exported to the
host.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
LP/HP RING OSC clocks were replaced by the ACE IPLL clock.
If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
LP/HP RING OSC clocks were replaced by the ACE IPLL clock.
If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.
Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The ACE family platforms do not have LP/HP RING OSC clocks. They were
replaced by the ACE IP integrated PLL clock. Selecting LP or HP in
CLKCTL will result in enabling IPLL.
Clock can supply frequencies for both replaced clocks, default frequency
equals to 393.2 MHz.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This creates separate dtsi files for the various memory density codes of
SAM X2xfamilies (they are the same where the specific size exists.)
All of the boards with the exclusion of EV11L78A use the same density
model of 18 (32KiB RAM and 256KiB flash) which is what the samd2x.dtsi
include specified for all of them previously.
The density code has been confirmed being the same across the D20/D21,
C20/C21, L21, and R21 families. This does not carry over to some other
series such as the E5x.
Signed-off-by: Diego Elio Pettenò <flameeyes@meta.com>
Add SRAM code region definition to RT6xx series SOC. The RT6xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SRAM code region definition to RT5xx series SOC. The RT5xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add yaml file for 'xen,xen', because without it an appropriate
'CONFIG_DT_HAS_XEN_XEN_ENABLED' isn't generated.
It will be used for checking Xen support on current setup, instead of
checking if it is BOARD/SOC "xenvm" (which is not correct for Domain-0
configurations).
Remove xen,xen-4.15.yaml at all, because it isn't necessary to have
yaml for some specific Xen version.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
This commit adds support for the ATMEL HSMCI peripheral
for the SAM4E MCU series, enabling native SD card support.
Signed-off-by: Vincent van Beveren <v.van.beveren@nikhef.nl>
The zdsp.basicmath needs a bit more ROM space to run.
So enlarge the indicated ROM size to accommodate that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
D extension implies the F extension, so writing `rv32ifd` is redundant
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit removes the enum array with allowed values for the `riscv,isa`
field. There are many ways in which RISC-V ISA extension string can be
represented, and listing them all is futile. In addition, custom extensions
can be implemented, meaning every extension would have to be listed in the
enum array as well.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
While most of the ST family SoCs have the compatible string set, several
targets still miss it.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Add a MBOX driver wrapper around the NXP MU, simular to
the existing wrapper around the NXP S32 MRU. This allows Zephyr IPC
to work based on the MU, on a number of NXP boards.
Also update the SHA of NXP HAL to enable the Kconfig for this driver.
Signed-off-by: Yicheng Li <yichengli@google.com>
Determine sh1106 from the `compatibility` value instead of
the SSD1306_CONTROLLER_TYPE setting.
Change the settings in `boards/shields/ssd1306/sh1106_128x64.overlay`
to follow this change.
Remove the SSD1306_CONTROLLER_TYPE from its Kconfig.defconfig,
and set the `compatibility` to `sinowealth,sh1106`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
When multiple devices are connected, the SSD1306_REVERSE_MODE setting
cannot switch for each device.
Add an equivalent setting to the devicetree properties to replace it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Moved the interrupt handling code from a bus-specific binding file to
the parent binding file. This modification ensures that interrupt
handling, which is inherently independent of the type of BUS used
(either i2c or spi), is located in the appropriate location within
the code.
Previously, this code was found in a bus-specific file, despite its
functionality being applicable to all buses. This change ensures a
more logical placement and will help to maintain coherence within the
codebase.
This change aligns with the existing implementation where the interrupt
handling code already operates independently of the BUS type.
Tested this on a nrf52840 with a bmi270 on spi bus with the sample from
zephyr/samples/sensor/bmi270 by adding an interrupt handler in main.c
which uses the bmi270_trigger.c implementation and verified this with
breakpoints and log output.
Added the irq-gpios to tests/drivers/build_all/sensor/i2c.dtsi and
tests/drivers/build_all/sensor/spi.dtsi and fixed whitespace formatting.
Fixes: #58843
Signed-off-by: Andreas Wiesinger <awiesing90@gmail.com>
The current implementation uses both, host and card capabilites to derive
the maximum bus width to be used. However, in cases where a MMC device is
not connected to the host via shdc using the full bus width of 8 lines,
device initialization fails. Introducing the `bus-width` property
circumvents this by reducing the host bus capabilites and forcing
communication with the MMC device using 1, 4 or 8 lines.
Signed-off-by: Mourad Kharrazi <mourad.kharrazi@ithinx.io>
Add a pseudo device which can be used to hook into qdec events and
optionally a button and relay the input_event to lvgl.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Initial version of Infineon CAT1 SPI Driver supporting synchronous
and asynchronous data transfer API
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add devicetree binding for the TI TCAN4x5x series of CAN controllers. These
CAN controllers are based on the Bosch M_CAN IP and interfaced via a SPI
bus.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Create dac_mcxu_lpdac.c file to implement mcux lpdac, add binding for
the mcux lpdac, update Kconfig.mcux and CMakeLists.txt file to support
mcux lpdac.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
The Nuvoton NCT38xx is a multi-function device providing a TCPC
controller and a I/O expander (GPIO driver). Add a multi-function
driver to manage exclusive access to the device.
Tested with "twister -T tests/drivers/build_all/gpio".
Signed-off-by: Keith Short <keithshort@google.com>
Seems like the SSD1306 controller needs a bit of time after power up
before it can take i2c commands. This causes problems with
microcontrollers that have no other delays in the startup sequence, like
rpi_pico.
There's currently no good way of modeling this in Zephyr right now, and
there's also no clear indication of how much time the device needs in
the datasheet that I could find, but it seems like 10ms is enough for
that to start reliably so add a delay in the ssd1306 init function to
ensure that at least that time has passed from system power up.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add `thr-sel` prop. to select the relevant threshold register for adc
comparator since there're two adc modules in npcx4 series.
Signed-off-by: Kate Yen <htyen@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
Compat strings in SoCs allow tools to identify hardware described in
flattened device trees.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Previously the pwm capture only support capturing on channel 1
and 2, because the slave mode controller was used, which uses
the signal TIxFP which is not available for channel 3 and 4.
This commit adds optional support for four channel capturing by
changing the method of capturing PWM signals to not use the
slave mode controller to reset the counter register. Instead the
counter is reset in the ISR. This will result in a slight loss
of accuracy but is still within an acceptable range.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
This commit adds option to dump i2c messages of only specified
devices. It makes it easier to debug communication of specific
i2c device instead of logging all i2c communication.
The filter of devices is specifiec in device-tree using the
node with "zephyr,i2c-dump-filter" compatible string.
Example of device-tree node:
i2c-dump-filter {
compatible = "zephyr,i2c-dump-filter";
devices = < &display0 >, < &sensor3 >;
};
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This introduces PWM driver with supporting PWM output
APIs based on NXP S32 EMIOS peripheral. This supports
three mode: OPWFMB, OPWMCB and OPWMB.
OPWFMB uses internal counter, the new period and duty
cycle takes effect immediately.
OPWMCB and OPWMB use external counter as timebase, changing
PWM period at runtime will impact to all channels share the
same timebase. Also the new period and duty cycle take effect
in next period boundary of the timebase
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This PR adds a misc driver for NXP S32 eMIOS peripheral.
eMIOS provides multiple unified channels (UCs), there are
several channels can be used as reference timebase
(master bus) for other channels. At this time, the
driver does initialize global configuration for eMIOS
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.
Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
Add TI VIM (Vectored Interrupt Manager) interrupt controller support.
VIM is a TI specific custom interrupt controller for ARM cores.
In J721E soc, VIM aggregates interrupts to Cortex R5 cores.
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
VIM: section 6.3.3.6
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Add fundamental feature support for RP2040 PIO SPI peripherals.
This commit implements synchronous transfer with 8-bit MSB
format. Using PIO allows any GPIO pins to be assigned the roles
of CS, CLK, MOSI, and MISO.
Optional features not implemented yet:
- Interrupt based transfer
- DMA transfer
- Slave mode
- Varying word size
- 3-wire SPI support
- LSB-first
Updated in response to review comments.
Further updates from second round of review.
Rename spi_pico_pio.c source to match zephyr/MAINTAINERS.yml
Remove unnecessary initialization code.
Resolve merge conflicts
Signed-off-by: Steve Boylan <stephen.boylan@beechwoods.com>
As per #26393, Local APIC is using Kconfig based option for
the base address. This patch adds DTS binding support in the driver,
just like its conunter part I/O APIC.
Signed-off-by: Umar Nisar <umar.nisar@intel.com>
Add missing definitions for ALH DAIs. Keep the same FIXME
reminder in the comments we have for ACE1.5 that explains
the background of these definitions.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reported-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
i.MX RT SoC have some pins related to the watchdog.
For example, iomuxc_gpio_ad_b0_15_wdog1_rst_b_deb allows WDOG1_RST_B_DEB
signal to be used as reset source for i.MX RT10xx boards.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
Update SNVS pin names in RT11xx DTSI files to align with new pin data
generated for the RT1176 and RT1166 processors. This pin data is stored
within the NXP HAL, so the SHA of the HAL is also updated by this
commit.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
To properly setup L1 exit timing this patch will use buffer interrupt
for HOST DMA and wait for Host HDA to actually start
First interrupt will clear all others.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Davinci gpio controller support to add various soc gpio
support (J721E, AM654).
TRM for J721e https://www.ti.com/lit/zip/spruil1
File: spruil1c.pdf
GPIO: section 12.1.2
BeagleBone AI_64 https://beagleboard.org/ai-64
Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
Created a seperate device tree file for the stm32f765.
Moved common nodes from the stm32f767 device tree file to the new file and
based the stm32f767 off the stm32f765.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
Allow use of multiple mb85rc frams at contiguous i2c addresses as a single
big fram module.
Tested on mb85rc1mt used as two 32K modules, where the first one was at
mb85rc1mt's first i2c address and the second one at mb85rc1mt's second i2c
address.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
The added cellular modem driver is a naive driver, which
shall serve as a template for implementing tailored
drivers for modems like the UBLOX-R4. It uses only
generic at commands, described in 3gpp, and protocols,
like CMUX and PPP.
A binding for the BG95 has been added, which replaces
the quectel,bg9x. This is neccesary since the BG95 does
not have a usable reset pin, the reset and powerkey are
internally connected to each other.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
The current-shunt calibration requires a factor of 4x if high-precision
mode is selected.
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
STM32L1, U5 and WBA can only have an asynchronous clock source for ADC.
STM32F2, F4 and F7 can only have a synchronous clock source for ADC.
For all these series, it can be defined directly in the dtsi files.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add two properties to define the STM32 ADC clock source:
- Clock source: synchronous or asynchronous
- Clock prescaler
By combining these two parameters, it will be possible to set the desired
ADC clock for most series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a pseudo device which can be used to hook into gpio-keys input_events
and relay the events to a lv_indev.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
Add the scaffolding to create input lvgl pseudo devices which route zephyr
input_event to their lvgl `indev` equivalent. As a first cut also add a
`zephyr,lvgl-pointer-input compatible which can be a drop-in replacement
for the existing kscan solution.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
This commit changes the I2C instance to IOM.
IOM instance can be I2C or SPI. The choice of either
using I2C or SPI should be made in board DTS.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Added configuration of termination current and trickle voltage
Added option to bypass low voltage charge inhibit
Added option to disable automatic recharge
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
/delete-node/ pointing at node labels needs to be out of the the tree
hierarchy, fixes the error:
devicetree error: zephyr/dts/arm/nordic/nrf52840_qfaa.dtsi:24 (column
16): parse error: expected node name
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
AXP192 is a small power management IC, that also
features 5 GPIOS.
Besides GPIO driver this commit also includes needed modifications
in axp192 regulator and mfd driver as LDOIO0 functioanlity
is multiplexed with GPIO0 pin.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Many fuel gauge ICs offer a battery cutoff/shipping mode functionality that
cutoff charge from the battery. This is often useful for preserving battery
charge on devices while in storage.
Add battery cutoff support to the fuel gauge API with a generic default SBS
driver showing an example of support in tests.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
This adds QSPI controller properties that allow tuning
chip select timings (needed for accessing QSPI at high speed)
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
RC32K/RCX/XTAL32K were present in device tree as fixed-clock.
Now calibration time for RCX and RC32K is added and settle time
for XTAL32K so additional binding is created.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add support for SPI host command backend for STM32 chips family.
Unfortunately, the current SPI API can't be used to handle the host
commands communication. The main issues are unknown command size sent
by the host(the SPI transaction sends/receives specific number of bytes)
and need to constant sending status byte(the SPI module is enabled and
disabled per transaction). Thus the SPI backend includes basic SPI STM32
driver adjusted to host command specification.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Add basic support of 'regulator-gpio'. For now, it is support
only controling voltage and driver presents only six functions:
* enable and disable the regulator;
* set and get voltage;
* count and list of voltage(s).
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This enables the power management for Intel ISH. It supports D0i1,
D0i2, D0i3 power saving modes for ISH.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
This adds support for the max1125x (max11254, max11254)
family of spi adc devices.
Signed-off-by: Mustafa Abdullah Kus <mustafa.kus@sparsetechnology.com>
The interrupt-map was missing the priority field.
This causes a build failure when trying to use it.
The lines are split to fit into the 100 column limit.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Now that all in-tree phys are declared under their mdio bus, drop the
`mdio` property and use DT_INST_BUS to find the bus.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
To better delimit renesas ranges dts, we need to use ranges folder.
It will also help maintainers to better delimit their files to
be notified about.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Since VWGPSM (Virtual Wire GPIO Target-to-Controller) registers are
introduced in npcx9 and later series, the CL moves the related DT nodes
from npcx-espi-vws-map.dtsi (Used for all npcx series) to the specific
dtsi files for npcx9 and npcx4 series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
When we lock an hwspinlock, we must write the CPU identifier to
the hwspinlock register. If we want to unlock the locked hwspinlock,
we have to rewrite the same CPU identifier.
To define the CPU identifier, we use affinity 1 and affinity 2 fields
of the MPIDR register.
Signed-off-by: Aziz Idomar <aidomar@sequans.com>
Rename the base device-tree for the AM62x M4F from a SK EVM specific
to a more generic name since this DT describes the M4F subsystem in
the AM62x SoC.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Add support for ADIN1110 10BASE-T1L Ethernet MAC-PHY.
The ADIN1110 is an ultra low power, single port, 10BASE-T1L
transceiver design for industrial Ethernet applications and is com-
pliant with the IEEE® 802.3cg-2019™ Ethernet standard for long
reach, 10 Mbps single pair Ethernet (SPE). Featuring an integrated
media access control (MAC) interface, the ADIN1110 enables direct
connectivity with a variety of host controllers via a 4-wire serial
peripheral interface (SPI). This SPI enables the use of lower power
processors without an integrated MAC, which provides for the
lowest overall system level power consumption. The SPI can be
configured to use the Open Alliance SPI protocol or a generic SPI
protocol.
Documentation:
https://www.analog.com/en/products/adin1110.html
Signed-off-by: Antoniu Miclaus <antoniu.miclaus@analog.com>
The existing i2c sda/slc pinctrl nodes serve as an input and output
for the USIC. This limits the number of pins that can be used for i2c
since the pin must be internally connected to both DOUT0 and DX0 signals
on the USIC (for the sda signal for example).
It is also possible to use separate pins to DOUT0 and DX0, but connect
the pins externally. Add these extra pinctrl nodes and document their
use in infineon,xmc4xxx-i2c.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In commit 541482ff20 the pinctrl alternate
function mask was increased to also include open-drain setting.
Revert this change because open-drain can already be set via property
drive-open-drain.
The commit also added separate pinctrl nodes for the i2c controller and
target modes. However, the alternate function settings
is the same in both modes, so keep only one and remove the mode
label.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
To be consistent with other xmc4xxx drivers.
A few other device tree changes:
- Rename clock signal option as it's handled by DX1.
- Remove clock-frequency option as it's already added in
i2c-controller.yaml, and interrupts is already defined as array
in base.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Since the pwm_nrf_sw driver can now be used on all nRF SoCs, add its
corresponding DT node in the common file included by all those SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Without status line, watchdog is enabled by default. The desired
behaviour is to have it disabled and enable only when watchdog
is used, with overlay files. The same way how it is done for
samples/drivers/watchdog and tests/drivers/watchdog/wdt_basic_api.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Rework the devicetree definition for smsc91x to put the mdio and
ethernet device at the same level, and make the phy a child of the mdio
node.
This allows matching up the device initialization sequence with the
devicetree hierarchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a property that allows explicit selection of the differential
input mode for ADC channels in DTS. This is useful for controllers
that do not have configurable inputs, so the zephyr,negative-input
property that implicitly selects the differential mode is not
specified for them.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rename the STM32H7 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32H7 FDCAN
clock and pinctrl macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32 FDCAN
pinctrl macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 bxCAN driver DTS compatible, Kconfig symbol, and
implementation file to match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
adds dts support for general purpose timer to accomodate timer driver
bringup on aglex and agilex5
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.
This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.
In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Allow properties 'regulator-min-microvolt' and 'regulator-max-microvolt'
for fixed regulators: Note: they should be equal.
Add simple functions for getting list of allowed and count of voltages.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Possible situation is that in some driver, devices can be controlled in
different ways: in some, we can only turn the power on or off, in others,
we can only control the voltage, and in some, we can control power supply
or voltage level. There may also be devices where there is no control
over power supply at all. A clear example of this can be eMMC devices
where the voltage is usually fixed and they are always powered on.
However, we would like to have a common code for controlling all the
mentioned types of devices, at least the driver shouldn't worry about the
implementation details of voltage regulators. Therefore, there may exist
empty regulators - regulators that only contain information about the
supported voltage, and we cannot change anything in them. The device tree
node description for such a regulator is only necessary for compatibility
with other regulators. Hence, we need to add the possibility of the
existence of such a dummy fixed-regulator.
In this commit, support for a fixed dummy regulator without the ability
for any control has been added. Note that such support also exists in the
Linux kernel. In other words, the logic of the fixed regulator has been
aligned with the logic of the fixed regulator inside the Linux kernel.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Although there are no in-tree users, we will deprecate the
`facebook` vendor prefix and add `meta`.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Add watchdog support to ELkhart Lake board basically copying
configuration from Raptor Lake.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Since we do not have any in-tree users, we will skip the
deprecation process for `facebook` and add `meta`.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Disabled uart0 and uart1 by default in alder_lake.dtsi and enable only
for intel_adl_crb board.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
This commit adds input clock selection to the RTC driver. This
is required to allow for the real hardware to operate. The
QEMU emulated hardware ignores the input clock settings.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
INPUT_REL_WHEEL is the code that normally refer to scroller wheel, which
probably makes a bit more sense in this context, use that instead of
INPUT_REL_Y.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Enable CANFD for rt11xx by including nxp,flexcan-fd
compatibility for all CANFD capable CAN with associated
properties.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This commit instantiates the counter peripheral.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Change the gpio-keys and zephyr,gpio-keys so that they can both be used
with the input subsystem driver. Make the zephyr,code property optional
so that existing out of tree board can still use this node with their
custom code, but change everything else so that an existin gpio-keys
node can be used with the input driver as long as the codes are defined.
From the application perspective, this means that the application can
still use the GPIOs directly, the input specific driver only gets
enabled if CONFIG_INPUT is enabled and the driver can always be turned
off manually.
This makes gpio-keys behave the same as gpio-leds with CONFIG_LED.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The controller and the driver support two hardware configurations:
- one three-channel (RGB) LED
- or three single-channel LEDs
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
Some boards may have connected the enable pin of the chipset to a GPIO.
On these boards, it is necessary to configure and set this GPIO before
using the chipset, otherwise the I2C circuitry is disabled.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add support for LP5009, LP5012, LP5018 and LP5024 devices which only
differ by the number of LEDs they can control.
Also, update application sample to run on all these new supported
devices.
Based on initial work from:
- Marek Janus <marek.janus@grinn-global.com>
- Rico Ganahl <rico.ganahl@bytesatwork.ch>
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
UART controllers present on Ambiq SoCs implement a PL011 compatible
interface, with some minor differences that require certain quirks.
To support them a dedicated compatible is needed.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
Adds a new I2C shim driver for Intel SoCs. Builds upon the SEDI bare
metal I2C driver in the hal-intel module.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Sometimes, channel C may write wrong register to the target device.
This issue occurs when FIFO2 is enabled on channel C. The problem
arises because FIFO2 is shared between channel B and channel C.
FIFO2 will be disabled when data access is completed, at which point
FIFO2 is set to the default configuration for channel B.
The byte counter of FIFO2 may be affected by channel B. There is a
chance that channel C may encounter wrong register being written due
to the FIFO2 byte counter wrong write after channel B's write operation.
The current workaround is that channel C cannot use FIFO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The system still takes both prefixed and unprefixed dt-bindings files,
but let's use zephyr/ prefixed in the examples and documentation.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
On ACE a seperate, soc specific, interrupt mask needs to be enabled
to unmask the interrupt. Do so for GPDMA.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
SPI driver is current working for common SPI devices.
However, addressable LED like WS2812 requires MOSI line to be
default LOW during initialization. This PR adds such option.
This has no effect on common SPI operation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Modify the NPCX driver erase method to allow 0x1000 byte size erases
along with 0x10000 byte size erases based on input parameters
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add initial support for NXP S32 GMAC/EMAC:
- it's a copy-implementation with DMA data buffers and buffer
descriptors in non-cached memory (buf len and ring size configurable)
- PHY interface selection only implemented for S32K3 devices as it is
SoC-specific
- no PHY driver integration, it works as a fixed link with speed/duplex
configured through devicetree
- supports multicast hash filtering, promiscuous mode, MAC loopback
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Change the eth-phy definition so that the phy is pointed by a phandle
rather than a child node, make the phy device a child of mdio. This
makes more sense from a devicetree hirearchy where the phandles have to
be initialized before the device itself, allows keeping the priorities
in check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add option to use (by defining the `wake-gpios` devicetree properties)
an additional signal line between SPI master and SPI slave that allows
the latter to stay in low-power state and wake up only when a transfer
is to occur.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Introduce support for NXP FS26 SBC watchdog. Both Challenger and
Simple watchdog types are supported. Only watchdog functionalities of
the device are supported and any other monitoring feature is either not
supported or disabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
It's used to pass right device index to hal_intel module.
DT_INST_FOREACH_STATUS_OKAY() does not guarantee the node ordering.
Signed-off-by: Dong D Wang <dong.d.wang@intel.com>
Rename the phy-dev property with phy-handle to match the Linux
ethernet-controller binding and move it up to ethernet.yaml so that it
can be used by other drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adds a new serial shim driver for Intel SoCs. Builds upon the SEDI bare
metal UART driver in the hal-intel module.
Signed-off-by: Nachiketa Kumar <nachiketa.kumar@intel.com>
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Add support ADC SAR for NXP S32. ADC SAR diver
support 3 group channels (precision, standard
and external), run normal trigger in oneshot
conversion mode with 2 callbacks normal end
of conversion and normal end chain callbacks.
An instance only run on 1 group channel and
1 kind of callback at the same time.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Enable SPI SDHC driver to manage card power via pwr-gpios property.
Control for this property was previously partially implemented. When
this property is present, the SPI SDHC driver will use it to control
power to the SD card.
Power is toggled during SD init, so this power control can make SD init
more reliable as the power toggle will insure the SD card state is reset.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add driver for HX8394 TFT LCD controller. This controller is driven via
MIPI DSI, and is configured for a 720x1280 display
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
So far pin identifiers were named after CN7 and CN10 connector names on
Nucleo-64 boards. In case of Nucleo-144 there are ST Morpho connectors on
both sides, but bigger (up to 72 instead of 38 pins on each side). First 38
pins out of 72 on each side usually map to the same pins (e.g. PA5 being
13th pin on right ST Morpho connector). This means that single ST Morpho
connector definition will suffice.
Leaving CN7 and CN10 (name of pin headers on Nucleo-64 boards) is confusing
in context of Nucleo-144 boards, since corresponding pin headers are named
CN11 and CN12.
Rename:
* s/ST_MORPHO_CN7_/ST_MORPHO_L_/
* s/ST_MORPHO_CN10_/ST_MORPHO_R_/
so that pin identifiers make more sense in context of Nucleo-144 boards.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Devicetree specification v0.4, Section 2.3.1:
"The compatible string should consist only of lowercase letters, digits
and dashes, and should start with a letter."
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This state is never used in practice, even if handled by the PM
subsystem hooks. Shutdown-like states are always invoked manually, so
they don't need to be described in DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The `cpu-power-states` property needs to be defined at SoC dts files,
since it's a property of the SoC, not board.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add mailbox and interrupt-controller nodes used for
inter-process communication.
Add also the dt binding for the interrupt-controller.
For now, this is used just to fix some compile errors,
since the mailbox requires an interrupt-controller.
For DSP, we have a direct interrupt line to the core.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Added a driver for the DFRobot A01NYUB distance sensor. This sensor
sends its readings via UART at 9600 baud. This driver uses interrupts
to read the data from the sensor.
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
Add support for flash NOR memory devices on a NXP S32 QSPI bus. The
driver uses a fixed LUT configuration assuming a default standard page
size and erase types, and allows to select between multiple read/program
instructions/modes. It is also possible to read the flash device
characteristics from the device at run-time as long as the memory is
JESD216 compatible, providing more flexibility.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The NXP S32 QSPI controller acts as an interface to up to two serial
flash memory devices, each with up to eight bidirectional data lines,
depending on the platform. It is based on a LUT enginee to interface
through commands with different memory types including flash NOR and
Hyperram.
This patch adds support for the QSPI in S32K344 which supports a single
memory device (side A) with up to four bidirectional data lines and SDR
only. Nevertheless, the memory controller is implemented flexible enough
to be extended to support more feature-rich QSPI blocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit aligns TWIM shim to utilize memory-region property.
The memory-region is not required property that enables user
to specify placement of dma buffers in memory region.
It is done by assigning to memory-region property,
phandle to node with zephyr,memory-region and mimo-sram compatible.
When memory-region property is not specified for given
instance, buffer is placed in default RAM region with other data.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
Each PSCI interface versions have different DT compatible strings
like arm,psci-0.2, arm,psci-1.1 and so on. However, the same driver
can be used for all the versions by adding #define DT_COMPAT for
required version and #undef DT_COMPAT for default version.
Add support for PSCI cold reset, warm reset and cpu-on function IDs.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
If the optional hardware reset line is available, this change
will use that reset line to assert the uart module and bring
it out of reset state to use.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which controls individual module
reset signals. During each system driver initialization, these
reset signals will be used to bring module out of reset state.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the
first version of device tree which enable four cores SMP and basic
drivers that needed by 'hello_world' and 'cli' applications.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
This is Intel's proprietary IP which supply the clock for all the
system peripherals. Clock manager is initialized only one time
during boot up by FSBL (ATF BL2) based on external user settings.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the followint criteria:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Previously the driver was retrofitted to the kscan api, handling it as a
input device with one row and three columns. With the move to the input
subsystem each input can have its proper input code instead.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
The 'zephyr,memory-region-mpu' property was addede gqas a
convenient way to create and configure MPU regions using information
coming from DT. It has been used a lot since it was introduced so I
guess we can consider it a Zephyr success story ™ .
Unfortunately it has been proved to be a bit limited and with some
important limitations:
1. It was introduced as a property of the compatible
zephyr,memory-region that is used to create linker regions and
sections from DT data. This means that we can actually create MPU
regions only for DT-defined regions and sections.
2. The naming is unfortunate because it is implying that it is used only
for MPU.
3. It is misplaced being in include/zephyr/linker/devicetree_regions.h
and still it has nothing to do with the linker at all.
4. It is exporting a function called LINKER_DT_REGION_MPU that again has
nothing to do with the linker.
Point (1) is also particularly limiting because it is preventing us to
characterize memory regions that are not generated using the
'zephyr,memory-region' compatible, like generic mmio-sram regions.
While we fix all the issues, we also want to extend a bit the range of
usefulness of this property. We are renaming it 'zephyr,memory-attr' and
it is now carrying information about the type of memory the property is
attached to (cacheable, non-cacheable, IO, eXecutable, etc...). The user
can use this property and the DT API coming with it to act on the memory
node it is accompanied by.
We are still providing the DT_MEMORY_ATTR_APPLY() macro that can be used
to create the MPU regions as before, but we are adding also a
DT_MEMORY_ATTR_FOREACH_NODE() macro that can be used to cycle through
the memory nodes and act on those.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
CPU idle states are not board specific. This patch moves Nuvoton idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves NXP idle states
to the core SoC dts files. Board can always tweak some state parameters
(if needed), but the definition belongs to core SoC dts files, same as
e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves Microchip MEC
idle states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves TI idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves STM32 idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves ESP32 idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the driver to support low power mode.
Introduced "enable-low-power" flag in device tree to
control(on/off) low power mode.
If flag added in DTS, during sleep BBLED will switch off the LEDs.
Otherwise BBLED will continue the configured blinking pattern on LEDs.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add support for resetting controller at boot, and update FT5336
documentation to indicate that the FT3267 IC is also supported by this
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for RM67162 MIPI display controller. This controller
is configured to run in MIPI command/DBI mode, driving a 400x392 OLED
display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Only setup DPI input from LCDIF if MODE_VIDEO is set, as this
is the the only case where input from the LCDIF would be required to
drive the display. Do not populate the dpi_config structure unless a
reference the the NXP LCDIF device is provided, since this is the output
device providing DPI data.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fixup support for DCS_LONG_WRITE command in DSI MCUX 2L driver. Since long
DCS commands may benefit from nonblocking I/O, add support for non blocking
transfers to the DSI driver.
This commit also corrects the interrupt number for the RT595, which uses
the DSI_MCUX_2L IP block.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Make DPI mode an optional configuration for the DSI MCUX 2L driver.
DPI mode will only be enabled when the MIPI is attached in video mode,
since this is when DPI formatted packets are expected.
This will enable the DSI driver to also support DBI/command mode, for
displays that use this format.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
- Add overlay for the esp32s2_saola board to die_temp_polling sample.
- Add aliases for the die_temp_polling sample to esp32s2 dtsi.
Signed-off-by: Hiroki Tada <tada.hiroki@fujitsu.com>
Enabled support for is31fl3733 driver. This driver supports
the full LED API, and enables the following features of the is31fl3733:
- individual LED dimming
- individual LED enable/disable
- bulk writes of LED enabled and dimming states
- global LED current limit
- blanking (via custom API)
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Add Nuvoton numaker series flash memory controller(FMC) with erase,
read & write features of soc-flash. Also update Nuvoton manifest
to include zephyrproject-rtos/hal_nuvoton#6.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This driver is built on top of the IVSHMEM doorbell
notification mechanism providing an unified way
to generate inter VM interrupts.
Signed-off-by: Felipe Neves <felipe.neves@linaro.org>
Add the new RCC bindings to the dtsi files.
STM32F373 uses the RCC F1 bindings because the ADC prescaler is the same
on the two series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add two new bindings for STM32F1x and F3x RCC to add the ADC prescaler
specific to these series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
AXP192 is a small and simple power management IC featuring different
LDOs, DCDCs, AINs and also GPIOs. It also offers functionaltiy for
battery management.
This change includes the basic regulator driver functionaltiy for
LDO2-3 and DCDC1-3 as well as the mfd driver layer. Further drivers
for GPIO and ADC will follow.
Drivers have been developed and tested on M5StackCore2, an ESP32-based
board. Support for M5StackCore2 is still in progress.
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
GT911 IC uses the INT pin to select the correct I2C address during
reset. However, some boards may not route this pin (or may only support
receiving inputs on it). This results in the I2C address selected by the
GT911 IC being arbitrary based on the state of the (floating) INT pin.
To resolve this, introduce an `alt-addr` property for this device. When
set, the INT pin will not be pulled low. Instead, the I2C address will be
probed at runtime, starting with the devicetree address and falling back to
`alt-addr`.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patchset is doing three things:
1. It is fixing the bogus algorithm to find the optimal number of
descriptors for a given memory size.
2. It is changing values for VDEV_STATUS_SIZE and
IPC_SERVICE_STATIC_VRINGS_ALIGNMENT to better align to a usual cache
line size.
3. RX/TX VRINGs are now correctly aligned to MEM_ALIGNMENT (and cache
line alignment).
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This patch adds a description section for the pwms property of the PWM
LED child node. This intends to explain how the period field is used by
the led_pwm driver and to help with its configuration.
Reported-by: Scott Worley <scott.worley@microchip.com>
Signed-off-by: Simon Guinot <simon.guinot@seagate.com>
Convert the GT911 driver to the input subsystem, fix the existing boards
to work in the default config.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Aligns the filename of TI's CC13/26xx system timer peripheral devicetree
binding to its compatible string.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
This adds support for the bosch bmi085 and bmi088. This also includes
support for data sync mode.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
This patch adds support for PWM blink which is found in intel's
PCH hardwares.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Current erroneous usages of dma-channels prop by lpc-dma nodes:
* dma-channels devicetree property should describe the number of
channels supported by the dma controller, not the number of channels
in use.
* LPC55SXX and RTXXX SOCs should be setting dma channels prop at SOC
level, not board level, since it is an SOC property, not a board
property.
* lpc55s28 has 23 channels for dma0, not 20.
* lpc55s28 has 10 channels for dma1, not 0.
* lpc55s69 has 23 channels for dma0, not 20.
* rt5xx has 37 channels for dma1, not 0.
* rt6xx has 33 channels for dma0, not 20.
* rt6xx has 33 channels for dma1, not 0.
Fix all of these issues
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Set the DMA number of otrigs DT property at the SOC level instead of the
board DTS because it is an SOC property and does not change on different
boards.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add basic device tree description fro stm32wba soc series.
This includes Flash/RAM clocks and clock control nodes
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Adding support for the adafruit can picowbell shield for the
raspberry pi picoi. Also added nodelable for spi0 called 'pico_spi'
as well as an GPIO nexus node 'pico_header'
Signed-off-by: Joseph Yates <joeyatessecond@gmail.com>
This change introduces the "_rtc_timer" suffix for the system tick timer
driver "compatible" property and aligns naming conventions with the
actual CC13/26xx SoC series product policy.
This frees up the "_rtc" namespace to introduce additional APIs based on
the same peripheral in the future (not part of this PR):
rtc: rtc@... {
compatible = "ti,cc13xx-cc26xx-rtc";
...
timer {
compatible = "ti,cc13xx-cc26xx-rtc-timer";
...
};
counter {
compatible = "ti,cc13xx-cc26xx-rtc-counter";
...
};
pps {
compatible = "ti,cc13xx-cc26xx-rtc-pps";
...
};
};
Or alternatively an MFD pattern with similar requirements.
Fixing the namespacing now makes sense standalone as it reduces the
chance of custom drivers being broken in the future.
Redundant extension of the mandatory system clock devicetree node is
replaced with a single `status = "okay"` which seems to be the more
sensible default to avoid user error when defining custom boards.
Knowledgeable users can still override this if really needed.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add SHA256 accelerator support for it8xxx2 series.
This driver passes the following test:
tests/crypto/crypto_hash/
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Changes rshunt-milliohms to rshunt-micro-ohms allowing for current
sensing of greater than 16.4A (1mOhm resistor). This is commonly
set to 100 uOhm for VMU/FMU boards/applications.
Co-authored-by: James Goppert <james.goppert@gmail.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
The different references manuals of the STM32H7 family (RM099, RM0433,
RM0445 and RM0468) states that SDMMC2RTS and STMMC2EN are on bit 9 of
respectively RCC_AHB2RSTR and RCC_AHB2ENR (not on bit 8). Fixes the stm32h7
dts accordingly.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.
Use the board's debug connector (P6 / LPUART2) as default console.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
SIUL2 may require multiple interrupt handlers instead of a single one as
currently supported for S32Z/E. This is needed to enable support on
S32K3.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Support pin control for NXP S32K3 devices and enable it by default on
mr_canhubk3 board configuration.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The clock controller is a singleton controller for all the system-level
clocks (XOSC, PLL, CGM, etc) to provide run-time information to the
peripheral device drivers about the module's clocks.
Clock configuration is not yet supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add a small delay between reading the transport header and reading the
HCI data. Failing to do so on a nRF9160<->nRF52832 link was reliably
resulting in the nRF9160 trying to read data before the nRF52832 had
set up the SPI transaction, resulting in the host reading a buffer full
of 0x00 and having to run the entire read result again.
Transceiving a 10 byte packet takes at least 31uS, while 100 byte
packets are around 150uS (duration of `spi_transceive` call). Waiting
1 tick to eliminate the need for most retransmissions is a valid
tradeoff.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Add an option that signifies that the ESP modem may be reset at the same
time as the SoC by an external source. When this is the case, we first
wait for an unsolicited "ready" message from the modem, before
attempting to reset the device. This prevents two initialisation
sequences attempting to run at the same time.
We still want to wait for the complete initialisation sequence to
complete before returning in this case.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
This adds support for the TIMER1-4 counter.
Each counter has 24bits and can run on LP_CLK (15-32KHz)
or DIVN clock (32MHz) with prescaler 1-32.
Each counter can have one alarm set.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
The display controller supports software reset and the driver already
implements it. Therefore it's not necessary to require a reset gpio in
device tree.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Remove `clocks` property for fixed-clock binding.
A fixed-clock should not have an input clock, since by
definition it's an always on fixed-rate clock.
Signed-off-by: Moritz Fischer <moritzf@google.com>
This adds a driver for Texas Instruments Cost-Optimized, Ultra-Small,
12-Bit, System-Monitoring ADCs. Currently only TLA2021 is supported,
TLA2022 and TLA2024 may follow based on this driver.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Convert the XPT2046 driver to the input subsystem, change the api,
remove the callback and enable logic.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Usage of 64-bit address constants from devicetree without a
UINT64_C wrapping macro results in the following warning and the
cut-off of the address value:
"warning: integer constant is so large that it is unsigned"
This change extends devicetree API adding few wrappers over the
address constant getters which add ULL size suffix to an
address integer literal when the appearance of 64-bit address
values is possible
Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
Add a GPIO based quadrature decoder driver that reports relative axes
movements using the input subsystem.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Adds properties to configure OCTOSPI IO
Manager data lines. That allows to use
any `IOLowPort` and `IOHightPort`.
Note: OSPIM requires additional clock to be enabled.
Please refer to Reference Manual.
Extra clock can be enabled in devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Add Nuvoton numaker series UART support, including interrupt-driven,
also apply pinctrl and clock-control.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add support for communication with serial ports on native POSIX platform
via UART driver API. Serial port driver supports polling API,
configuration of the serial ports used via devicetree and command line
options, and runtime configuration with `uart_configure`.
Multiple instances of the driver are supported.
Example use and configuration is also demonstrated in the
`samples/drivers/uart/native_tty` sample.
Closes: #56586
Signed-off-by: Marko Sagadin <marko.sagadin42@gmail.com>
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
The IS31FL3216A is a fun light LED controller. The LED current of each
channel can be set in 256 steps by adjusting the PWM duty cycle through
an I2C interface.
Signed-off-by: Guy Morand <guy.morand@bytesatwork.ch>
Add a minimal driver for the ti lp5569 led controller. The driver supports
multiple instances. Commands on|off|set_brightness are supported.
Signed-off-by: Jonas Remmert <j.remmert@phytec.de>
Currently, only the presence of a GIC is reflected in the device tree,
and its version must be set separately in each SoC's Kconfig.
This patch adds separate bindings for each GIC version whose presence
in the device tree automatically enables the corresponding Kconfig symbol.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
When the GIC driver was originally introduced, it was only used on
Cortex-R SoCs. However, this is not the case anymore. Update the
description to reflect that this driver is not specific to Cortex-R.
Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
Add driver for TCN75A temperature sensor. The following features are
supported:
- TCN75A oneshot mode, which allows single shot conversions with lower
power consumtion
- Resolution selection, up to 12 bit resolution (9 bit default)
- Triggering based on temperatue thresholds. If the TCN75A exits a set
threshold range, the application can be notified via a callback.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This PR adds a custom driver for the ADS1112 ADCs. Unlike ADS1113/4/5
family served by the ADS1x1x driver, the ADS1112 does not use an address
pointer to address config registers. Instead, there is only one writable
register and all i2c writes will set it. The registers resemble the
ADS1119 device, but config bitmap is different, include a distinct data
rate table, gain table, and input multiplexing table. There is also not a
status register to be monitored with the ADS1112, as it uses config bit 7
for the same purpose instead of a separate register.
The driver was tested on hardware using the ADC shell interface. Manual
probing validated the voltages for the MUX_SINGLE configs at datarate 15
in CM_SINGLE. Higher gains were not tested and CM_CONTINUOUS is not
supported in this initial implementation.
The new driver has also been added to the existing ADC test using adc_emul
for completeness.
Origin: original
License: Apache 2.0
Purpose: Adding support for ADS1112 ADCs
Signed-off-by: Jordan Montgomery <jordan.montgomery@getcruise.com>
Move dt files related to SoC family and series to npcx folder. It only
leaves SoC dt file in `dts/arm/nuvoton folder` in case of confusion with
the other Nuvoton SoCs.
The dt files path will be:
dts/arm/nuvoton
|--npcx
| |--npcx7
| | |--npcx7-miwus-wui-map.dtsi
| | |--npcx7-alts-map.dtsi
| | |--.....
| +--npcx9
| | |--npcx9-miwus-wui-map.dtsi
| | |--npcx9-alts-map.dtsi
| | +--.....
| |--npcx-miwus-wui-map.dtsi
| |--npcx-alts-map.dtsi
| |--npcx.dtsi
| |--npcx7.dtsi
| |--npcx9.dtsi
|--npcx7m6fb.dtsi
|--npcx7m6fc.dtsi
|--npcx9m8f.dtsi
+--npcx9m3f.dtsi
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Move the two UART nodes so that they are under "soc" rather than "espi",
leave only xec-espi-host-dev nodes there.
The UART device can be used indepdently by the driver uart_mchp_xec.c
and it's normally initialized before before the espi one.
Moving the device node up a level so this does not trigger a false
positive on the build time priority checking.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Restructure the Bosch M_CAN driver backend to use per-instance Message RAM
configuration.
This removes the need for a common, artificial "can" devicetree node for
SoCs with multiple Bosch M_CAN-based CAN controllers and allows for
per-instance configuration of the number of e.g. standard (11-bit) and
extended (29-bit) filter elements.
As part of the restructure, software handling of CAN filter flags was moved
from per-flags bitfields to per-filter bitfields, solving an issue when
using more than 32 standard (11-bit) filter elements or more than 16
extended (29-bit) filter elements.
Fixes: #42030, #53417
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Switch the Bosch M_CAN devicetree binding to use a bosch,mram-cfg property
for specifying the memory layout of the Bosch M_CAN Message RAM. This is
identical to the Linux kernel devicetree binding for Bosch M_CAN IP core
based CAN controllers.
This introduces an offset cell which can be used for controllers with
shared Message RAM between Bosch M_CAN instances.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The BG95 pin configuration does not internally ever use the reset pin.
Because of this, there is no need to make reset pin mandatory.
Commit removes reset pin dependency [e.g. in case of BG95].
Signed-off-by: Andrei Hutanu <andrei.hutanu.i@gmail.com>
Add a property to the ADC channels which allows the configuration
of the current source pin.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Added Input/Output trigger mux address's as properties
that can be passed into the DMA driver. This is intended
to send INPUTMUX signals into the DMA.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Ports the Jinghua Display JHD1313 LCD (with RGB backlight) driver
to use the new auxdisplay driver interface. This driver is used on
the seeed grove LCD RGB display, and replaces it.
Signed-off-by: Jamie McCrae <spam@helper3000.net>
Removed few VIF properties which are being hardcoded
Updated the script to parse source VIF XML and add information to
the output
Added optional Kconfig option to configure custom source VIF XML path
Cleaned up the code
Signed-off-by: Madhurima Paruchuri <mparuchuri@google.com>
Added intel LPSS DMA interface using dw common to support
usage of internal DMA in LPSS UART, SPI and I2C for
transfer and receive operations.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Adds PHY driver. Works via MDIO API and
exposed ADIN2111 MDIO Clause 45
functions.
Link status detection is triggered by
ADIN2111 driver within offloaded IRQ
handler.
Supports:
- LED0, LED1 enable/disable
- Fatal HW error detection
- AN 2.4V tx mode enable/disable
The initialization order is important.
PHY 2 must be initialized after PHY1.
Therefore, it shall be defined after the 1st one
in the devicetree.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds MDIO driver. Works via exposed
ADIN2111 functions.
It is possible to access Clause 45 and 22 registers.
Due to MDIO API limitation Clause 45 access
is done using driver specific MDIO functions.
Provides API and functions for PHY driver.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds initial ADIN2111 2-Port 10BASE-T1L (SPE)
switch support. Works over SPI.
The driver creates 2 interfaces, 1 per port (PHY).
Configures multicast and broadcast filters.
The same unicast is applied to both ports.
Supports:
- Link state detection
- CRC enable/disable
- Ports config set
- Ports ETH stats
Provides functions for MDIO driver.
Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>
Adds the pwrmgr devicetree node. This is a simple binding that holds
only the address of the registers for now.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The OpenTitan power manager is responsible for changing the OpenTitan's
operation to and from low power state. This patch adds a simple binding
for the power manager's config registers.
This is part of the OpenTitan watchdog patch series. The power manager
HWIP block needs to be configured to enable the watchdog reset
functionality in the OpenTitan Verilator simulation.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
Adds the AON Timer device in the OpenTitan Earlgrey device tree.
Adds overlay files to enable the watchdog and set the alias to
`watchdog0`.
Adds the AON timer (watchdog part) to the supported features section
of the OpenTitan documentation.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The OpenTitan AON Timer is a hardware device that has two features:
the wakeup timer and watchdog timer. This commit series implements the
watchdog feature.
The spec can be found here:
https://opentitan.org/book/hw/ip/aon_timer/index.html
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
This selects default flash controller in device tree.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
This adds support for the USB interface for the
Renesas Smartbond DA1469x device family.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
RT1040 removes LPSPI3, and refers to the peripheral called LPSPI4 on
other RT devices as LPSPI3. Remove the default LPSPI3 peripheral and add
an `lpspi3` alias to LPSPI4.
Fixes#57942
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add missing USB-OTG control nodes. Like other STM32-platforms it's
disabled by default and uses the internal 48 MHz clock by default.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Add an API-less MFD driver for nPM6001. In this case, the MFD device
driver doesn't expose any API as plain I2C API is used within other
device drivers (regulator, GPIO, watchdog). This driver just initializes
some device properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update the default Flash and SRAM size to 1024kb and 288kb, Update the
mpn file overrides accordingly
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
cpu@0 node is not supported on some mpn's so it should be deleted from
the mpn files and not the package files.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
- Remove the spi node from an older commit since its replaced with the
SCB node now
- GPIO nodes should have been part of pinctrl
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
include the infineon,cat1-scb.yaml for I2c and UART bindings to convey
that they are using SCB (Serial Control Block)
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Add a new regulator driver for Analog Devices ADP5360. While it is a MFD
device, only support for BUCK/BUCKBOOST regulators is added in this
patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add new vref node to the DTS definitions of supported SoCs.
Extend DTS ADC channel properties where missing.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Add VREF+ sensor driver and DT node definition.
This driver allows determining the actual voltage applied to an SoC's
VREF+ pin, by comparing the VREFINT internal bandgap voltage reference
with its factory calibration data.
In packages where VREF+ is bonded to VDDA, this permits direct measurement
of VDDA voltage.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Introduce DesignWare ARC Data Fusion IP Subsystem(DFSS) SPI
driver for ARC boards, i.e. EMSDP, which uses DW SPI to controll
SPI-Flash and DFSS SPI to connect external devices. Both drivers
share most source code, but DFSS uses ARC auxiliary registers.
Move FIFO depth setting to device tree.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Add support board Pandora_STM32L475;
Drives that have been verified at present:
- GPIO
- PWM
- QSPI_FLASH_W25Q128
Signed-off-by: Tianshuang Ke <qinyun575@gmail.com>
Renesas Renesas SmartBond(tm) have two ADC blocks:
GPADC and SDADC.
This change adds drivers for both.
Each ADC supports only one channel setup, drivers allow
to have multiply channels in sequence. Switching
between ADC sources in done in software.
GPADC has 10 bit resolution (accuracy can be increase
with oversampling). Values up to 3.6V can be measured
on selected pins. V30 and VBAT1 can also be measured.
SDADC has 14 bit resolution and can take measurements
from 8 pins (single of differential) and VBAT.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Since Merge zephyrproject-rtos#57360, user can use ch<x> and ch<x>N
simultaneously, which is beneficial for STM32 users
working in motor control area.
Signed-off-by: Savent Gate <savent_gate@outlook.com>
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
- The boards\arm\cy8cproto_063_ble board now has ADC enabled
- This includes overlay files for the test app and sample app
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This driver implement basic functions of ili9342c controller
which comes mostly with IPS displays.
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
The LSM6DSV16X is a system-in-package featuring a 3-axis digital
accelerometer and a 3-axis digital gyroscope for industrial and IoT
solutions. The LSM6DSV16X embeds advanced dedicated features such as
a finite state machine (FSM) for configurable motion tracking and a
machine learning core (MLC) for context awareness.
https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html
This driver is based on stmemsc HAL i/f v2.02
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Convert the NPCX keyboard scan driver to the input subsystem and add the
input to kscan compatibility driver to maintain functionality with the
current API.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add a USB device controller driver skeleton to use as a starting point
for implementing a specific driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Example configuration uses 'A' and 'X' key codes for longpress events.
Described behavior shows correct key codes (30 and 45), however comments
near those key codes were invalid for 'X' key. Fix that.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Added i-cache-line-size and d-cache-line-size values
to device tree for ace20_lnl platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Allows Ethernet communication between "cells"
in the Jailhouse hypervisor.
The vring queue deviates from a standard virtqueue
so is implemented separately.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This allows finding the correct PCIe device when multiple devices
have the same vendor-id/device-id but differ in the class-rev register
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add RT1040 SOC devicetree. This devicetree removes IP blocks absent on
the RT1040, and configures clock dividers correctly for the RT1040's
clock tree
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix PINT base address for LPC51xxx and 54xxx. These addresses were
incorrectly copied from the LPC55S69, which utilizes trustzone. Add the
relevant base address offset to the addresses.
Fixes#57334
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the same wording in description for both I2C and SPI variants to
improve consistency.
Create st,lsm6dsl-common.yaml to include common binding properties from I2C
and SPI variants.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add common LCD interface binding. This binding captures the
following properties, which are shared between multiple LCD interface
IP blocks:
- VSYNC/HSYNC pulse width
- Vertical/Horizontal front and back porch
- HSYNC,VSYNC,data enable, and pixel clock polarity flags
- pixel clock frequency
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Let the Bosch M_CAN front-end drivers supply their own register read/write
functions.
This is preparation for handling non-standard Bosch M_CAN register layouts
directly in the front-end and for accessing Bosch M_CAN IP cores over
peripheral busses.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Currently, the usb_dc_dw driver is not enabled for any platform.
Allow to build the driver for cyclonev_socdk. Subsequent patches
will allow the driver to be used on additional platforms.
Enable USB device controller and use use new snps,dwc2 compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Although snps,designware-usb bindings already exist, this one is
prolematic. Compatible is too general and does not reflect
the actual controller IP. It has Zephyr-specific properties,
but has no zephyr prefix. It forces properties that are not
necessary for this controller. We start here with new bare minimum
properties for DesignWare OTG USB 2.0 controller.
The STM32F4 SoC family USB controllers, which are also implement
DesignWare OTG USB 2.0 IP, can also be used with existing drivers,
but require certain quirks. To use these we need special compatible.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add GDMA support for esp32s3.
Remove suspend/resume since they are optional and do
the same as start/stop.
Fix possible null pointer derreference.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Declare SCB nodes to be used as UART/SPI/I2C by the boards, Move
common declarations from psoc6_02 to the parent dtsi file
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
Added device tree bindings and implementaion for setting the
spi controllers chip select setup and hold time settings.
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
As recommended in AN4760 the memory region where the QSPI flash can be
memory mapped should be configured to be Strongly ordered memory. This
works around an issue where a speculative read from the CPU may cause
later problems with using the QSPI bus.
This avoids #57466.
Signed-off-by: Ole Morten Haaland <omh@icsys.no>
Most available AT45 flash chips have their first two sectors shorter
than the consecutive ones. Usually, the first sector is marked as 0a
and has its size equal to eight pages (one block) and the second one
(usually 0b) is the complement to the size of a regular sector.
This commits modifies the driver so that erasing of these first two
sectors is performed correctly. This modified behavior is configurable
with a new DT property so that it is still possible to also use legacy
AT45 chips that do not feature such sector split. Such legacy chips
usually also do not support the chip erase and sector erase commands,
so two more DT properties are introduced to cover that.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The LSM6DSO16IS is a system-in-package featuring a 3-axis digital
accelerometer and a 3-axis digital gyroscope for industrial and IoT
solutions. The LSM6DSO16IS embeds a new ST category of processing,
ISPU (intelligent sensor processing unit) to support real-time applications
that rely on sensor data. The ISPU is an ultra-low-power, high-performance
programmable core which can execute signal processing and AI algorithms
in the edge.
https://www.st.com/en/mems-and-sensors/lsm6dso16is.html
This driver is based on stmemsc HAL i/f v2.02
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.
So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.
Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"
For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig
The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
- Added initial version of Infineon CAT1 Flash driver
- Added binding file for infineon,cat1-flash-controller.yaml
- Added overlays for subsys/nvs and drivers/flash_shell
to support cy8cproto_063_ble, cy8cproto_062_4343w boards
- Defined erase-block-size in PSoC6 MPN dtsi.
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This PR adds a driver for the BMI323, which implements
the following features:
* Enable and disable accelerometer and gyroscope respectively
* Set full scale for accelerometer and gyroscope respectively
* Set data rate for accelerometer and gyroscope respectively
* Get samples (x,y,z) from accelerometer and gyroscope respectively
* Get die temperature
* Set trigger to accelerometer data ready, and accelerometer any motion.
The driver implements device and device runtime power management. If
runtime management is used, it is initialized into the suspended state,
which soft-resets the device to achieve the lowest possible power
consumption, otherwise it is resumed when initialized. When resumed,
the bus is initialized, the feature engine is enabled, and INT1 is
initialized.
The driver only implements the SPI bus at this time. The driver is
prepared to be expanded with I2C support in the future.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
Add the `full-duplex` property for the `microchip,enc28j60` node.
Replace ETH_ENC28J60_0_FULL_DUPLEX Kconfig option with this property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Updated the code to to invoke reset using PCR block
z_mchp_xec_pcr_periph_reset() instead of resetting
using I2C Configuration register
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The SERCOM4 is hardwired to PB30/31, PC18/19 internally for the LoRa
radio. Move the pinctrl entries to SoC dts level. The same applies for
samr35.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In general, peripherals should be disabled by default and enabled at
board level when needed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add the ability for the flash simulator to store its contents in a
memory region.
This allows filesystems on the flash simulator to survive a reboot.
And allows subsystems (e.g. coredump) to store their info on ram while
using the (existing) flash partition backend.
Add a example (for nucleo_f411re) that shows how to configure the flash
simulator for hardware (cfg discussion #54166).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
Add support for a generic NTC, `ntc-thermistor-generic`. In this case,
the compensation table is provided via devicetree. Note that DT property
is prefixed with `zephyr,`, because while hardware related, it is linked
to a particular software implementation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Refactor driver to align a bit more with its Linux counterpart, ie,
ntc_thermistor. This driver did quite a few _unconventional_ things,
like using "zephyr," compatibles, a dedicated node for pre-computed
compensation table (referenced by the actual pseudo-device node), etc.
The comparison helper function should likely be simplified as well (to
avoid the need for custom wrapper for bsearch), but this can be done
later.
In this refactor, each thermistor gets a compatible, e.g. "epcos,xxxx".
Compatibles are known by the driver, so are compensation tables. This
simplifies devicetree files. There's no need to bother about
compensation tables in **every** board file if Zephyr supports a certain
NTC model.
In general we should respect Linux bindings, which in the end influence
how drivers are implemented. In this case, this principle resulted in
simplified, easier to use code.
For future developers, this is how support for a new NTC can be added:
1. Add to the end of the driver:
```c
#undef DT_DRV_COMPAT
#define DT_DRV_COMPAT vnd_model
static __unused const struct ntc_compensation comp_vnd_model[] = {
{ x, y },
...,
};
#define DT_INST_FOREACH_STATUS_OKAY_VARGS(NTC_THERMISTOR_DEV_INIT,
DT_DRV_COMPAT, comp_vnd_model)
```
3. In driver's Kconfig make sure it depends on
DT_HAS_$DT_DRV_COMPAT$_ENABLED
Note: $X$ means _value_ of X.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
It looks like the Zephyr thermistor driver bindings were half-copied
from Linux ntc-thermistor. Zephyr principle is to maintain compatibility
with Linux, when possible, so there's no reason to deviate here. Convert
the connection type from a custom enum to a boolean, as Linux does.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
This commit moves the `mpfs-icicle.dtsi` file to a common `microchip`
directory and updates include paths in the `mpfs_icicle` board
devicetree.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Initial sensor driver for NPM1300 PMIC charger.
Includes basic configuration of charger voltage and current.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
All Nucleo boards provide the ST Morpho connector/header, which exposes
all pins of the MCU. It is tipically used in ST shields, so provide a
nexus node to allow creating generic shields.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add Port 14/15 to device tree. These ports can only be configured as input.
Error out in gpio driver if user sets them as output.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
XMC4500 and XMC47/800 MCUs have a different memory layout. The
definitions have been moved to the derivative .dtsi of each MCU.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
This patch introduces support for NXP S32 CANEXCEL (CANXL) peripheral.
CAN protocol supporting:
- CAN classic
- CAN FD
Remote transmission request is not supported as this feature is not
available on NXP S32 CANXL HAL.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\cy8cproto_062_4343w board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Added RTC driver that supports Motorola MC146818B
Enabled RTC set/get time and alarm, alarm callback
and update callback.
Counter and RTC uses same hardware in case of
Motorola MC146818, so they can't be used at a time.
Updated stand-alone mc146818 counter dts instances
to support rtc and counter with same compatible
string of "motorola,mc146818" on ia32, atom,
apollo_lake, elhart_lake and raptor_lake platforms.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This patch adds support for the TI INA3221 current monitor.
This is the datasheet used for reference:
https://www.ti.com/lit/gpn/ina3221
Since this device has three channels, there is a custom attribute to
select which channel is to be used when getting a sample.
Measurements are done on all enabled channels.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Make it possible to use CPOL/CPHA SPI clock modes with the SDHC driver.
Some cards require the clock to switch to low when not active.
Signed-off-by: Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
The current configuration is too long and will block soc from
entering sleep mode. This change was made to get better power
number on EVB.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add a binding for STM32 ADC to specify the resolutions and all associated
register information (through a STM32_ADC_RES macro).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Remove build asserts in favor of DT enums
- Remove power level property since it is unused by SDK
- Correct voltage ref value in DT to correspond to
chip specific values documented in reference manuals
instead of corresponding to SDK enum names.
- Fix SOC devicetrees affected by these changes.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This is a new parameter to divide the LPTIM input clock
by a prescaler, changing the max reachable timeout of the LP timer.
It will divide the LPTIM input clock by 1 (reset value) up to 128.
The lptim configuration register is written with a 3bit value.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
CAVS platforms are not fully integrated with zephyr. Some of the
registers are still programed from SOF side. This feature can be enabled
for those platforms later when integration is fully done.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Implements a UART driver using PIO. Both PIOs are supported.
Only polling API is supported. Only 8N1 mode is supported.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Added a generic driver for RaspberryPi Pico PIO.
This driver is an intermediate driver for abstracting the PIO
device driver from physical pin configuration.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
- To link image loadable by MCUboot, zephyr,code-partition
must be set in the DTS.
- Move partition definitions from SoC DTS to the board DTS.
- Remove scratch partition since MCUboot does not recommend to use it.
- Increase bootloader partitions to 48K to fit recent MCUboot.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The newly added "power-amplifier-output" property for STM32WL SubGHz
radio nodes is mandatory.
Add the property to all affected modules and boards with the
appropriate value for the factory-default hardware configuration.
Add the "rfo-XX-max-power" properties to all affected modules and
boards with the appropriate value for the hardware configuration.
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Add STM32WL-specific sx126x_set_tx_params function based on the
STM32CubeWL modifications to LoRaMac-node.
Add the "power-amplifier-output" DT property to
"st,stm32wl-subghz-radio" for selecting between the RFO_LP and RFO_HP
output configurations provided by the above mentioned function.
Add the "rfo-lp-max-power" and "rfo-hp-max-power" DT properties for
defining the maximum design power of the respective outputs' matching
networks.
closes#48511
Signed-off-by: Kenneth J. Miller <ken@miller.ec>
Adds a retention system which builds on top of retained_mem
drivers to allow partitioning of areas and data integrity with
magic header prefixes and checksum of stored data.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Adds address cells of size 1 and size cells of size 1 to GPREGRET
instances for Nordic devices.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds support for the `drivers.adc` test by adding an overlay
for the `efr32bg22_brd4184a` board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
EFR32MG24 uses the Secure Element's mailbox for entropy gathering
purposes. Reflect that in the device tree structure.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The efr32bg22-pinctrl.dtsi file was shared between bg22 and bg27 files.
It's better to name it efr32bg2x-pinctrl.dtsi.
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
This commit splits device tree into more logical structure. Peripherals
which are on a board are in board dts files, while those which are parts of
a SoC are in SoC dtsi files.
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
The general structure of efr32b27_sltb010a board is shared by more than one
board. This commit intrduces changes to the organization of board files,
which aim to take that into account.
Signed-off-by: Krzysztof Boronski <kboronski@antmicro.com>
This commit makes the alarms-count dts property of the
rtc-device.yaml optional, setting the default to 0.
This simplifies the dts rtc dts node by not requiring
the property to be set to 0 if it is not supported.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
- Add initial version of Infineon CAT1 i2c driver.
- Add initial version of binding file for Infineon
CAT1 I2C driver
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Move the devicetree bindings for Analog-to-Digital Converters (ADCs)
from dts/bindings/iio/adc to dts/bindings/adc as Zephyr does not have
an IIO layer.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
1. Increase sram to 256KB.
A block sram of SCAR0~15 is 4KB.
A block sram of SCAR16~19 is 16KB.
A block sram of SCAR20~23 is 32KB.
2. Removed the register of RVILMCR which has no effect.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
The alternate pins of UART2 have been remapped, and the remapped
alternate pins must be added to the pinctrl map.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add the pinctrl node that has been remapped in the chip of it82xx2.
And modify kscan's pinctrl for the it82xx2.
And swap I2C default pins.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
On iMX.RT devices, the number of GPIO pins exceeds the maximum of
64 that the PINT interrupt controller can support. Therefore, two
interrupt lines are now shared between the GPIO modules.
This patch allows the user to set the interrupt source for a GPIO
peripheral. For most LPC devices, this will always be the PINT. For some
RT devices, the PINT cannot use pins on GPIO modules other than 0 and 1
as input, and thus the INTA and INTB sources should be used.
Since Zephyr does not support sharing these interrupt between all GPIO
controllers, the user must configure a subset of all GPIO controllers to
use the shared module interrupts. An example of how to do so is provided
for the RT595 EVK.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce PINT driver, for NXP pin interrupt and pattern match engine.
The driver currently supports only the pin interrupt feature of the
PINT.
Add DTS entires for the PINT on LPC and RT devices that support this
peripheral, and remove the interrupt defintions that are PINT specific
from the GPIO module on these devices.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch adds HDA to device tree for LNL platforms.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The I2CLCTL_MLCS setting was recently added to MTL
platform. LNL has these registers in separate space, therefore
new field is added to intel,ssp-dai.yaml and appropraite definitions
to LNL device tree.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Repleace usage of shim2 device tree field with hdamlssp.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In current implementation the HDAMLI2SL register is represented by
shim2 field in common SSP device tree file. This could be misleading
since the filed is is different location to I2S IP.
Adding separate device for this register following DMIC case.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A recent change added the stop-bits and data-bits to the base
uart-controller binding, meaning it's no longer required to
be added in the Altera specific binding.
This requires no further changes because its only use is in
uart_altera.c where only the index of the enum is used,
which remains the same between the new implementation and
how it was previously implemented in the altera specific binding.
Relevant commit: 0234f12
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
PR https://github.com/zephyrproject-rtos/zephyr/pull/55129 deleted the
"port-sel" property. Delete this property from remaining Microchip SoC
variants and boards.
Test: west build -b mec172xevb_assy6906 samples/drivers/espi/
Signed-off-by: Keith Short <keithshort@google.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add the header file required for the example to work. Users get the
following error due to unresolved INPUT_BTN_* values otherwise:
parse error: expected number or parenthesized expression
Signed-off-by: Amit Kucheria <amitk@kernel.org>
Signed-off-by: Amit Kucheria <amit@mbedrock.com>
These bindings are removed because they are now handled in the
included base uart-controller.yml.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Add bindings for LTC1665/LTC1660, which is a 8/10-bit
Digital-to-Analog Converter with eight individual channels.
Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
This addition should help users to better understand potential issues
with domain clock configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In ACE 2.0 platform (LNL) dmic got two new shim register ranges.
DMIC driver need to program them to configure the interface.
This patch adds new shims to device tree.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
The temperature sensor of the STM32F0x0 is similar to C0 (with one value
for calibration) but uses a negative coefficient, so we add it to the
bindings, just like in st,stm32-temp.yaml
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add a devicetree binding for the CAN-FD capable variant of the NXP FlexCAN
controller. Add example devicetree snippets to both NXP FlexCAN and NXP
FlexCAN-FD binding documentation to limit confusion.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the nxp,kinetis-flexcan devicetree compatible to nxp,flexcan as it
is not specific to the NXP Kinetis series.
This is preparation for adding a nxp,flexcan-fd binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add new compatible to separate production calibrated sensors
with single and dual calibration temperatures. Also update
stm32_temp driver to support single calibration sensors.
Signed-off-by: Benjamin Björnsson <benjamin.bjornsson@gmail.com>
Adds support for a devicetree property that controls the ClockDiv
value provided to the SDIO during init.
Signed-off-by: Maxmillion McLaughlin <github@maxmclau.com>
No fmc node for the stm32u5 is implemented. This commit
adds a stm32-fmc compatible node to the device tree.
Signed-off-by: Christian Spinnler <christian.spinnler@fau.de>
Without adding a RAM entry for the USB RAM in the MPU,
USB RAM is mapped in the Peripheral Memory region
where unaligned memory accesses will cause a fault error.
Unaligned access errors were uncovered when we switch
to a different Zephyr C library where the memcpy function
implementation has unaligned accesses to the USB RAM.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Zephyr SPI driver model for full-duplex operation assumes
data will be transmitted and received during each clock period.
The QMSPI driver for the XEC family also supported dual and
quad I/O use cases which are inherently half-duplex. To
support dual/quad the driver incorrectly processed spi buffers
as all transmit buffers first then all receive buffers. This
worked if only the SPI driver was used. It did not work with
the Zephyr flash SPI NOR driver which assumes SPI drivers
follow the SPI driver model. This commit implements a QMSPI
driver that follows the Zephyr SPI driver model resulting in
a slightly smaller driver. Dual/quad SPI transactions are
supported if the experimental SPI extended mode Zephyr
configuration flag is enabled. We also remove the QMSPI full duplex
driver added previously to support the flash SPI NOR driver.
Added board to spi loop-back test and spi_flash sample.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add the FDCAN peripheral to the stm32H5 serie.
Two CAN1 & 2 instances for the stm32H56x/H57x devices.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Arm fvp_baser_aemv8r and fvp_base_revc_2xaemv8a boards are using
SMSC91C111 as their ethernet adapters.
Portions of the codes are based on FreeBSD code from its
'src/sys/dev/smc/if_smc.c' and 'src/sys/dev/smc/if_smcreg.h'.
This driver has two parts, one is the ethernet controller driver, which
is MAC layer driver. The other is the MDIO driver, which is the PHY
layer driver. Both of them are in the same source file due to that they
need to share the same reading and writing register functions and
the smsc object.
The mdio driver is needed by the existing 'phy_mii' driver, which is
a driver for the generic MII-compliant PHY.
This driver was developed under the fvp_base_revc_2xaemv8a target and
has been tested on the fvp_baser_aemv8r target.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
move DT_DRV_COMPAT to bmm150.h. so that can be decide which interface
to use.
define struct bmm150_bus_io interface for bmm150_i2c.c and bmm150_spi.c
in bmm150.h.
redefined bus operation interface in bmm150.c, this allow the driver
to decide which interface to use during construction.
Signed-off-by: Weiwei Guo <guoweiwei@syriusrobotics.com>
Convert the SDL driver to use the input subsystem. This is specifically
meant to emulate touchscreen drivers, so it's setup to send triplet of
x, y, touch for touch-on events and just touch off on touch off events.
Renamed the driver to input-sdl-touch since now we can also develop an
sdl driver for simulating key events.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds support for ANY_MOTION and DATA_READY interrupts for
the BMI270. To implement this, a different config blob than the
"max_fifo" blob has to be used.
Signed-off-by: Benjamin Lindqvist <benjamin@eub.se>
This adds the i2c driver for the Renesas SmartBond(tm) MCU family.
It supports blocking transfers and callback transfers.
Currently only supports controller mode.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Under disk bindings. NVMe is a purely PCIe based technology, thus the
relevant includes.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Removed extra #includes at top of files. Missed closing } of
mec172xnlj.dtsi. Lower-cased 'reg' field of PWMs.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This adds a driver for the DS2482-800 1-wire multi channel bus driver.
The driver uses a split architecture in order to share a common lock
among all configured channels of a single IC.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
Add test for the experimental feature GPIO_ENABLE_DISABLE_INTERRUPT,
which covers APIs gpio_pin_interrupt_enable() and
gpio_pin_interrupt_disable().
Signed-off-by: Sung-Chi Li <lschyi@google.com>
Use the LTDC in combination with the DSI HOST makes the pinctrl obsolete.
DSI HOST has dedicated pins.
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
The driver has been recently moved under the input subsystem but the
corresponding driver was left over. Move it from kscan to input.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Give precision to the description of the dma phandle in the
quadspi node.
When a DMAMUX is present and enabled, the channel is the dma one
(not dmamux channel) and the request is given by the DMAMUX.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The emulated RTC device driver is used to emulate a real
RTC device. Note that it is not a replacement for the
native_rtc module, which is used to control simulated time,
get time from the host system, etc.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
This test suite adds tests for the following:
- Setting and getting time
- Validating time is incrementing correctly
- Validating behavior of alarms with callback disabled
- Validating behavior of alarms with callback enabled
- Validating update callback
The test suite uses the devicetree alias rtc to find
the device to test.
Signed-off-by: Bjarki Arge Andreasen <baa@trackunit.com>
Add optional filter value properties. The filter is disabled by default
but can be enabled by setting the filter-sample-period > 0 in the dts
file. A latency is introduced if the filter is enabled. The latency can
be printed by setting sensor log level to debug.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
This commit implements the temperature sensor interface for
the Maxim MAX31865 SPI Temperature Sensor.
Signed-off-by: Fin Maaß <fin.maass@haw-hamburg.de>
Co-authored-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Sort SoC nodes by address to make it easier to find them. As part
of this also move the intel-sha node under SoC where it belongs.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
In ACE 2.0 platform (LNL) ssp got new shim registers.
SSP driver need to program them to configure the interface.
This patch adds new shims to device tree.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
As the power domain nodes don't represent something accessible via
a MMIO register move those under the lps node to address warnings
generated when building the DTS.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds definition of ACE 2.0 Lunar Lake board.board.
Signed-off-by: Krzysztof Frydryk <Krzysztofx.Frydryk@intel.com>
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Adds the nodes for the GPDMA 1 & 2 peripherals
to the stm32h5 serie.
Each instance has 8 channels and 140 DMA requests.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Adds tmd2620 driver and devicetree bindings to work in
trigger and polling mode supporting Power management.
Signed-off-by: Peter Fecher <p.fecher@phytec.de>
Add LEDC device for esp32s3
Update PWM LED binding
Remove invalid comment from driver source file
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Added UART instances and changes to enabled
support for PCIe UART instances.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
Enabled simultaneous support by adding a DTS variable named “io-mapped”.
There are 3 possibilities through instance in dtsi file.
Under PCIe, PCIe ns16550.
Under soc and has a variable io-mapped, legacy(IO mapped).
Under soc and don’t have a variable io-mapped, MMIO mapped.
Simultaneous access can be enabled by a Kconfig.
For PCIe instances UART initialization should be done post-kernel as it
depends on PCIe initialization.
Co-authored-by: Najumon BA <najumon.ba@intel.com>
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
The sdmmc clock source is either pll1_q or pll2_r according to the
refMan of the stm32h7 devices. HSI48 is not a vaild clock source.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes warnings produced by dtc 1.6 due to missing address-cell
in all arm st exti definition.
Signed-off-by: Christian Spinnler <christian.spinnler@fau.de>
Add the `zephyr,pm-device-runtime-auto` flag to `pm.yaml` and
`struct pm_device`.
This flag is intended to signify to the boot system that device runtime
PM should be automatically enabled on the device after the init function
has run.
Only run `pm_device_runtime_auto_enable` function on a device if
initialisation succeeded. This prevents actions being run on devices
that are not ready.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
Changed the watchdog driver used by the ACE platform from
snps,designware-watchdog to intel,adsp-watchdog.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Adds the nodes for the window and independent watchdog peripherals
plus the rng to the stm32h5 serie
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a driver that listens for input events and reports them on a kscan
API. This allows porting kscan drivers to the input APIs while
maintaining compatibility with the existing kscan based applications.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This patch makes possible to choose custom byte which should be used
to enable non-permanent readout protection (RDP1). Actually, any byte
except 0xAA and 0xCC (which are used by RDP0 and RDP2 respectively)
can be used to enable RDP1 but in multi-image environment, some other
image could check if RDP1 is enabled by comparing it to some hardcoded
value.
If property is not defined, 0x55 will be used to enable RDP1. The
default value comes from STM32 HAL.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Update DMA bindings with DMA config macros
only for st,stm32-dma-v2.yaml and st,stm32-dma-v2bis.yaml
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Adds the new stm32h5 serie to the list of st,stm32g0-exti
compatible : now the matching targets is C0/G0/H5/U5/L5/MP1.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add binding and sensor attribute to allow single phase
mode where only one signal is required from the encoder.
The signal must be connected to Phase A input.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a GPIO nexus binding for Pmod interface connectors.
This commit also includes a header file with macros
that map signal names in the Pmod specification to
the corresponding indices in the GPIO nexus, meant for
use in devicetree files.
Signed-off-by: Alexander Mihajlovic <alexander@eub.se>
Add an input device to take input key events as an input and generates
short press or long press devices as output.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The number of available EasyDMA MAXCNT bits is now defined per-instance
in Devicetree.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Deleted adc_mchp_xec.c and microchip,xec-adc.yaml file.
DTSI, yaml, CMakeLists.txt and Kconfig.xec files are
updated for compatible.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Updated the "adc_mchp_xec_v2.c" adc driver to support both MEC172x and
MEC15xx SOC.
ADC smapling clock configuration updated using DTS.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
The regulator driver has a configured min/max range that is used
to limit set values, and to initialise the regulator.
A new init value has been added, so that the startup voltage can
be higher than the lowest permitted value.
Signed-off-by: Andy Sinclair <andy.sinclair@nordicsemi.no>
Added initial version of Infineon cyw43xxx BT (
H4 HCI extension drivers/bluetooth/hci/CMakeLists.txt)
Add initial version of binding file for Infineon CYW43xx BT
HCI extension driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
This adds a basic Intel TCO watchdog driver. The driver doesn't support
windowed timeouts (a non-zero window.min value) or callbacks. The driver
currently assumes TCO version 6, which can be found e.g. on Elkhart Lake
and Raptor Lake platforms. The driver also expects the TCOBA base
address to be specified through DTS, rather than doing runtime lookup
(using e.g. ACPI or PCIe).
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Remedial rework to handle the enabling of the I2S master clock
output based on the presence of an introduced DT property.
For details see issue/54841.
Signed-off-by: Raul Pando <raul.pando@bytegrity.co.uk>
This update devicetree entries and Kconfig definition to allow use of
reset cause on all SAM series.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
Microchips PolarFire-SoC Icicle Kit has 4x UART interfaces available
via single micro USB and 1x UART for programming and debugging via micro
USB. Add the remaining UARTs to the Devicetree
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Some lines of the mpfs_icicle Devicetree contained a jumble of white
space and tabs. Just use tabs
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Add support for the TI TPS382x series. The IC has an input pin which
should be toggled by the processor and a output pin which should be
connected to the RESET input of the processor. The timeout is not
configurable.
This device can be used by devices which does not have any internal
hardware watchdog device.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Modifying counter drivers (rtc and timer) to rely completely on
device tree and not on Kconfig of MDK flags.
Adapting dtsi for all SoCs and adapting test configuration.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Adds a driver for the Nordic nRF GPREGRET registers and adds
entries to the SoCs for this peripheral.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support for virtual UART device that uses ARC Hostlink channels
for data transfers. Due to the Hostlink principle, this driver
supports only polling API.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This symbol allows users of the driver to disable the
power management feature of just this sensor if they are
not using the int_gpios pin of the BQ274XX.
Signed-off-by: Nick Ward <nix.ward@gmail.com>
interrupts property was previously added with "required: false", but
when required was removed (redundant), the interrupts property was left
dangling.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
To enable Bluetooth controller coexistence feature, there is
implementation of ticker task, which aborts any ongoing radio events
during assertion of the grant pin. This solves the co-existence issue
in the role of the subordinate transceiver.
Signed-off-by: Tomáš Beneš <tomas@dronetag.cz>
This commit removes the deletion of the `sram0` node, which resulted in
the compat string `mmio-sram` missing from the final devicetree when
building stm32l4r5-based platforms in Zephyr.
This bug was introduced in
306dea6ff3.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The zephyr,gpio-keys is now emitting input events, so it makes sense to
require a key code to be set. Change the zephyr,code property to be
required and add an example in the binding description.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Port the gpio_keys_zephyr driver from the gpio subsystem with a
dedicated API to the input subsystem reporting input events.
Move the test as well, simplify the cases a bit since the API is simpler
now.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The 200ns reset time specified in the datasheet are a minimum time; and the
nanoseconds were being rounded to whole microseconds anyway.
Also make it the same type as `config_delay_us` (`uint16_t`).
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":
> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
Change the preprocessor identifier from CONFIG_SOC_ESP32C3 to
SOC_GDMA_SUPPORTED so it can include ESP32S3 in GDMA routines.
Remove hardcoded values from hal calls to use dma_host instead.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
The board embeds an audio codec IC, Cirrus CS42L73. While there is no
in-tree driver for it, we need a binding to describe how it is wired in
the board, e.g. for IRQ/RESET lines.
Following Linux binding for the same IC, create one in
dts/bindings/sound. Note that Linux binding is less complete/outdated.
Ref. https://statics.cirrus.com/pubs/proDatasheet/CS47L63_DS1249F2.pdf
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
There is a spi-flash fl256s on emsdp board, which can be
contolled by DesignWare SPI driver. Now add DW SPI and
SPI-FLASH support for emsdp board.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Remove SPI2 from F070 (not present on F070x6) and add it to F070xB.
Add it to F051 and remove it from F091 (since it is already defined).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Flash erase-block-size is 2048 for F030xC, F070xB, and F071 and higher.
For all others, it is 1024, default value in base dtsi.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove calibrated temperature measure from base dtsi since it does not
exist for STM32F0x0, and add it only for the other STM32F0.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fix DMA1 interrupt channels. There are 7 for STM32F071 and higher, and 5
for all others, default value for the series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove TIM6, 7 & 15 from base dtsi, and add TIM6 & 15 to F030x8, TIM7 for
F030xC, TIM15 for F070, TIM6 & 7 for F070xC, TIM6 & 15 to F051, and TIM7
for F071.
Remove TIM2 from F072 and F091 dtsi since it is already included in F031.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Modify the successive dtsi include to better reflect the underlying
structure of the F0 family.
There are two main subfamilies: STM32F0x0 on one side, and STM32F0x1, x2
and x8 on the other
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Fixes the warning below. This commit does not change the firmware
binary. Thanks Kumar Gala for the suggestion.
build-mtl/zephyr/zephyr.dts:279.42-285.5: Warning (simple_bus_reg):
/soc/ace_comm_widget@71C00: simple-bus unit address format error,
expected "71c00"
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Add driver for Xptek XPT2046 resistive touch controller on SPI.
Only interrupt driven mode supported, does not do polling.
Signed-off-by: Seppo Takalo <seppo.takalo@iki.fi>
- Add overlay for the esp32c3 board to die_temp_polling sample.
- Add aliases for the die_temp_polling sample to esp32c3 dtsi.
Testing Environment:
esp32c3-devkitC-02
Signed-off-by: Hiroki Tada <tada.hiroki@fujitsu.com>
Introduce driver for NXP DCNANO LCDIF (lcd interface) peripheral,
present on iMX.RT500. Currently this driver only supports updating
the primary framebuffer, and does not implement support for the cursor
buffer present on this IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for MCUX MIPI DSI 2L. This IP block differs slightly from
the existing MCUX MIPI peripheral, and uses a different hardware
abstraction layer. For these reasons, a new driver was introduced rather
than extending the existing mcux_dsi implementation.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow configuration of AHB RX buffer allocation. This allows sections
of the AHB RX buffer to be reserved for specific masters, which can
enhance performance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
STM32L432 SDMMC issue
RM0394 :SDMMC
Not available on STM32L42xxx, STM32L432xx and STM32L442xx devices.
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
The driver utilizes ST Microelectronics library (which
exists in modules\hal\st\sensor\vl53l1x. Platform specific
headers and source files used by the library are included
and adapted for Zephyr.
The driver can be configured in proj.conf to use a
interrupt/polling methods and the use of the XSHUT pin on
the VL53L1X. All uses were tested successfully.
Signed-off-by: Mark Watson <mwatson@prosaris.ca>
This patch adds watchdog driver for Renesas Smartbond SOCs.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This adds driver for SmartBond TRNG peripheral that with separate
ISR an thread data pools.
Co-authored-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
Add support for configuring power on delay when using SPI SDHC. This
allows cards that reliably initialize with a shorter (1ms) delay to
avoid the long initialize delay otherwise imposed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add I2C bus recovery support to the STM32 v1 and v2 driver. The STM32 i2c
peripheral does not natively support I2C bus recovery so recovery is
performed using GPIO bitbanging. This mirrors the bus recovery
implementation for NXP MCUX LPI2C driver.
Fixes: zephyrproject-rtos#54917
Signed-off-by: Maxmillion McLaughlin <github@maxmclau.com>
Microchip XEC devices specify GPIO pin using octal numbering and
organize pins in banks of 32. Chip documentation does not use
bank naming rather naming each pin by its octal number. This has
led to the developer having to calculate the bit position of a pin
in its 32-bit bank when a specifying the pin for GPIO usage. We
created a set of defines for all possible GPIO pins that specify
the DT GPIO bank name used in the chip level DTSI files and the
bit position in that bank.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The dma-requests specified for dmamux is changed to
the correct number of 107. This can be found in the
Reference Manual RM0455 Section 17.1.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Extends dmamux driver to support DMAMUX 2,
which supports the BDMA on STM32H7 devices.
Co-authored-by: Jeroen van Dooren <jeroen.van.dooren@nobleo.nl>
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
update MEC172x adc driver to support device PM.
Implement pm resume and suspend actions to put adc
pins in proper state for suspend and resume.
Notify kernel of busy when adc sampling is in progress.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Added initial version of Infineon CAT1 GPIO driver.
Added initial version of binding file for Infineon CAT1 GPIO driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Add initial version of Infineon CAT1 clock control driver.
- supports clock initialization based on board DT configuration.
Added initial version of system_clocks.dtsi for Infineon PSoC 6 SOC.
Includes: clk_imo, path_mux0..4, fll0, pll0, clk_hf0..4, clk_fast,
clk_slow and clk_peri.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Added initial version of Devicetree for Infineon PSoC 6 SOC with following
structure:
1. MPN devicetree files
|--> psoc6
|--> mpns
|--> CY8C6016BZI_F04.dtsi
|--> CY8C6036BZI_F04.dtsi
|--> CY****.dtsi
Those file describes cpus, flash-controller, sram memory, nvic option. It
includes the package dtsi (e.g. psoc6_02.124-bga.dtsi) with information
about gpio (based on package e.g. 68-qfn, 128-tqfp, 124-bga, etc.) and
peripherals for (based on PSoC 6 series, psoc6_01, psoc6_02, etc).
MPN devicetree file is main platform dtsi file, which should be included
from board dts (e.g cy8cproto_062_4343w.dts), example:
#include <infineon/psoc6/mpns/CY8C624ABZI_S2D44.dtsi>
2. Devicetree files for PSoC 6 series 02 (2M).
Includes: psoc6_02.dtsi - peripherals dtsi psoc6_01.xxxxx.dtsi - package
dtsi. User does not directly include those files.
It automatically includes via MPN dtsi.
|--> psoc6_02
|--> psoc6_02.dtsi
|--> psoc6_02.100-wlcsp.dtsi
|--> psoc6_02.124-bga.dtsi
|--> psoc6_02.128-tqfp.dtsi
|--> psoc6_02.68-qfn.dtsi
In future PR/commits will be added Devicetree for support all
PSoC 6 series:
- for PSoC 6 series 01 (1M)
- for PSoC 6 series 03 (512)
- for PSoC 6 series 04 (256)
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Provide dts binding for F412 PLL I2S.
This I2S dedicated PLL is fully configurable and take same
input as Main PLL
Only one output clock (PLLR) is supported for now.
This PLL could be found on STM32F412 and F413 parts for instance.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide dts binding for F4 PLL I2S.
This PLL share input source and input M diviso with F4 Main PLL.
Only one output clock (PLLR) is supported for now.
This PLL could be found on STM32F401 parts for instance.
Additionally, provide related header definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Polarity support added to XEC PWM driver. This allows (for example) PWM
controlled LEDs that are active low to actually be turned off when set
to off.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Rework the Host Command support. It includes:
-change API to backend
-change a way of defining rx and tx buffers
-fix synchronization between the handler and backend layer
-simplify the HC handler
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Follow naming pattern in the subsystems(logging or shell) and name
the layer between generic handler and peripheral driver "backend".
The name doesn't suit that well to the SHI backend, because there isn't
SHI API itself and the SHI interface is used only for the host
communication. So the backend code includes the peripheral driver itself.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Change the dtsi order for the stm32L4plus serie,
starting with stm32l4p5-stm32l4q5 and stm32l4r5-stm32l4s5
Significant changes are on the SRAM size, the sdmmc2
and separated RTC-bbram registers.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The SRAM1(total 192 KBytes) plus SRAM2: (total 64 KBytes)
plus SRAM3(total 512 KBytes) is available from 0x20000000 to
0x200BFFFF.
The SRAM size is only 768KB at address 0x20000000
The 16KB SRAM4 is located at address 0x28000000 so that no ram
is present from 0x200c0000 to 0x28000000.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add the implementation for the akm09918c magnetometer driver.
Additionally, add the appropriate node to the TDK robokit1 device
tree. In order to prevent regressions, add the sensor to the sensor
build_all tests and specific tests using an emulator.
Signed-off-by: Yuval Peress <peress@google.com>
Add a driver implementation that uses the I2S peripheral.
Based off this blog post:
https://electronut.in/nrf52-i2s-ws2812/
Should help with #33505, #29877 and maybe #47780, as there is no garbage
data at the end of transmissions on nRF52832, and no gaps.
Signed-off-by: Jonathan Rico <jonathan@rico.live>
Some register addresses change within the AM6X family.
AM62X is common to AM623X/AM625X processors.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
STM32L4plus mcu has SDMMC internal DMA which works without any
configuration and it's handled by SDMMC HAL driver. This commit adds
option to enable it and use it.
Signed-off-by: Petr Hlineny <development@hlineny.cz>
For STM32L47x and STM32L48x, the high calibration value for temperature is
110. For all other STM32L4xx, it is 130. So we set 130 by default and set
it to 110 for L471.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
ADC3 is already defined for STM32L471 which is included in STM32L476 and in
STM32L496 so no need to define it a second time.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Move LPTIM2 from stm32l431 dtsi to the general stm32l4 dtsi since all
STM32L4xx have two LPTIMs.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Create and use a new `zephyr,i2c-target-eeprom` compatible
within I2C eeprom target driver that allows to use
that driver along with real atmel at24 EEPROM simultaneously.
Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
Microchip's PolarFire SoC has a core complex consisting of one e51
monitor core and four u54 application cores. Add the remaining cpu nodes
to mpfs-icicle device tree. Add the software and timer interrupt irq's
to the clint for the additional cpu nodes.
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
Update machine timer drivers to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on NIOSV devicetree.
Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
All STM32H7 variants seems to have two fd-can interfaces available. Add
a can2 definition in stm32h7.dtsi, drop the current one in
stm32h723.dtsi. Also drop the override of address/size cells, this node
is not supposed to have any child node so they are not needed.
Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit adds access to the string values without a quotes.
Signed-off-by: Radosław Koppel <r.koppel@k-el.com>
Co-authored-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
rt1064 already includes dtsi file for rt1060, including values for ARM and
IPG PODFs. Drop explicit assignment of those PODF values in order to reduce
duplicated code.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS
samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...
tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This commit adds support for BH1750 ambient light sensor.
The driver works using I2C peripheral in one-time mode.
Signed-off-by: Michal morsisko <morsisko@gmail.com>
The Microchip XEC (MEC172x and MEC152x) have a breathing-blinking
LED (BBLED) block which implements a simple PWM mode. The BBLED
PWM frequencies are 32KHz and 48MHz selectable in device tree.
Frequency divider is 12-bit resolution from 256 to (256 * 4096).
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The Microchip XEC family of microcontrollers includes a
simple DMA block implementing multiple channels. DMA supports
memory to memory, memory to peripheral, and peripheral to
memory transfers. Peripheral support is limited by each
chip to I2C and SPI controllers. DMA hardware does not support
scatter-gather or linked transactions.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
* there is a subtle difference to the stm32h74x
* c.f. rm0468 (stm32h723/733 stm32h725/735 and stm32h730)
* verified on stm32h735
Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
Align driver with changes introduced in the hal. `nrf_timer_frequency_set`
was changed to `nrf_timer_prescaler_set`, update driver accordingly.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
New Zephyr WDT driver for TI CC13xx/CC26xx family.
Supports interrupts & MCU soft reset on timeout.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Each GPIO controller may contain GPIO hog definitions. GPIO hogging is a
mechanism for providing automatic GPIO configuration during system
initialization.
Each GPIO hog is represented as a child node of the GPIO controller.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
changes to support low power and wake support in microchip xec uart
driver. Add support for wakerx_gpio config in dts to select the wake gpio.
Configure for wake in PM_DEVICE_ACTION_SUSPEND state and clear
interrupt in wake isr. Also added support for
CONFIG_UART_CONSOLE_INPUT_EXPIRED
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
assign interrupt number 0 for jtag_uart.
Number can be found in soc/nios2/nios2-qemu/include/system.h
JTAG_UART_0_IRQ 0
Signed-off-by: Goh Shun Jing <shun.jing.goh@intel.com>
This board is confirmed to build and run simple applications in
RTL simulation as described in the included board documentation.
Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
According to the reference manual, all STM32G4 variants except
STM32G431/STM32G441 have the UART5 peripheral.
Signed-off-by: Mario Jaun <mario.jaun@gmail.com>
Boolean properties for STM32 ADC internal channels are not used anymore
and can be removed. It is replaced by channel number properties.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
In all STM32 dts, remove all reference to the following properties:
- has-temp-channel
- has-vref-channel
- has-vbat-channel
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that we have a binding to define the channel number for temperature
and Vref measurement, update all dtsi to include the information.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add some bindings to define STM32 ADC internal channels for:
- Temperature
- Vref
- Vbat
The goal is to transfer information to the dts instead of inside the
ADC driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Bugfix for the Cyclone V SoC DK ethernet driver need to add emac-index
in dts
- We remove the "local-mac-address" property from
dts/arm/intel_socfpga_std.dtsi to
boards/arm/cyclonev_socdk/cyclonev_socdk.dts, since this value is
dependant on the board / implementation and not universal to
the "intel_socfpga" package that it inherets from.
- The above is also true for the "status" property as the board
should enable the device.
Signed-off-by: Benjamin Kyd <benjamin.kyd@intel.com>
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Add a driver for the NXP MCUX Quadrature Decoder. The driver
is simple and only implements the phase a and phase b inputs. The
module has additional features which can be added in future PRs.
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Change the name of the custom macro defined for the stm32 devices
to fit the VND_PWM_xxx model
Keeping old deprecated macro, though.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce Ethernet low-level driver for NXP S32 Network Controller
(NETC). Current driver allows to manage from Zephyr a Physical Station
Interface (SI) and/or a Virtual SI. The NETC has an integrated Ethernet
Switch. Currently the Switch is initialized from this driver with a
default configuration, and all ports are enabled and transparent for
the user. A separate Switch driver should be addressed in future patches.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce NXP S32 NETC External MDIO controller driver. Driver supports
a single instance, as current support is based on NXP S32Z/E SoCs.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Introduce NXP S32 Message Receive Unit (MRU) driver based
of Mbox API. The MRU couples with a processor and allows to
receive messages from senders, which are other modules or
processors.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
On STM32L4 that probvide HSI48 clock, use it as 48MHz domain clock.
This impacts following devices:
-SDMMC
-RNG
-USB
Otherwise, when HSI48 is not available MSI is used.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STMF412 and STM32F413 did not support CAN bus in Zephyr yet.
This adds the device tree entries to be able to use all 2, resp.
3 CAN controllers.
Signed-off-by: Tom Stirnkorb <tom@stirnkorb.me>
Remove the vref-mv = <3300>; property for all the ADC node of
the stm32 devices as it is set by default to 3300mV by the
dts/adc/st,stm32-adc.yaml
(Except for the stm32f303 vref is 3000mV)
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Configure RNG domain clock and align it on USB (as this is the same clk).
This is not stricly required, as this configuration matches default
reset but its more consistent this way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove SDMMC from f410 soc variant since it's not actually available.
Do this in package variant as F410 is included by f412 who has a SDMMC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Provide SDMMC domain clock, when required (because it is common)use
the same as the one selected by USB and RNG.
Otherwise, when available use HSI48, otherwise use the most handy (MSI,
sysclk ...).
PLLSAI is not used as not implemented for now.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add 2 properties in STM32 external interrupt controller:
- num-lines
- line-ranges
Additionally, make interrupt-names a required property.
The properties will help to simplify exti init code in building the
exti_irq_table and simplify the isr related bits.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Align RNG domain clock confguration on USB clock configuration.
For now we're not able to fully use CLK48 as a mux clock, so
this has to be done on both nodes rather than on a centralized
fashion.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The interrupt is used to wake up EC from low power mode.
So EC does not defer eSPI bus while transaction is accepted.
Fixes EC host commands slow issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
This commit makes the peripheral-id property optional and removes it's
usage from the Gecko SPI driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
ALH dts definitions need to have 16 nodes, thus add them to supported
platforms (cavs25 and ace15).
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This sets the RNG node that will be used by the Nordic
devices which support TF-M (nRF5340/nRF9160) to use the
defined scheme with psa_generate_random.
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
The documentation for the fixed-partitions binding is missing critical
information and is vague in other important respects. This is an
important binding that deserves to be crystal clear. Fix it.
Signed-off-by: Marti Bolivar <marti.bolivar@nordicsemi.no>
Describe USB default domain clock on all USB devices.
When available select HSI48.
On some series, a default clock my be set by default at start up.
On those series, in order to be able to compute USB clock at runtime,
clock_control driver needs to be aware of configuration and then this
default config has to be described explicitly too.
Default clocks are not enabled though. It is up to board configuration
to provide correct clock configuration (and we should not enabled by
default clocks that would not be required by board configuration).
Note: This change doesn't consider STM32F1/F3 devices, which
have a specific USB clock configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add kscan pins gpio driver for KSI[7:0], KSO[15:0] pins that
they can be configured to gpio mode. These pins registers address,
bit fields and function are different from GPIO group, so I create
a new compatible driver for these pins.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
- Adds the declaration of the MMC API
- Adds MMC spec related declarations
- Adds some properties to sdhc dts binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
While nPM1100 is to be operated in fixed configuration for some
applications, it has some degree of configuration via GPIOs. For
example, mode (auto/PWM) can be configured via MODE pin. VBUS current
can also be adjusted using ISET pin, even though there is no API yet to
limit the PMIC input current.
This patch adds a new regulator class driver for nPM1100 PMIC, so that
it can be used with the standard regulator API when needed.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In file stm32l412.dtsi, spi2 was missing fifo compatibility,
this way failing to initialise fifo threshold correctly
when spi data width is configured.
Signed-off-by: Mirko Bottarelli <mirko.bottarelli@gmail.com>
Add rng definition to f410.
Though, don't inherit directly in f412 as it's integrated
in a different way.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ease description of DCKCFG regsiters,
make f412 a variant of f410 as it supposed to be.
Only exception is missing DAC1.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The interrupt and watchdog registers of the it82xx2 will be
remapped, so these device nodes should be separated to
it81xx2 from it8xxx2. it8xxx2 dtsi are common settings
for it81xx2 and it82xx2.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
This commit adds the support for host commands being transported
by the Serial Host Interface on the IT8xxx2 SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Adds a driver for TDK InvenSense 42688 six axis IMU. Verified using
the sensor shell sample app via:
- sensor info
- sensor get icm42688p@0
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Signed-off-by: Yuval Peress <peress@google.com>
Add the st,static-prescaler DTS property to the
stm32u5 family on the LPTIM1.
Also present on lptim3, 4 but not defined yet.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add a st,static-prescaler optional property to DTS
of the stm32 where the LPTIM has a x2 factor on
its clock input.
This property is present or not depending on the stm32.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Drop compatible from fuel-gauge.yaml, it's not needed since this binding
is not meant to be used directly, and is also incorrect as it includes
the "yaml" suffix.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The GCR, PINCTRL, I2C and WUC registers of the it82xx2 will be remapped,
so these device nodes will not be in the it8xxx2.dtsi, these should be
separated to create a it81xx2.dtsi.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Purpose of this node is only to provide a way to configure RF
clock using device tree and clock_control driver.
Default configuration is reproducing existing hard-coded configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add missing interrupts property for second FlexSPI device on RT5xx.
This interrupt is shared between both FlexSPI devices, but the memc
driver does not use interrupts so no conflict should arise.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all comments-indentation errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(comments-indentation)'
This checks that the comment is aligned with the content.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all hyphens errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(comments)'
Default config would be to require two spaces after the start of the
comment, proposing to keep it on 1, inline with the Linux binding
config, that is:
```
- comments:
- min-spaces-from-content: 1
```
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all hyphens errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(hyphens)'
Default config is only one space after the hyphen.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all brackets errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(brackets)'
Default config is to have no spaces inside brackets, changed few
documentation strings as well that refered to lists even though the
linter does not care about those.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The addresses of the flash and flash controller of the RP2040
SoC were mixed up. There was no clear distinction between the
flash and the flash controller, which was unclear but also
caused a DTC warning.
This commit makes the distinction clearer: The SSI peripheral at
0x18000000 is the flash controller, and the flash itself starts
at 0x10000000. The flash driver and rpi_pico.dts were fixed
accordingly.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
The pinctrl node of the RP2040 had the same unit address as the GPIO
bank, causing a DTC warning. To fix this, the pinctrl's address was
removed, as it does not require any.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add initial support for gd32l23x series. gd32l23x used Cortex-M23, based
on ARMv8-M baseline, implement the System Timer.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Enable RTU.SWT (Real-Time Unit.Software Watchdog Timer) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to 48 Mhz.
Signed-off-by: Quang Bui Trong <quang.buitrong@nxp.com>
Add missing I2C clock sources for STM32F303 & F373.
Add a comment for all STM32F3 I2Cx and for STM32F0 I2C1 that the clock
source should always be defined.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add config cell property to gd,gd32-dma.
For supporting hardware variation, Splitting base definition
to gd,gd32-dma-base.yaml.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Define SYSCLK as the default I2C source clock for I2C1 on STM32F0x
and all I2Cx on STM32F3x.
On most series, the default I2C clock source (when it exists) is PCLK.
This clock does not exist as I2C clock source on FO & F3 and the default
one is HSI. Since HSI is not necessarily enabled we explicitly set it
to SYSCLK instead.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Include the new clock file dedicated for STM32F7 instead of the F4 one
previously used.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
peripheral-id property should be eventually removed.
For now set it as optional and allow skipping the usage
in UART driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
peripheral-id property should be eventually removed entirely.
For now set it as optional and allow skipping the usage
in GPIO driver.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
HAL update affects also EFR32MG21 SoC. Because of that we need to
update the reg addresses in DTS.
Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds initial support for Silabs Real-Time counter
Co-authored-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
This commit adds a series of driver-related changes to
Gecko pinctrl.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit adds initial support for gecko pinctrl driver
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add FFF-based fake regulator driver. This driver can be used as a stub
or mock in testing.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
These inherited properties from Linux bindings are not supported yet.
The reason for the removal is because regulator-couple-with requires
definition of #cells spec, unless bindings explicitely ban the property
or use allowlist.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add i.MX93 Cortex-A Core support on Zephyr.
i.MX 93 applications processors deliver efficient machine learning
(ML) acceleration and advanced security with integrated EdgeLock
secure enclave to support energy-efficient edge computing.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Adds two additional alh2 and alh3 "devices" to already defined
alh0 and alh1. This (seems) is a temporarily solution as
the hardware actually supports 16 streams and future update
to device tree is required.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Add support for virtual USB host controller intended for use
together with virtual bus and virtual device controllers.
This driver is not an emulation of any real host controller.
The driver has initial support for handling control and bulk
transfers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add support for virtual USB device controller intended for use
by virtual bus and virtual UHC controllers. This driver is not
an emulation of any real host controller.
The driver has initial support for handling control and bulk
transfers.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add common layer of UHC API and MAX3421E host controller driver.
This implements the bare minimum necessary to communicate with
one peripheral device.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Assigning power domain to the GP DMA.
NOTE: Only controllers 1 and 2 are under IO_0 domain, controller 0 is
under HUB-ULP domain.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Support for the measuring the CPU die temperature
for the ESP32 targets S2,C3. The ESP32 support
was ommited due to lack of offset calibration.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Serial speeds listed in device tree did not reflect
what driver supports.
2M and 500K were missing while
1200, 2400 and 460800 were present while not supported.
This change synchronized dts with driver code:
drivers/serial/uart_smartbond.c
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
PCA9420 PMIC offers of multiple operation states, or DVS (Dynamic
Voltage Scaling). Such states may be automatically changed by hardware
using MODESEL0/1 pins. Certain MCUs allow to automatically configure
certain output pins when entering low power modes so that PMIC state is
changed without software intervention. This means that application just
needs to configure the voltages for each state using
`nxp,modeN-microvolt`, set `nxp,enable-modesel-pins` in devicetree and
forget about configuring regulators.
This patch introduces a new _parent_ API to expose such functionality in
a vendor agnostic way. Consider this API as experimental for now, until
we have other usecases.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Most of devicetree properties for regulator, such as:
- regulator-min/max-microvolt
- regulator-min/max-microamp
- regulator-allowed-modes
- etc.
Are meant to specify limits on what consumers may set. They are **NOT**
meant to describe the hardware capabilities. For example, I could have a
BUCK converter that supports 0-5V output voltage, but my circuit may
only allow working on the 2.7-3.3V range.
This patch reworks the API so that the API class layer manages this
information. This is done by drivers collecting all such fields in a
common configuration structure that is later accessed by the class
layer. This simplifies drivers implementation. For example, if A
consumer calls regulator_set_voltage() with a voltage that is supported
but not allowed, driver code won't be called. Similarly, if a regulator
is configured to be `always-on`, enable/disable driver code will never
be called.
Drivers have been adjusted. PCA9420 mode settings have been removed from
devicetree in this commit as they are not actual modes but PMIC states.
This will be refactored in a follow-up commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The stm32G0 device has a one APB peripheral clock bus
but splitted on two RCC registers: RCC_ABPENR1 and RCC_ABPENR2
Peripherals are on one or the other.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
The interrupt-map property specifies both 32-bits values and a phandle;
update the type accordingly.
Update the definition of pcie-host-ecam-generic on qemu arm64 to match
the new type.
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
Add DTS information for qemu-virt-a53 and qemu-kvm-arm64 for PCIe
controller support. Three new bindings are required for the PCIe
controller in ECAM mode.
The DTS information was extracted from QEMU (dumpdtb) with a PCIe device
attached to the virtual machine (ivshmem)
Signed-off-by: Rodrigo Cataldo <rodrigo.cataldo@huawei.com>
Co-authored-by: Henri Xavier <datacomos@huawei.com>
We are about to add UART reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
We are about to add timer reset during driver initialization. First step
is to add 'resets' property, which provides information about reset
register offset and bit.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
To deassert reset in STM32MP1 RCC the driver needs to set the bit in
reset clear register.
This patch extends existing implementation to support this type of
register.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reset controller node is necessary to enable support for resetting
peripherials using RCC.
This patch also includes RCC reset registers offsets used by STM32_RESET
macro.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
This driver exposes STM32 RCC reset functionality through reset API.
Information about RCC register offset and bit is encoded just like GD32.
The first 5 least significant bits contains register bit number.
Next 12 bits are used to keep RCC register offset. Remaining bits are
unused.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32L4 devices, except STM32L412 STM32L422 STM32L4P5 STM32L4Q5, have
32 4-byte battery-backed RTC backup registers. Other STM32L4 devices
have backup registers in tamper module, not used in Zephyr.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All STM32L1 devices have 4-byte battery-backed RTC registers, but
they have different number of registers:
STM32L151Xb-a has 5 registers.
STM32L151Xb has 20 registers.
STM32L151Xc, STM32L152Xc, STM32L152Xe have 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add BBRAM entry for all STM32H7 microcontrollers except STM32H7A3 and
STM32H7B3 which have backup registers in tamper module.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
All supported STM32F3 devices have 4-byte battery-backed RTC registers,
but they have different number of registers:
STM32F303x8 and STM32F334 have 5 registers.
STM32F303xc and STM32F303xe have 16 registers.
STM32F302x8 has 20 registers.
STM32F373 has 32 registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Among supported devices only STM32F031, STM32F051, STM32F072 and
STM32f09x have 5 4-byte battery-backed RTC registers.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
STM32 battery-backed RAM is organized in 4 byte registers. Number of
registers can vary between models from 5 to 32 registers.
Usually, the registers are part of RTC. On some variants they are part
of tamper module. On STM32F1 the registers are in separate module. For
now, only backup registers from RTC are supported.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Add definitions for DMAs, Digital Audio Interfaces (DAIs) and
the necessary clocks to enable full use of audio peripherals
in the intel_adsp_cavs25_tgph boards.
Link: https://github.com/thesofproject/sof/issues/6710
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
NXP LPUART IP supports rs485 mode when transceiver driver enable
using RTS. Allow setting rs485 mode up via the "nxp,rs485-mode"
dts property. "nxp,rs485-de-active-low" dts property can be used
for set RTS polarity.
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
Add the HSI48 clock to the stm32 devices that have this
clock signal.
Within a stm32 family, only few might have the
RCC_HSI48_SUPPORT.
STM32WB has a CLK48 mux.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT1170 and RT1160 CM7 and CM4 cores have the same set of differences.
Merge the DTS files for both CM4 and CM7 cores, to create generic
rt11xx_cm4 and rt11xx_cm7 files.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
- Similar to what was done for other parts of the driver, remove any
register specification from Devicetree (modesel-reg/mask)
- Keep all the information in the driver, and define modes as "numbers",
e.g. PCA9420_MODE0: 0, PCA9420_MODE1: 1, etc.
- Bindings provide IC defaults now (all modes allowed 0/1/2/3 and
initial mode set to 0).
- When mode is controlled via the MODESEL0/1 pins (ie directly by an iMX
MCU using the dedicated PMIC_MODE0/1 pins), the driver will not allow
to select a mode (it is not possible). This mode is now enabled by
setting `nxp,enable-modesel-pins` in Devicetree. When enabled, all the
allowed modes are configured to be selectable via pins. When disabled,
mode can be set via I2C (using TOP_CNTL3 MODE0/1_I2C fields)
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add system reset control device (sysrst), so that the drivers can
assert/deassert its reset line through the public reset controller
driver API.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add bindings for Aspeed AST10x0 reset driver. The reset line can be
de-asserted or asserted through the syscon registers.
Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Add RX and TX fifo size properties to CDC ACM UART bindings.
This allows per instance settings in contrast to Kconfig
USB_CDC_ACM_RINGBUF_SIZE option. New properties takes the default
size value of USB_CDC_ACM_RINGBUF_SIZE which can be removed
subsequently.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Add rgb-is-inverted option to indicate module's pixel-format is
inverting from MADCTL settings of ST7735R controller.
This option intends to implement a workaround for LCD modules
that is the actual screen color was different (inverted)
from the RGB setting in MADCTL property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Implement a LED driver for Microchip XEC using the breathing,
blinking LED controller. The driver supports LED on, off, and
blink API's. The BBLED block uses the 32768 Hz clock domain
allowing the module to operate in light and deep sleep states.
Blink frequency is 32768 divided by 256 * (prescale + 1) where
prescale is a 12-bit value. Duty cycle is specified by an 8-bit
value where 0 = full off, 127 is 50%, and 255 is full on.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Re-enable the CAAM for entropy
now that the HAL driver has been fixed
Job descriptors must be accessed coherently
between CAAM DMA and core.
The M4 Cores still do not work
because of mpu/cache/kconfig arch complications,
disable caam for M4 cores in DTS
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Remove regulator-fixed-sync specialization, create a single driver that
is always synchronous. The asynchronous part is rarely/never used, so
let's keep things simple for now.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Enable RTU System Timer Module (STM) instances on
s32z270dc2_r52 boards. Module clock frequency is fixed to
133.333333 MHz.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
NXP S32 System Timer module includes a 32-bit count-up timer and four
32-bit compare channels with a separate interrupt source for each
channel. The timer is driven by the module clock divided by an 8-bit
prescale value.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
add Intel HDA DAI driver
Long device list in dtsi needs to be refactored in the future
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
The driver had a conceptual issue regarding current limitation. PCA9420
is able to limit the current flowing through VIN, ie input current. This
is a global setting, not individual to each regulator. This patch
creates a new DT property: nxp,vin-ilim-microamp to specify such limit.
It is applied when the device is initialized.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Voltage ranges were hardcoded in Devicetree, however, things can be
significantly simplified by using the recently introduce linear ranges
API. All values are now computed using information stored in the driver,
so there is no need to store any lookup table in ROM. Code should now
both be faster in average and consume less ROM.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Maximum current was not specified. Even though not used, yet, it is a
valuable information. Values taken from PCA9420 datasheet, Figure 1
"Simplified block diagram".
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Regulator registers were set for each BUCK/LDO in DT, likely because of
the way the devices were instantiated. When using a generic iterator,
ie, DT_INST_FOREACH_CHILD, there's no way to differentiate the child
being _parsed_. Since instantiation happens now based on child node
names, we are able to know which registers each devices gets assigned at
the driver level. This greatly simplifies Devicetree, and it actually
removes information that is not strictly hardware description from it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Right now the PCA9420 driver instantiates by iterating over all
children. This is somewhat problematic, for a few reasons:
- Since instantiation is generic code, we're forced to put internal
details on Devicetree, e.g. reg-masks. After this change, this will no
longer be necessary.
- We take all children, regardless of what is defined in DT.
While we have no means to validate Devicetree node names as in Linux
dtschema, this approach allows us to have per-child specific
initialization code. This is somewhat similar to the Linux approach.
Note: nodelabels have been removed, since they were not used.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
regulator-allowed-modes/regulator-initial-mode are standard properties
defined in regulator.yaml, so use them.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Import all Linux properties, so that we can maximize compatiblity with
upstream bindings.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following Linux regulator.yaml, regulator-name is a common property for
all regulators.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Define the octospi node for the stm32l4plus MCUs from
STMicroelectronics.
It is controlled by a OSPIMgr in front of each peripheral.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The sdhc-spi-slot requies an spi bus, but sd nodes (like sdmmc-disk)
cannot be added to it without a warning because it does not declare an
sd bus.
Signed-off-by: JP Sugarbroad <jpsugar@amazon.com>
RT1718S is an i2c-based TCPC chip that supports 3 additional GPIOs.
The pins can be used for USB-C operations e.g. handling FRS, but they
can also work as usual GPIOs.
Add a driver for the RT1718S GPIO and a handler for an alert signal from
the chip. The handler reads the alert register once asserted and calls
the GPIO interrupt handler if needed(Vendor-defined alert).
gpio_rt1718s.c file and "richtek,rt1718s" node collect common properties
and data for all RS1718S functionalities. The file can be extended for
TCPC driver. rt1718s.h file also defines inline functions with i2c
operations common for all drivers. The common header and source files
can be moved to tcpc directories once the tcpc driver is added since it
is the main functionality.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Add drdy_pulsed property in Device Tree in order to select how
data ready irq should behave (either pulsed or latched mode).
Moreover change/fix the API called to set drdy irq mode.
(fix#51944)
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Since we can include other binding files at any level (child,
grand-child, etc.) it makes no sense to maintain two copies of pinctrl
props definitions (pincfg-node/pincfg-node-group). Instead,
pincfg-node.yaml defines props at root level, and it is included where
needed, either child-binding or grandchild-binding.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Added i-cache-line-size and d-cache-line-size values
to device tree for cavs and ace platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added to the device tree values of the dma-copy-alignment
and dma-buf-size-alignment attributes.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
dma-buf-size-alignment: Buffer size alignment required by the DMA
controller.
dma-copy-alignment: Minimal chunk of data possible to be copied
by the controller.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Renamed the dma-buf-alignment field to a more explicit
and descriptive name dma-buf-addr-alignment.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
No sfdp-table property given by the DTS but received from
the octoflash Node rely on the issued by the read sfdp command.
Note that the size of the mx25lm51245 flash controller
is expressed in bits (ie 512Mbits or 64 Mbytes).
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Changing pcie0 to pcie0: pcie0 allows it to be referenced as &pcie0. I
am not sure why this is required. Otherwise I get error:
...
parse error: undefined node label 'pcie0'
...
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
FlexSPI memory map indicates that the FlexSPI register space is 128MB, not
64MB. Update this value to be correct.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Add a sample sbs gauge driver with feature parity and basic tests
comparison to its sensor counter-part. Includes a simple stub test that is
extended upon.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Added support for fxas21002 sensor over SPI bus on
RDDRONE board and proper selection through dts.
Tested with fxas21002 sensor on RDDRONE.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Sumit Batra <sumit.batra@nxp.com>
Added support for fxos8700 sensor over SPI bus on
RDDRONE board and proper selection through dts.
Tested with fxos8700 sensor on RDDRONE.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Sumit Batra <sumit.batra@nxp.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Use the new PCIe core infrastructure for looking up the BDF at runtime
based on the VID/DID values.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
The BDF values can differ on the same platform, based on e.g. BIOS
configuration, and in the case of qemu the command line parameters. It's
therefore more reliable to always look up the BDF value based on the
known Vendor and Device IDs.
This patch introduces such a framework, and allows the incremental
update of PCIe drivers to start taking advantage of it.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Add property mxicy,mx25r-power-mode to jedec,spi-nor binding for
controlling low power/high performance mode on Macronix MX25R* Ultra Low
Power flash devices.
- "low-power" configures the flash in ultra low power mode.
- "high-performance" configures the flash in high performance mode.
Signed-off-by: Gregers Gram Rygg <gregers.gram.rygg@nordicsemi.no>
Updating mps3_an547 board files with DTB entries for Ethos-U.
Adding DTS bindings for the Ethos-U DTB entry.
Signed-off-by: Kristofer Jonsson <kristofer.jonsson@arm.com>
Signed-off-by: Fredrik Knutsson <fredrik.knutsson@arm.com>
This commit adds an ieee802154 node to the list of nRF5340 application
core's peripherals. While it does not translate directly into a physical
RADIO peripheral, it represents the capability to use the ieee802154
radio (indirectly, through the network core).
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
The sensor uses the ALERT terminology (pin can be configured to trigger
on certain events such as conversion ready or overvoltage alerts). The
"IRQ" name is not clear.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Specify the units of the current LSB in microamperes, so that we can
measure low maximum currents. Right now it was specified in
milliamperes, but ignored and always hardcoded to 1mA in the driver.
This makes the driver pretty much useless when the maximum current to be
measured is in a range of e.g. 20-50mA.
This patch also removes some unnecessary ifdeffery: since we write the
calibration register, we can always provice measurements with the right
units. It is also wrong to provide sensor readings that do not match
with the units specified by the channel. After this change voltage is
always reported in V, current in A and power in W.
Note that power measurement had the current LSB hardcoded in the
calculation (assuming 1mA/LSB), this has been fixed as well.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Following dtschema practices, add phyisical units to the shunt resistor
value: milliohms.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The "pmic" driver was in reality a driver for NXP PCA9420 PMIC. There's
no "universal PMIC". While the driver may work for other NXP PMICs, it
is clearly not generic for other vendors PMIC.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Force cache-size to 0 and treat flashdisk as read-only when backing
partition has read-only flag set. This allows users to save RAM when the
application does not write to the flashdisk, e.g. when a predefined FAT
filesystem is used.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Ensure that PECI block is enabled in the EC Subsystem by clearing
the PECI_DIS (peci disable) register
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Sort SoC nodes by address to make it easier to find them. As part
of this also move the intel-sha node under SoC where it belongs.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Following the modification of the STM32 OSPI driver, the clock-names
binding is now required
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
For all STM32 featuring octospi, clock-names are added to use them
instead of indexing for configuring the clock.
For U5 series, a third clock is added for the OSPI manager.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
"alh0: alh1:" will create only one instance and this needs to be
reverted to original form with two instances
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
As the power domain nodes don't represent something accessible via
a MMIO register move those under the lps node to address warnings
generated when building the DTS.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
The icmsg backend for ipc_service has a limitation of supporting only
on endpoint. This limitation is acceptable for many IPC instances.
However, some require to use multiple endpoints sharing a single
instance. To preserve the simple and the most efficient single-instance
backend, a separated backend is introduced implementing a wrapper
around icmsg core which adds multiple endpoints support.
There are two multi-endpoint ipc_service icmsg backends: one in the
initiator role, and the other one in the follower role. In a IPC
configuration one end of communication must be in the follower role
while the other one is in the initiator. The initiator initiates
an endpoint discovery handshake to establish enpoint identifiers for
requested endpoint names. The follower responds to requests sent by
the initiator.
Signed-off-by: Hubert Miś <hubert.mis@nordicsemi.no>
For larger transfers DMA can be used enabling other tasks
to continue running. A threshold of 32 byte transfers
is about right and is defined threshold value for using DMA.
This does not currently support multiple SPI transactions changing
chip select with DMA (though the hardware supports this) currently.
Instead opting for the simpler first change of enabling one shot
DMA SPI transfers for those where the size warrants it.
Adds the loopback binding option to enable the spi_loopback test.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Set the status of the DMA controller, xdmac, to disabled. In effect
changing the default status from okay to disabled for all sam e70
based board.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Add support input interrupts for GPIO pins on NXP S32Z27
SoC. The driver will convert GPIO pin to respective
interrupt line that will be processed by External
Interrupt Controller.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add initial support for the NXP S32Z27 SIUL2 External
Interrupt Controller. Each SIUL2 node has a child node
will act as an interrupt-controller that processes external
interrupt signals.
This driver is required to manage GPIO interrupts.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
New ADC driver for the TI CC13xx/CC26xx family.
ADC channel configurations are translated from Zephyr constants to
simplelink driverlib ones (e.g., sample times use a lookup table).
Async mode was also implemented & tested.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.
The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.
The code is inspirated from atmel_sam0/samd21.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This commit adds an optional property to the nRF21540 Front-End Module
devicetree description that specifies supply voltage in mV. This
property can be used by the nRF21540 driver to compensate the value of
achieved gain for different supply voltage.
Signed-off-by: Artur Hadasz <artur.hadasz@nordicsemi.no>
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Define the DMA and DMAMUX peripheral for the stm32MP1
DMA1 and 2 are of type V1 of 8 streams (channels) each
with a DMAMUX peripheral. See the RefManual for details.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Add SparkFun Pro Micro header connector that is implemented by many
other controllers. This allows hardware with compatible headers to
define the related GPIOs and peripherals.
Signed-off-by: Peter Johanson <peter@peterjohanson.com>
Cavs25 alh definition is currently the same as in ace platform, which is
wrong, thus fix it.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
