michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: ssp: Repleace shim2 with hdamlssp

Browse source 
Repleace usage of shim2 device tree field with hdamlssp.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Jaroslaw Stelter 2023-01-26 13:20:26 +01:00 • committed by Anas Nashif
commit 99d5d9aaa8
4 changed files with 17 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

20
drivers/dai/intel/ssp/ssp.c
View file

@ -29,7 +29,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
#define dai_base(dai) dai->plat_data.base
#define dai_ip_base(dai) dai->plat_data.ip_base
#define dai_shim_base(dai) dai->plat_data.shim_base
#define dai_shim2_base(dai) dai->plat_data.shim2_base
#define dai_hdamlssp_base(dai) dai->plat_data.hdamlssp_base
#define DAI_DIR_PLAYBACK 0
#define DAI_DIR_CAPTURE 1
@ -725,11 +725,11 @@ static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t i
I2SLCTL_CPA(index), 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#elif CONFIG_SOC_INTEL_ACE20_LNL
sys_write32(sys_read32(dai_shim2_base(dp) + I2SLCTL_OFFSET) |
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) |
I2SLCTL_SPA(index) | I2SLCTL_OFLEN,
dai_shim2_base(dp) + I2SLCTL_OFFSET);
dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
/* Check if powered on. */
ret = dai_ssp_poll_for_register_delay(dai_shim2_base(dp) + I2SLCTL_OFFSET,
ret = dai_ssp_poll_for_register_delay(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(index), 0,
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#else
@ -761,11 +761,11 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t
I2SLCTL_CPA(index), I2SLCTL_CPA(index),
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#elif CONFIG_SOC_INTEL_ACE20_LNL
sys_write32(sys_read32(dai_shim2_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(index)) &
(~I2SLCTL_OFLEN), dai_shim2_base(dp) + I2SLCTL_OFFSET);
sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(index)) &
(~I2SLCTL_OFLEN), dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
/* Check if powered off. */
ret = dai_ssp_poll_for_register_delay(dai_shim2_base(dp) + I2SLCTL_OFFSET,
ret = dai_ssp_poll_for_register_delay(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET,
I2SLCTL_CPA(index), I2SLCTL_CPA(index),
DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
#else
@ -2240,10 +2240,10 @@ static const char irq_name_level5_z[] = "level5";
.plat_data = { \
.base = DT_INST_REG_ADDR_BY_IDX(n, 0), \
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(sspbase)), \
(.ip_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(sspbase), 0),)) \
(.ip_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(sspbase), 0),))\
.shim_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(shim), 0), \
IF_ENABLED(CONFIG_SOC_INTEL_ACE20_LNL, \
(.shim2_base = DT_INST_PROP_BY_IDX(n, shim2, 0),))\
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(hdamlssp)), \
(.hdamlssp_base = DT_REG_ADDR(DT_NODELABEL(hdamlssp)),))\
.irq = n, \
.irq_name = irq_name_level5_z, \
.fifo[DAI_DIR_PLAYBACK].offset = \

2
drivers/dai/intel/ssp/ssp.h
View file

@ -318,7 +318,7 @@ struct dai_intel_ssp_plat_data {
uint32_t ip_base;
uint32_t shim_base;
#ifdef CONFIG_SOC_INTEL_ACE20_LNL
uint32_t shim2_base;
uint32_t hdamlssp_base;
#endif
int irq;
const char *irq_name;

5
dts/bindings/i2s/intel,ssp-dai.yaml
View file

@ -24,8 +24,3 @@ properties:
dma-names:
required: true
shim2:
type: array
description: |
Intel HD Audio Multiple Links Capability Structure
for I2S / PCM Link.

12
dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
View file

@ -163,13 +163,18 @@
reg = <0x28000 0x1000>;
};
hdamlssp: hdamlssp@d00 {
compatible = "intel,adsp-hda-ssp-cap";
reg = <0xD00 0x40>;
status = "okay";
};
ssp0: ssp@28100 {
compatible = "intel,ssp-dai";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00028100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x00 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 1
@ -185,7 +190,6 @@
#size-cells = <0>;
reg = <0x00029100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x01 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 2
@ -201,7 +205,6 @@
#size-cells = <0>;
reg = <0x0002a100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x02 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 3
@ -217,7 +220,6 @@
#size-cells = <0>;
reg = <0x0002b100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x03 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 4
@ -233,7 +235,6 @@
#size-cells = <0>;
reg = <0x0002c100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x04 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 5
@ -249,7 +250,6 @@
#size-cells = <0>;
reg = <0x0002d100 0x1000
0x00079C00 0x200>;
shim2 = <0x0D00 0x10>;
interrupts = <0x04 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 6