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ace20_lnl: dts: Add d-cache and i-cache line size

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Added i-cache-line-size and d-cache-line-size values
to device tree for ace20_lnl platforms. These values
are used by sys_cache_instr_line_size_get and
sys_cache_data_line_size_get functions.

Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
This commit is contained in:
Jaroslaw Stelter 2023-05-11 14:14:08 +02:00 • committed by Anas Nashif
commit edaac6d8d2
1 changed files with 2 additions and 0 deletions
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dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
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@ -17,6 +17,8 @@
compatible = "cdns,tensilica-xtensa-lx7";
reg = <0>;
cpu-power-states = <&d0i3 &d3>;
i-cache-line-size = <64>;
d-cache-line-size = <64>;
};
cpu1: cpu@1 {