drivers: loapic: add device tree support for loapic
As per #26393, Local APIC is using Kconfig based option for the base address. This patch adds DTS binding support in the driver, just like its conunter part I/O APIC. Signed-off-by: Umar Nisar <umar.nisar@intel.com>
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14 changed files with 101 additions and 37 deletions
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@ -13,6 +13,7 @@
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* exception) stubs are implemented in this module. The stubs are invoked when
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* entering and exiting a C interrupt handler.
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*/
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#define LOAPIC_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(intc_loapic))
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#include <zephyr/arch/x86/ia32/asm.h>
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#include <offsets_short.h>
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@ -197,10 +198,10 @@ alreadyOnIntStack:
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wrmsr
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#else /* xAPIC */
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#ifdef DEVICE_MMIO_IS_IN_RAM
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movl z_loapic_regs, %edx
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movl Z_TOPLEVEL_RAM_NAME(LOAPIC_REGS_STR), %edx
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movl %eax, LOAPIC_EOI(%edx)
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#else
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movl %eax, (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
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movl %eax, (LOAPIC_BASE_ADDRESS + LOAPIC_EOI)
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#endif /* DEVICE_MMIO_IS_IN_RAM */
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#endif /* CONFIG_X2APIC */
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@ -2,6 +2,7 @@
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* Copyright (c) 2019 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define LOAPIC_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(intc_loapic))
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#include <zephyr/toolchain.h>
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#include <zephyr/arch/x86/multiboot.h>
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@ -142,7 +143,7 @@ x86_ap_start:
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* so we can locate our x86_cpuboot[] bundle. Put it in EBP.
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*/
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movl CONFIG_LOAPIC_BASE_ADDRESS+LOAPIC_ID, %eax
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movl LOAPIC_BASE_ADDRESS+LOAPIC_ID, %eax
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shrl $24, %eax
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andl $0x0F, %eax /* local APIC ID -> EAX */
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@ -810,7 +811,7 @@ irq_dispatch:
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movl $(X86_X2APIC_BASE_MSR + (LOAPIC_EOI >> 4)), %ecx
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wrmsr
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#else /* xAPIC */
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movq z_loapic_regs, %rdx
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movq Z_TOPLEVEL_RAM_NAME(LOAPIC_REGS_STR), %rdx
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movl %eax, LOAPIC_EOI(%rdx)
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#endif /* CONFIG_X2APIC */
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@ -9,12 +9,6 @@ menuconfig LOAPIC
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if LOAPIC
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config LOAPIC_BASE_ADDRESS
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hex "Local APIC Base Address"
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default 0xFEE00000
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help
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This option specifies the base address of the Local APIC device.
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config X2APIC
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bool "Access local APIC in x2APIC mode"
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help
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@ -3,6 +3,9 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT intel_loapic
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/*
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* driver for x86 CPU local APIC (as an interrupt controller)
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*/
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@ -59,18 +62,15 @@
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#define LOAPIC_SPURIOUS_VECTOR_ID CONFIG_LOAPIC_SPURIOUS_VECTOR_ID
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#endif
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#define LOPIC_SSPND_BITS_PER_IRQ 1 /* Just the one for enable disable*/
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#define LOPIC_SUSPEND_BITS_REQD (ROUND_UP((LOAPIC_IRQ_COUNT * LOPIC_SSPND_BITS_PER_IRQ), 32))
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#define LOAPIC_SSPND_BITS_PER_IRQ 1 /* Just the one for enable disable*/
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#define LOAPIC_SUSPEND_BITS_REQD (ROUND_UP((LOAPIC_IRQ_COUNT * LOAPIC_SSPND_BITS_PER_IRQ), 32))
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#ifdef CONFIG_PM_DEVICE
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#include <zephyr/pm/device.h>
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__pinned_bss
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uint32_t loapic_suspend_buf[LOPIC_SUSPEND_BITS_REQD / 32] = {0};
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uint32_t loapic_suspend_buf[LOAPIC_SUSPEND_BITS_REQD / 32] = {0};
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#endif
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#ifdef DEVICE_MMIO_IS_IN_RAM
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__pinned_bss
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mm_reg_t z_loapic_regs;
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#endif
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DEVICE_MMIO_TOPLEVEL(LOAPIC_REGS_STR, DT_DRV_INST(0));
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__pinned_func
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void send_eoi(void)
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@ -87,11 +87,8 @@ __pinned_func
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void z_loapic_enable(unsigned char cpu_number)
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{
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int32_t loApicMaxLvt; /* local APIC Max LVT */
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DEVICE_MMIO_TOPLEVEL_MAP(LOAPIC_REGS_STR, K_MEM_CACHE_NONE);
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#ifdef DEVICE_MMIO_IS_IN_RAM
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device_map(&z_loapic_regs, CONFIG_LOAPIC_BASE_ADDRESS, 0x1000,
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K_MEM_CACHE_NONE);
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#endif /* DEVICE_MMIO_IS_IN_RAM */
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#ifndef CONFIG_X2APIC
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/*
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* in xAPIC and flat model, bits 24-31 in LDR (Logical APIC ID) are
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@ -340,7 +337,7 @@ static int loapic_suspend(const struct device *port)
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ARG_UNUSED(port);
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(void)memset(loapic_suspend_buf, 0, (LOPIC_SUSPEND_BITS_REQD >> 3));
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(void)memset(loapic_suspend_buf, 0, (LOAPIC_SUSPEND_BITS_REQD >> 3));
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for (loapic_irq = 0; loapic_irq < LOAPIC_IRQ_COUNT; loapic_irq++) {
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17
dts/bindings/interrupt-controller/intel,loapic.yaml
Normal file
17
dts/bindings/interrupt-controller/intel,loapic.yaml
Normal file
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@ -0,0 +1,17 @@
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description: Local Advanced Programmable Interrupt Controller (APIC)
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compatible: "intel,loapic"
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include: [interrupt-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#interrupt-cells":
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const: 3
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interrupt-cells:
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- irq
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- sense
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- priority
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@ -37,6 +37,14 @@
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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pcie0: pcie0 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -36,6 +36,14 @@
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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pcie0: pcie0 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -32,6 +32,13 @@
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#interrupt-cells = <3>;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -41,6 +41,14 @@
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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pcie0: pcie0 {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -29,6 +29,14 @@
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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dram0: memory@0 {
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device_type = "memory";
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reg = <DT_DRAM_BASE DT_DRAM_SIZE>;
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@ -60,6 +60,14 @@
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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sram: memory@ff200000 {
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device_type = "memory";
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compatible = "mmio-sram";
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#interrupt-cells = <3>;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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/*
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* Platforms with Lakemont SoC can have different hardware
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* configurations. So RAM and peripherals need to be
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interrupt-controller;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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#address-cells = <1>;
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};
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pcie0: pcie0 {
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#address-cells = <1>;
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#size-cells = <1>;
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#define LOAPIC_LVT_MASKED 0x00010000 /* mask */
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/* Defined in intc_loapic.c */
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#define LOAPIC_REGS_STR loapic_regs /* mmio device name */
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#ifndef _ASMLANGUAGE
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#ifdef __cplusplus
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extern "C" {
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#endif
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DEVICE_MMIO_TOPLEVEL_DECLARE(LOAPIC_REGS_STR);
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extern uint32_t z_loapic_irq_base(void);
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extern void z_loapic_enable(unsigned char cpu_number);
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extern void z_loapic_int_vec_set(unsigned int irq, unsigned int vector);
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return z_x86_msr_read(X86_X2APIC_BASE_MSR + reg);
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}
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/* Defined in intc_loapic.c */
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#ifdef DEVICE_MMIO_IS_IN_RAM
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extern mm_reg_t z_loapic_regs;
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#endif
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/**
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* @brief Read 32-bit value from the local APIC in xAPIC (MMIO) mode.
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*
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static inline uint32_t x86_read_xapic(unsigned int reg)
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{
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mm_reg_t base;
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#ifdef DEVICE_MMIO_IS_IN_RAM
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base = z_loapic_regs;
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#else
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base = CONFIG_LOAPIC_BASE_ADDRESS;
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#endif
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base = DEVICE_MMIO_TOPLEVEL_GET(LOAPIC_REGS_STR);
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return sys_read32(base + reg);
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}
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static inline void x86_write_xapic(unsigned int reg, uint32_t val)
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{
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mm_reg_t base;
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#ifdef DEVICE_MMIO_IS_IN_RAM
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base = z_loapic_regs;
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#else
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base = CONFIG_LOAPIC_BASE_ADDRESS;
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#endif
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base = DEVICE_MMIO_TOPLEVEL_GET(LOAPIC_REGS_STR);
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sys_write32(val, base + reg);
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}
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