michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: mr_canhubk3: enable flash controller for QSPI

Browse source 
This board has a MX25L6433F memory connected to the only QSPI port
available in S32K344.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is contained in:
Manuel Argüelles 2023-07-07 13:31:58 -03:00 • committed by Carles Cufí
commit 3cc1c41f41
4 changed files with 72 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

8
boards/arm/mr_canhubk3/doc/index.rst
View file

@ -49,6 +49,7 @@ SIUL2 on-chip | pinctrl
| gpio
| external interrupt controller
LPUART on-chip serial
QSPI on-chip flash
============ ========== ================================
The default configuration can be found in the Kconfig file
@ -119,6 +120,13 @@ the watchdog so the FS26 must be started in debug mode following these steps:
3. Power on the board.
4. Reconnect the jumper ``JP1`` (pins 1-2 shorted).
External Flash
==============
The on-board MX25L6433F 64M-bit multi-I/O Serial NOR Flash memory is connected
to the QSPI controller port A1. This board configuration selects it as the
default flash controller.
Programming and Debugging
*************************

20
boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi
View file

@ -90,4 +90,24 @@
input-enable;
};
};
qspi0_default: qspi0_default {
group1 {
pinmux = <(PTD11_QUADSPI_IOFA0_O | PTD11_QUADSPI_IOFA0_I)>,
<(PTD7_QUADSPI_IOFA1_O | PTD7_QUADSPI_IOFA1_I)>,
<(PTD12_QUADSPI_IOFA2_O | PTD12_QUADSPI_IOFA2_I)>,
<(PTC2_QUADSPI_IOFA3_O | PTC2_QUADSPI_IOFA3_I)>;
output-enable;
input-enable;
};
group2 {
pinmux = <PTD10_QUADSPI_SCKFA_O>;
output-enable;
};
group3 {
pinmux = <PTC3_QUADSPI_PCSFA>;
output-enable;
bias-pull-up;
};
};
};

36
boards/arm/mr_canhubk3/mr_canhubk3.dts
View file

@ -21,6 +21,7 @@
zephyr,code-partition = &code_partition;
zephyr,console = &lpuart2;
zephyr,shell-uart = &lpuart2;
zephyr,flash-controller = &mx25l6433f;
};
aliases {
@ -132,3 +133,38 @@
pinctrl-0 = <&lpuart14_default>;
pinctrl-names = "default";
};
&qspi0 {
pinctrl-0 = <&qspi0_default>;
pinctrl-names = "default";
data-rate = "SDR";
a-rx-clock-source = "LOOPBACK";
a-dll-mode = "BYPASSED";
ahb-buffers-masters = <0 1 2 3>;
ahb-buffers-sizes = <0 0 0 256>;
ahb-buffers-all-masters;
status = "okay";
mx25l6433f: mx25l6433f@0 {
compatible = "nxp,s32-qspi-nor";
reg = <0>;
size = <DT_SIZE_M(64)>;
jedec-id = [c2 20 17];
quad-enable-requirements = "S1B6";
readoc = "1-4-4";
writeoc = "1-4-4";
has-32k-erase;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x0 0x100000>;
};
};
};
};

8
dts/arm/nxp/nxp_s32k344_m7.dtsi
View file

@ -415,6 +415,14 @@
clocks = <&clock NXP_S32_LPUART15_CLK>;
status = "disabled";
};
qspi0: qspi@404cc000 {
compatible = "nxp,s32-qspi";
reg = <0x404cc000 0x4000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
};