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dts: x86: intel: alder_lake: Added GPIO instances

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Added GPIO instances supported on Alderlake platform

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This commit is contained in:
Anisetti Avinash Krishna 2023-08-22 16:04:24 +05:30 • committed by Carles Cufí
commit 2e219f3697
1 changed files with 162 additions and 0 deletions
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162
dts/x86/intel/alder_lake.dtsi
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@ -8,6 +8,7 @@
#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pcie/pcie.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
/ {
cpus {
@ -110,6 +111,167 @@
status = "okay";
};
gpio_0_b: gpio@fd6e0700 {
compatible = "intel,gpio";
reg = <0xfd6e0700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <0>;
status = "okay";
};
gpio_0_a: gpio@fd6e09a0 {
compatible = "intel,gpio";
reg = <0xfd6e09a0 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <41>;
status = "okay";
};
gpio_1_s: gpio@fd6d0700 {
compatible = "intel,gpio";
reg = <0xfd6d0700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
pin-offset = <0>;
status = "okay";
};
gpio_1_i: gpio@fd6d0780 {
compatible = "intel,gpio";
reg = <0xfd6d0780 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <19>;
pin-offset = <8>;
status = "okay";
};
gpio_1_h: gpio@fd6d08c0 {
compatible = "intel,gpio";
reg = <0xfd6d08c0 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x2>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <25>;
status = "okay";
};
gpio_1_d: gpio@fd6d0a40 {
compatible = "intel,gpio";
reg = <0xfd6d0a40 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <20>;
pin-offset = <49>;
status = "okay";
};
gpio_4_c: gpio@fd6a0700 {
compatible = "intel,gpio";
reg = <0xfd6a0700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
pin-offset = <0>;
status = "okay";
};
gpio_4_f: gpio@fd6a0880 {
compatible = "intel,gpio";
reg = <0xfd6a0880 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x1>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <24>;
status = "okay";
};
gpio_4_e: gpio@fd6a0a70 {
compatible = "intel,gpio";
reg = <0xfd6a0a70 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x3>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
pin-offset = <57>;
status = "okay";
};
gpio_5_r: gpio@fd690700 {
compatible = "intel,gpio";
reg = <0xfd690700 0x1000>;
interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
group-index = <0x0>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
pin-offset = <0>;
status = "okay";
};
hpet: hpet@fed00000 {
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;