drivers: spi: Add Ambiq SPI driver
This commits adds SPI master driver for Apollo4 SoCs. Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
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7 changed files with 282 additions and 1 deletions
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@ -41,6 +41,7 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PW spi_pw.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_SMARTBOND spi_smartbond.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_OPENTITAN spi_opentitan.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_NUMAKER spi_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ spi_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_RTIO spi_rtio.c)
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zephyr_library_sources_ifdef(CONFIG_SPI_ASYNC spi_signal.c)
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@ -129,4 +129,6 @@ source "drivers/spi/Kconfig.opentitan"
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source "drivers/spi/Kconfig.numaker"
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source "drivers/spi/Kconfig.ambiq"
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endif # SPI
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15
drivers/spi/Kconfig.ambiq
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15
drivers/spi/Kconfig.ambiq
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@ -0,0 +1,15 @@
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# Ambiq SDK SPI
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#
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SPI_AMBIQ
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bool "AMBIQ SPI driver"
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default y
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depends on DT_HAS_AMBIQ_SPI_ENABLED
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select AMBIQ_HAL
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select AMBIQ_HAL_USE_SPI
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help
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Enable driver for Ambiq SPI.
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237
drivers/spi/spi_ambiq.c
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237
drivers/spi/spi_ambiq.c
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@ -0,0 +1,237 @@
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ambiq_spi
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(spi_ambiq);
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#include <zephyr/drivers/spi.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/byteorder.h>
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#include <stdlib.h>
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#include <errno.h>
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#include "spi_context.h"
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#include <am_mcu_apollo.h>
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#define PWRCTRL_MAX_WAIT_US 5
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typedef int (*ambiq_spi_pwr_func_t)(void);
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struct spi_ambiq_config {
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uint32_t base;
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int size;
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uint32_t clock_freq;
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const struct pinctrl_dev_config *pcfg;
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ambiq_spi_pwr_func_t pwr_func;
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};
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struct spi_ambiq_data {
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struct spi_context ctx;
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am_hal_iom_config_t iom_cfg;
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void *IOMHandle;
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};
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#define SPI_BASE (((const struct spi_ambiq_config *)(dev)->config)->base)
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#define REG_STAT 0x248
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#define IDLE_STAT 0x4
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#define SPI_STAT(dev) (SPI_BASE + REG_STAT)
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#define SPI_WORD_SIZE 8
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static int spi_config(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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data->iom_cfg.eInterfaceMode = AM_HAL_IOM_SPI_MODE;
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int ret = 0;
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if (config->operation & SPI_HALF_DUPLEX) {
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LOG_ERR("Half-duplex not supported");
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return -ENOTSUP;
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}
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if (SPI_WORD_SIZE_GET(config->operation) != 8) {
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LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
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return -ENOTSUP;
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}
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if ((config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
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LOG_ERR("Only supports single mode");
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return -ENOTSUP;
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}
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if (config->operation & SPI_LOCK_ON) {
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LOG_ERR("Lock On not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_TRANSFER_LSB) {
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LOG_ERR("LSB first not supported");
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return -ENOTSUP;
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}
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if (config->operation & (SPI_MODE_CPOL | SPI_MODE_CPHA)) {
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if (config->operation & (SPI_MODE_CPOL && SPI_MODE_CPHA)) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_3;
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} else if (config->operation & SPI_MODE_CPOL) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_2;
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} else if (config->operation & SPI_MODE_CPHA) {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_1;
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} else {
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data->iom_cfg.eSpiMode = AM_HAL_IOM_SPI_MODE_0;
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}
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}
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if (config->operation & SPI_OP_MODE_SLAVE) {
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LOG_ERR("Slave mode not supported");
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return -ENOTSUP;
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}
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if (config->operation & SPI_MODE_LOOP) {
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LOG_ERR("Loopback mode not supported");
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return -ENOTSUP;
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}
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if (cfg->clock_freq > AM_HAL_IOM_MAX_FREQ) {
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LOG_ERR("Clock frequency too high");
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return -ENOTSUP;
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}
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data->iom_cfg.ui32ClockFreq = cfg->clock_freq;
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/* Disable IOM instance as it cannot be configured when enabled*/
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ret = am_hal_iom_disable(data->IOMHandle);
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ret = am_hal_iom_configure(data->IOMHandle, &data->iom_cfg);
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ret = am_hal_iom_enable(data->IOMHandle);
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return ret;
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}
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static int spi_ambiq_xfer(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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struct spi_context *ctx = &data->ctx;
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int ret = 0;
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am_hal_iom_transfer_t trans = {0};
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uint8_t *buf3;
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trans.eDirection = AM_HAL_IOM_FULLDUPLEX;
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uint16_t cmd = *ctx->tx_buf;
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trans.ui32InstrLen = ctx->tx_len;
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spi_context_update_tx(ctx, 1, 1);
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cmd = __bswap_16(cmd | *ctx->tx_buf << 8);
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trans.ui64Instr = cmd;
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if (ctx->rx_buf != NULL) {
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trans.pui32TxBuffer = (uint32_t *)ctx->tx_buf;
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spi_context_update_rx(ctx, 1, ctx->rx_len);
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buf3 = (uint8_t *)malloc(sizeof(uint8_t) * ctx->rx_len);
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trans.ui32NumBytes = ctx->rx_len;
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trans.pui32RxBuffer = (uint32_t *)&buf3;
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ret = am_hal_iom_spi_blocking_fullduplex(data->IOMHandle, &trans);
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memcpy(ctx->rx_buf, &buf3, (ctx->rx_len * sizeof(uint8_t)));
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} else if (ctx->tx_buf != NULL) {
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spi_context_update_tx(ctx, 1, 1);
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trans.ui32NumBytes = ctx->tx_len;
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trans.pui32TxBuffer = (uint32_t *)ctx->tx_buf;
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trans.pui32RxBuffer = (uint32_t *)ctx->tx_buf;
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ret = am_hal_iom_spi_blocking_fullduplex(data->IOMHandle, &trans);
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}
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spi_context_complete(ctx, dev, 0);
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return ret;
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}
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static int spi_ambiq_transceive(const struct device *dev, const struct spi_config *config,
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const struct spi_buf_set *tx_bufs,
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const struct spi_buf_set *rx_bufs)
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{
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struct spi_ambiq_data *data = dev->data;
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int ret;
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ret = spi_config(dev, config);
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if (ret) {
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return ret;
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}
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if (!tx_bufs && !rx_bufs) {
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return 0;
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}
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spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
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ret = spi_ambiq_xfer(dev, config);
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return ret;
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}
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static int spi_ambiq_release(const struct device *dev, const struct spi_config *config)
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{
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struct spi_ambiq_data *data = dev->data;
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if (!sys_read32(SPI_STAT(dev))) {
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return -EBUSY;
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}
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spi_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static struct spi_driver_api spi_ambiq_driver_api = {
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.transceive = spi_ambiq_transceive,
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.release = spi_ambiq_release,
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};
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static int spi_ambiq_init(const struct device *dev)
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{
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struct spi_ambiq_data *data = dev->data;
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const struct spi_ambiq_config *cfg = dev->config;
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int ret;
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ret = am_hal_iom_initialize((cfg->base - REG_IOM_BASEADDR) / cfg->size, &data->IOMHandle);
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ret = cfg->pwr_func();
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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return ret;
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}
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#define AMBIQ_SPI_INIT(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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static int pwr_on_ambiq_spi_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(PWRCTRL_MAX_WAIT_US); \
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return 0; \
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} \
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static struct spi_ambiq_data spi_ambiq_data##n = { \
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SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx), \
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SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx)}; \
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static const struct spi_ambiq_config spi_ambiq_config##n = { \
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.base = DT_INST_REG_ADDR(n), \
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.size = DT_INST_REG_SIZE(n), \
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.clock_freq = DT_INST_PROP(n, clock_frequency), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.pwr_func = pwr_on_ambiq_spi_##n}; \
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DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, NULL, &spi_ambiq_data##n, &spi_ambiq_config##n, \
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POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_ambiq_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SPI_INIT)
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21
dts/bindings/spi/ambiq,spi.yaml
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21
dts/bindings/spi/ambiq,spi.yaml
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Ambiq SPI
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compatible: "ambiq,spi"
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include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clock-frequency:
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required: true
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ambiq,pwrcfg:
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required: true
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@ -35,4 +35,9 @@ config AMBIQ_HAL_USE_I2C
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help
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Use the I2C driver from Ambiq HAL
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config AMBIQ_HAL_USE_SPI
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bool
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help
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Use the SPI driver from Ambiq HAL
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endif # AMBIQ_HAL
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2
west.yml
2
west.yml
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@ -142,7 +142,7 @@ manifest:
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groups:
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- hal
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- name: hal_ambiq
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revision: 446736a1c36199d1c8b9b2c4b3d14bf27006d440
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revision: fbb1618df8b0946cc2abea817309dc85fe051c21
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path: modules/hal/ambiq
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groups:
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- hal
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