The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
This commit adds layput page cells to the atmel sam flash
controller and the flash node. These allow for describing
the actual flash page layout of each soc, allowing the
flash driver to fully utilize the capabilities of the
flash.
With this update, we unlock the following capabilties:
- utilize 2048 erase block size for small sectors
- utilize 16384 erase block size for large sectors
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
The max size was determined by looking at the ARCH of the cpu. This really
comes from the ip configuration when generated. Add `max-xfer-size`
property to the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Add definition of the DMIC to the RT5xx devicetree, including all
PDM channels.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Since the pins of bt-spi instance are wired internally in the chip, it will
make sense to move the definition to soc dts so no need for every board
using the chip to redefine the same.
Signed-off-by: Aaron Ye <aye@ambiq.com>
A 1KHz counter is present in the LPC RTC.
Add support for this counter to get better
resolution for certain applications.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Consistently use "int0" and "int1" as interrupt names for CAN controllers
based on the Bosch M_CAN IP core. This aligns with the upstream Linux
bindings.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This is in preparation for xmc4xxx mdio/ethernet patch set. In the
ethernet drivers, the DMA memory (including descriptor and buffers)
must live in dsram1 or dsram2.
Currently, in xmc47_relax_kit the RAM is the psram1 region meaning
that DMA transfers will not work. Switch to using dsram regions instead.
Also, merge dsram1 and dsram2 into a single region since they are
contiguous.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
The sci devices described in the device tree source for RA MCUs are
incorrectly specified as being UARTs when they should be SCIs (serial
communication interfaces) which can not only operate as UARTs but also
as I2C, SPI etc.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
This commit modifies the I2S driver to work for STM32H7
family of MCU's. Currently only TX is working.
Tested on nucleo_stm32h743zi. Requires dma1 & dmamux1 to be enabled.
Signed-off-by: Emil Lindqvist <emil@lindq.gr>
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.
Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present
This commit also updates the NXP HAL to include pin control files for
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Declare the SRAM0 region as memory-region
for the stm32f745 serie. Will be included for the stm32f746
for the stm32f765 serie. Will be included for the stm32f767
for the stm32f722 serie. Will be included for the stm32f723
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit updates the Ambiq Apollo4x series soc clock frequency
of defined instances to align with context of these dts files.
Signed-off-by: Aaron Ye <aye@ambiq.com>
We might have to do this differently:
Configure rng default clock in .dtsi
Set board specific config in .dts
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SRAM6 is used by RF and should be defined as RAM_NOCACHE
to allow unaligned access reads.
"IO" might be a better match but is not available on this arch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Add SMBus devices to all SoCs which have either
a st,stm32-i2c-v1 or st,stm32-i2c-v2.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The commit fixes the SHA driver because the ROM API has the following
changes from ES to QS chip:
1. base addres: from 0x13c -> 0x148
2. required SHA context buffer size : from 228 -> 240 bytes
This change also adds a check for the pre-allocated buffer size of the
SHA context when the driver initiliazes.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add `compatible` node to Ambiq SoCs, along with secondary common compat,
since they share many similarities.
Signed-off-by: Mateusz Karlic <mkarlic@antmicro.com>
Add code to configure and program Lcu, Trgmux and Emios_Icu IPs to
get the the rotations by the motor in radians.
Co-authored-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Co-authored-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Based on stm32wba55, stm32wba55Xg is similar from device tree description
to stm32wba52Xg.
Take the opportunity to fix stm32wba52Xg descriuption scheme which was
missing stm32wba52.dtsi.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Fixes an issue with the register addresses which was caused by a
missing `ranges;` option for the power peripheral
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This PR set the correct value for the stm32F7 devices.
And change vrefint-cal-addr to <0x1FF07A2A> for stm32F722-F723
soc serie.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use the "ambiq,gpio" binding to combine the "ambiq,gpio-bank"
child nodes for Apollo4 Plus soc.
Also update the GPIO driver accordingly.
Signed-off-by: Aaron Ye <aye@ambiq.com>
This removes all occurrences of arm,num-mpu-regions relying on the value
reported by the register instead.
A user may still define this property if they need to have a compile time
definition for it.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Although the RT1015 only supports 128 KB of FlexRAM being used at once, the
default fusemap overallocates 160KB of FlexRAM. The JLink flashloader
algorithm appears to rely on the 64KB of DTCM in the default fusemap
being configured. Reducing the DTCM allocation resulted in JLink
failing to flash the SOC.
To resolve this, utilize the default fusemap of {O, O, D, D, I} for the
RT1015 FlexRAM setup. Add a note about the restrictions on using
overallocated FlexRAM to the SOC DTSI.
Fixes#65889
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
The number of IRQ priority bits was incorrectly set to 3 instead
of 2, which is the correct number for Cortex-M0+.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
After porting from h5 to f7 i noticed that not all mcus have
cpu node labels. Added cpu0 node labels to all stm32 dts.
Signed-off-by: Kacper Dalach <dalachowsky@gmail.com>
r8a779f0 is also know as S4, this SoC is part of the Gen4 SoC series,
has 8 Cortex-A55 and a dual core lockstep Cortex-R52 processor.
SCIF0 is dedicated to Zephyr and SCIF3 to Linux.
**Control Domains**
IMPORTANT: This SoC is divided into two "domains":
- Application domain contains some peripherals as well as A55 & R52 cores.
- Control domain that contain a G4MH/RH850 MCU and other peripherals.
In order to access control domain peripherals such as gpio4-7 and CAN-FD
from application domain, the G4MH MCU has to unlock a protection
mechanism from control domain buses.
"Protected" controllers will be flagged in gen4 device trees,
warning users that they need to flash a custom G4MH firmware
to unlock access to these controllers.
**Clock controller**
This SoC clock controller is offering "domains"
for each world (Zephyr/Linux).
These domains are several "entry points" to the clock controller
which are arbitrated to avoid a world from turning off a clock needed
by another one.
We decided to use the same domain as Linux because the
security mechanism as to be implemented before accessing
another domain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The shi module in npcx4 supports the enhanced buffer mode.
Add a new compatible string "nuvoton,npcx-shi-enhanced" for it.
Then the shi driver can determine if it should use the enhanced buffer
mode based on the compatiable string.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This add regulator driver for Smartbond DA1469X SOC.
Driver can control VDD, V14, V18, V18P, V30 rails,
full voltage range supported by SOC is covered.
For VDD, V14, V18, V18P DCDC can be configured.
Special VDD_CLAMP (always on) and VDD_SLEPP are added
to allow configuration of VDD in sleep modes.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Only RTC can be used as the idle timer for cortex-m systick. Set the
chosen node as RTC by default.
The idle timer will be enabled only if PM management is set.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
Rather than configuring in serial_wakeup sample, define LPUART1 wakeup
line in wl.dtsi file.
Additionally make few cosmetic changes to nucleo_wl55rj overlay in
serial wakeup sample.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
On STM32WL, the backup memory is defined as part of the TAMP peripheral.
This seems to be a deviation from the stm32 family where this memory is
defined as part of the RTC.
The STM32WL reference manual shows that tamp_pclk is connected to
rtc_pclk. This means that the clock required to run the TAMP peripheral
is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved
by instanciating the bbram device as a child of the RTC and by modifying
the address offset to the first backup register from the rtc base
address.
Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
This commit moves configuration of hfxo from headers defined on board level
to device trees of SoCs.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Add Verdin iMX8M Plus board with i.MX8MP SoC and ARM Cortex-M7 processor.
Add two targets (DDR and ITCM) for the iMX8M Plus board.
Port and documentation are based on NXP MIMX8MM EVK board.
This code is intented to be used with the Cortex-M7.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add support for UART1 usage by adding uart1 node and configuration
to the i.MX 8ML devicetree include.
Signed-off-by: Gabriel Freitas <gabriel.freitas@toradex.com>
Add Renesas rzt2m gpio driver with basic functionality.
It supports pin mode configuration and writing/reading to/from gpio ports.
Includes dts changes to build blinky sample.
Signed-off-by: Jakub Michalski <jmichalski@internships.antmicro.com>
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a UART driver for the Renesas RZ/T2M
Serial Communication Interface.
The driver implements:
* Polling API,
* Interrupt-driven API.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
Enable NXP FlexRAM in DTS and SOC code.
Do not configure flexram at runtime if the code is in the RAM.
Fix RT1060 DT to be more accurate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The M4F subsystem has a dedicated GPIO controller with 24 available
pins. Add the node definition for the recently added driver.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Initialize the MDIO peripheral clock (normally done during GMAC
initialization) before trying any MDIO transfers, preventing startup
errors.
Signed-off-by: Nick Kraus <nick@nckraus.com>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This device lost the reg property since 88c9d1fbaf, causing the
nucleo_l011k4 board to not build anymore. Add it back, 512 bytes should
be the right number for this chip.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added initial version of Infineon CAT1 SDHC/SDIO driver
Added initial version of binding file for Infineon CAT1 SDHC/SDIO
driver
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
The variants of this family have different sizes of eeprom. This moves
eeprom definition from common family definition to device specific.
Signed-off-by: Gerson Fernando Budke <gerson.budke@ossystems.com.br>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adding initial support for Renesas RA UART.
To avoid complicating initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA GPIO.
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
The header file defines macros that are not used in the boards dts but on
the SoC level. They should be include where they are used.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
for nucleo_stm32g0b1 board.
the HSI48 clock is the clock used by default for the USB controller,
however its default tolerance is not enough for the USB specification,
leading to some random errors depending on many factors, including the
upstream HUB or host.
this commit adds an option in the device tree to enable the STM32 Clock
recovery system (CRS) using USB SOF packet reception as a reference,
which brings the HSI48 within the required accuracy for USB transfers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
Refactor the pinctrl nodes slightly so that the port devices are not
child of the main pinctrl node. This is because the pinctrl node is
being used as parent for pinctrl setting nodes itself, and having the
port nodes as child end up creating a circular depdency with the edt
child enumeration patch.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This files has been changed as part of a refactoring in 13a87081b9.
Unfortunately the refactoring introduced few issues:
- usage of devicetree macros before their definition
- usage of pinctrl label before the definition of the corresponding node
- removal of few node overrides that are causing build errors
Unfortunately there's no board usptream using this specific dts file, so
the issue has not been caught in CI and was only found downstream.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This commit adds the RTC device to the following
atmel sam devicetrees:
- sam3x.dtsi
- sam4e.dtsi
- sam4s.dtsi
- same70.dtsi
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
STM32WB MCUs has two AES peripeherals. Add AES1 definition, AES2 must not
be used by application CPU core.
Signed-off-by: Lukasz Hawrylko <lukasz@hawrylko.pl>
Use a new property, "clock-mux" to select the clock mux for the SAI.
Previously, the clock mux was being selected using the "bits" specifier
of the "clocks" phandle property, which is not the purpose of this
specifier. This can be shown by the regression introduced by 5bebbb91,
which changed the "bits" field to the clock gate shift (which is the
intended meaning).
This incidently worked for the SAI1 and SAI3 peripherals, as the lower 2
bits of the correct clock source selection (0b10) are the same as the new
value placed in the "bit" specifier. For SAI2, the clock source was
switched to PLL3 PDF0 by this change.
To resolve this, use an explict "clock-mux" property for this selection.
Fixes#63541
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
MEC172X series SoCs share most IP but the -LJ series expands the PWM and
ADC channels available as well as defines extra pinctrl pins.
Separating these better to be able to simplify their inclusion and
driver code. Any board based on either the -SZ or -LJ package can just
include the mec172x<sz/lj> dtsi files for their specific package.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Define WKPU interrupt controller node and its respective interrupt
sources mapping to GPIO pins.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The pre-alloacted size of the buffer for the SHA ROM API code increases
in npcx4 chip. This commit adds a new property context-buffer-size to
sha0 DT node in npcx9 and npcx4 separately. The driver can pre-allocate
buffer with the correct size based on the property.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Different nRF52 devices have different maximum TWI DMA transfer size,
and it's easy to hit the limit with i2c displays on nrf52832 (8 bit) and
nrf52810 (10 bit). Currently neither the driver or the hal validate the
limit, leading to random NACK errors when trying to transfer more data.
Add a check on the driver to fail gracefully when going over the limit.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added pinctrl nodes for Silabs SoCs where they were missing:
efm32pg, efm32hg, efm32wg, efr32mg21.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Use clock control API to retrieve the counter module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This introduces pwm capture shim driver for NXP S32 EMIOS,
the driver uses SAIC mode that is supported for all channels,
to capture the counter value on each edge for period/pulse
measurement
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This prepares support pwm capture APIs by extended current pwm
shim driver but use a differrence hal component:
- Introduce a Kconfig options that will be set when PWM pulse
generation API is used, it is also used to select the hal
component. Guarding current code inside this Kconfig option
- Increase #pwm-cells to 3, flags is supported for PWM capture
- Do not require duty-cycle and polarity be set in dt, PWM
capture doesn't need it.
- Rename emum value for pwm-mode to keep only key information
- Add preprocessor in case no channel is configured for generate
PWM output, to avoid warning when build
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This enables and declares interrupt handlers for eMIOS,
the handlers defined and implemented at HAL, the driver
takes the name for each id from interrupt-names devicetree
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add "st,stm32-flash-controller" as compatible for STM32H7 so that
what is defined for STM32 in general is also defined for STM32H7.
Already most of the other STM32 versions have this addition.
Also removed the specific STM32H7 flag check in
/flash/driver/Kconfig.stm32.
Signed-off-by: Stefan Petersen <spe@ciellt.se>
Updates Ethernet PHY devicetree bindings to be more consistent with
Linux by using the standard `reg` property for the PHY address instead
of a custom `address` property. As a result, MDIO controller bindings
now require standard `#address-cells` and `#size-cells` properties.
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Provide the soc configuration for sdmmc1 and sdmmc2 controllers.
This includes registers address, clocks, resets and interrupt line
details.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Update the descriptions for the various CAN devicetree timing properties
specified in Time Quanta (TQ) to make it clear that these, if present, are
only used for the initial timing parameters.
Deprecate the (Re-)Synchronization Jump Width (SJW) devicetree properties
for both arbitration and data phase timing as these are now only used in
combination with the other TQ-based CAN timing properties, which are all
deprecated.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.
For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk
Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
The current implementation iterates over all channels
even if only several channels share the same irq. This
introduces one more dt property to describe an offset
between two channels share the same interrupt id.
Beside that, the error interrupt must be put as last
element of "interrupt" dt property.
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The PIT maximum load value may not be always 32-bit. Allow the SoC to
define this value from devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Remove temp-, vref- and vbat-channel from STM32 ADC nodes as it is not
used in the driver anymore.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add phandle prop to reference any regulator that must
be enabled in order for the LPADC to function as intended.
Change LPADC driver to use this property if present.
LPADC on LPC55S36 depends on VREF peripheral, enable for this platform.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:
- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers
Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).
Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This platform (SOC_SERIES_EFM32PG1B) is also using SOC_GECKO_SERIES1 and
needs a pinctrl device defined to build the gecko-uart driver
successfully.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
The gecko UART driver needs pinctrl support for SOC_GECKO_SERIES1
devices, this has been added to jg and pg 12b series in 40fa96506b but
is missing in others, causing some build failurse.
Add the device nodes for the gg11b and gg12b files since they contain
gecko-uart references and seems to be under the SERIES1 define.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This creates separate dtsi files for the various memory density codes of
SAM X2xfamilies (they are the same where the specific size exists.)
All of the boards with the exclusion of EV11L78A use the same density
model of 18 (32KiB RAM and 256KiB flash) which is what the samd2x.dtsi
include specified for all of them previously.
The density code has been confirmed being the same across the D20/D21,
C20/C21, L21, and R21 families. This does not carry over to some other
series such as the E5x.
Signed-off-by: Diego Elio Pettenò <flameeyes@meta.com>
Add SRAM code region definition to RT6xx series SOC. The RT6xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SRAM code region definition to RT5xx series SOC. The RT5xx shares
SRAM partitions between the code and data bus, but a default allocation
is chosen by the SOC level devicetree. The user can modify this
allocation by changing the base address and size of the sram_code and
sram0 regions in their board devicetree.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit adds support for the ATMEL HSMCI peripheral
for the SAM4E MCU series, enabling native SD card support.
Signed-off-by: Vincent van Beveren <v.van.beveren@nikhef.nl>
While most of the ST family SoCs have the compatible string set, several
targets still miss it.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Add a MBOX driver wrapper around the NXP MU, simular to
the existing wrapper around the NXP S32 MRU. This allows Zephyr IPC
to work based on the MU, on a number of NXP boards.
Also update the SHA of NXP HAL to enable the Kconfig for this driver.
Signed-off-by: Yicheng Li <yichengli@google.com>
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
Compat strings in SoCs allow tools to identify hardware described in
flattened device trees.
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
This introduces PWM driver with supporting PWM output
APIs based on NXP S32 EMIOS peripheral. This supports
three mode: OPWFMB, OPWMCB and OPWMB.
OPWFMB uses internal counter, the new period and duty
cycle takes effect immediately.
OPWMCB and OPWMB use external counter as timebase, changing
PWM period at runtime will impact to all channels share the
same timebase. Also the new period and duty cycle take effect
in next period boundary of the timebase
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
This PR adds a misc driver for NXP S32 eMIOS peripheral.
eMIOS provides multiple unified channels (UCs), there are
several channels can be used as reference timebase
(master bus) for other channels. At this time, the
driver does initialize global configuration for eMIOS
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.
Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
Update SNVS pin names in RT11xx DTSI files to align with new pin data
generated for the RT1176 and RT1166 processors. This pin data is stored
within the NXP HAL, so the SHA of the HAL is also updated by this
commit.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Created a seperate device tree file for the stm32f765.
Moved common nodes from the stm32f767 device tree file to the new file and
based the stm32f767 off the stm32f765.
Signed-off-by: Rahul Arasikere <arasikere.rahul@gmail.com>
STM32L1, U5 and WBA can only have an asynchronous clock source for ADC.
STM32F2, F4 and F7 can only have a synchronous clock source for ADC.
For all these series, it can be defined directly in the dtsi files.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
This commit changes the I2C instance to IOM.
IOM instance can be I2C or SPI. The choice of either
using I2C or SPI should be made in board DTS.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
/delete-node/ pointing at node labels needs to be out of the the tree
hierarchy, fixes the error:
devicetree error: zephyr/dts/arm/nordic/nrf52840_qfaa.dtsi:24 (column
16): parse error: expected node name
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This adds QSPI controller properties that allow tuning
chip select timings (needed for accessing QSPI at high speed)
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
RC32K/RCX/XTAL32K were present in device tree as fixed-clock.
Now calibration time for RCX and RC32K is added and settle time
for XTAL32K so additional binding is created.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
To better delimit renesas ranges dts, we need to use ranges folder.
It will also help maintainers to better delimit their files to
be notified about.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Since VWGPSM (Virtual Wire GPIO Target-to-Controller) registers are
introduced in npcx9 and later series, the CL moves the related DT nodes
from npcx-espi-vws-map.dtsi (Used for all npcx series) to the specific
dtsi files for npcx9 and npcx4 series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Rename the base device-tree for the AM62x M4F from a SK EVM specific
to a more generic name since this DT describes the M4F subsystem in
the AM62x SoC.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
The existing i2c sda/slc pinctrl nodes serve as an input and output
for the USIC. This limits the number of pins that can be used for i2c
since the pin must be internally connected to both DOUT0 and DX0 signals
on the USIC (for the sda signal for example).
It is also possible to use separate pins to DOUT0 and DX0, but connect
the pins externally. Add these extra pinctrl nodes and document their
use in infineon,xmc4xxx-i2c.yaml.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In commit 541482ff20 the pinctrl alternate
function mask was increased to also include open-drain setting.
Revert this change because open-drain can already be set via property
drive-open-drain.
The commit also added separate pinctrl nodes for the i2c controller and
target modes. However, the alternate function settings
is the same in both modes, so keep only one and remove the mode
label.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Since the pwm_nrf_sw driver can now be used on all nRF SoCs, add its
corresponding DT node in the common file included by all those SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rename the STM32H7 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32H7 FDCAN
clock and pinctrl macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 FDCAN node labels to match to naming used in the ST
reference manuals. This also matches the naming used in the STM32 FDCAN
pinctrl macros.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 bxCAN driver DTS compatible, Kconfig symbol, and
implementation file to match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.
This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.
In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Enable CANFD for rt11xx by including nxp,flexcan-fd
compatibility for all CANFD capable CAN with associated
properties.
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This commit instantiates the counter peripheral.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst support for the system timer peripheral which
can be found in Apollo4 SoCs.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Devicetree specification v0.4, Section 2.3.1:
"The compatible string should consist only of lowercase letters, digits
and dashes, and should start with a letter."
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This state is never used in practice, even if handled by the PM
subsystem hooks. Shutdown-like states are always invoked manually, so
they don't need to be described in DT.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The `cpu-power-states` property needs to be defined at SoC dts files,
since it's a property of the SoC, not board.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
CPU idle states are not board specific. This patch moves Nuvoton idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves NXP idle states
to the core SoC dts files. Board can always tweak some state parameters
(if needed), but the definition belongs to core SoC dts files, same as
e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves Microchip MEC
idle states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves TI idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves STM32 idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Fixup support for DCS_LONG_WRITE command in DSI MCUX 2L driver. Since long
DCS commands may benefit from nonblocking I/O, add support for non blocking
transfers to the DSI driver.
This commit also corrects the interrupt number for the RT595, which uses
the DSI_MCUX_2L IP block.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Add Nuvoton numaker series flash memory controller(FMC) with erase,
read & write features of soc-flash. Also update Nuvoton manifest
to include zephyrproject-rtos/hal_nuvoton#6.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add the new RCC bindings to the dtsi files.
STM32F373 uses the RCC F1 bindings because the ADC prescaler is the same
on the two series.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Current erroneous usages of dma-channels prop by lpc-dma nodes:
* dma-channels devicetree property should describe the number of
channels supported by the dma controller, not the number of channels
in use.
* LPC55SXX and RTXXX SOCs should be setting dma channels prop at SOC
level, not board level, since it is an SOC property, not a board
property.
* lpc55s28 has 23 channels for dma0, not 20.
* lpc55s28 has 10 channels for dma1, not 0.
* lpc55s69 has 23 channels for dma0, not 20.
* rt5xx has 37 channels for dma1, not 0.
* rt6xx has 33 channels for dma0, not 20.
* rt6xx has 33 channels for dma1, not 0.
Fix all of these issues
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Set the DMA number of otrigs DT property at the SOC level instead of the
board DTS because it is an SOC property and does not change on different
boards.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add basic device tree description fro stm32wba soc series.
This includes Flash/RAM clocks and clock control nodes
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This change introduces the "_rtc_timer" suffix for the system tick timer
driver "compatible" property and aligns naming conventions with the
actual CC13/26xx SoC series product policy.
This frees up the "_rtc" namespace to introduce additional APIs based on
the same peripheral in the future (not part of this PR):
rtc: rtc@... {
compatible = "ti,cc13xx-cc26xx-rtc";
...
timer {
compatible = "ti,cc13xx-cc26xx-rtc-timer";
...
};
counter {
compatible = "ti,cc13xx-cc26xx-rtc-counter";
...
};
pps {
compatible = "ti,cc13xx-cc26xx-rtc-pps";
...
};
};
Or alternatively an MFD pattern with similar requirements.
Fixing the namespacing now makes sense standalone as it reduces the
chance of custom drivers being broken in the future.
Redundant extension of the mandatory system clock devicetree node is
replaced with a single `status = "okay"` which seems to be the more
sensible default to avoid user error when defining custom boards.
Knowledgeable users can still override this if really needed.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
The different references manuals of the STM32H7 family (RM099, RM0433,
RM0445 and RM0468) states that SDMMC2RTS and STMMC2EN are on bit 9 of
respectively RCC_AHB2RSTR and RCC_AHB2ENR (not on bit 8). Fixes the stm32h7
dts accordingly.
Signed-off-by: Johan Lafon <johan.lafon@syslinbit.com>
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.
Use the board's debug connector (P6 / LPUART2) as default console.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Support pin control for NXP S32K3 devices and enable it by default on
mr_canhubk3 board configuration.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
