soc: stm32g0: add fdcan2
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working with zephyr yet as both controllers shares the same IRQ. Recently, the shared irq system was integrated on now, both can controllers can work on this chip. Shared interrupts must be enabled only if both can controllers are enabled. Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
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@ -43,6 +43,19 @@
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status = "disabled";
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};
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fdcan2: can@40006800 {
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compatible = "st,stm32-fdcan";
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reg = <0x40006800 0x400>, <0x4000b750 0x350>;
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reg-names = "m_can", "message_ram";
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interrupts = <21 0>, <22 0>;
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interrupt-names = "int0", "int1";
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>;
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bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
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sample-point = <875>;
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sample-point-data = <875>;
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status = "disabled";
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};
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usart5: serial@40005000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40005000 0x400>;
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@ -11,4 +11,11 @@ config SOC
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config NUM_IRQS
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default 31
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if CAN_STM32_FDCAN
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config SHARED_INTERRUPTS
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default y if $(dt_nodelabel_enabled,fdcan1) && $(dt_nodelabel_enabled,fdcan2)
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endif # CAN_STM32_FDCAN
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endif # SOC_STM32G0B1XX
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