drivers: bbram: stm32-bbram: port to stm32wl
On STM32WL, the backup memory is defined as part of the TAMP peripheral. This seems to be a deviation from the stm32 family where this memory is defined as part of the RTC. The STM32WL reference manual shows that tamp_pclk is connected to rtc_pclk. This means that the clock required to run the TAMP peripheral is the same as the RTC's. A quick port of BBRAM on STM32WL is achieved by instanciating the bbram device as a child of the RTC and by modifying the address offset to the first backup register from the rtc base address. Signed-off-by: Adrien Bruant <adrien.bruant@aalberts-hfc.com>
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2 changed files with 20 additions and 1 deletions
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@ -14,7 +14,14 @@
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LOG_MODULE_REGISTER(bbram, CONFIG_BBRAM_LOG_LEVEL);
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#define STM32_BKP_REG_BYTES 4
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#define STM32_BKP_REG_OFFSET 0x50
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#ifdef TAMP
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/* If a SoC has a TAMP peripherals, then the backup registers are defined there,
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* not in the RTC.
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*/
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#define STM32_BKP_REG_OFFSET (TAMP_BASE + offsetof(TAMP_TypeDef, BKP0R) - RTC_BASE)
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#else
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#define STM32_BKP_REG_OFFSET offsetof(RTC_TypeDef, BKP0R)
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#endif
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#define STM32_BKP_REG_INDEX(offset) ((offset) >> 2)
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#define STM32_BKP_REG_BYTE_INDEX(offset) ((offset)&0x3UL)
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#define STM32_BKP_REG(i) (((volatile uint32_t *)config->base_addr)[(i)])
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@ -207,6 +207,18 @@
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
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prescaler = <32768>;
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status = "disabled";
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/* In STM32WL, the backup registers are defined as part of the TAMP
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* peripheral. This peripheral is not implemented in Zephyr yet, however,
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* the reference manual states that tamp_pclk is connected to rtc_pclk.
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* It makes sense to have BBRAM instantiated as a child of RTC, so that
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* the driver can verify that its parent device (RTC) is ready.
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*/
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bbram: backup_regs {
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compatible = "st,stm32-bbram";
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st,backup-regs = <20>;
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status = "disabled";
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};
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};
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iwdg: watchdog@40003000 {
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