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dts: arm: st: u5: correct lptim2 clock enable bit

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The LPTIM2 clock enable is bit 5 of RCC APB1 clock enable register 2
(RM0456 Rev 4 11.8.34).

Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
This commit is contained in:
Brett Witherspoon 2023-10-06 21:04:21 -04:00 • committed by Carles Cufí
commit f8e812aa3f
1 changed files with 1 additions and 1 deletions
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2
dts/arm/st/u5/stm32u5.dtsi
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@ -443,7 +443,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40009400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
interrupts = <68 0>;
interrupt-names = "global";
st,static-prescaler;