dts: arm: st: u5: correct lptim2 clock enable bit
The LPTIM2 clock enable is bit 5 of RCC APB1 clock enable register 2 (RM0456 Rev 4 11.8.34). Signed-off-by: Brett Witherspoon <brett@witherspoon.engineering>
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@ -443,7 +443,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40009400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
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interrupts = <68 0>;
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interrupt-names = "global";
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st,static-prescaler;
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