spi: nxp_s32: use clock control APIs
Use clock control API to retrieve the module's frequency and update the boards using it to provide the source clocks. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
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be08ce18d0
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5 changed files with 49 additions and 56 deletions
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@ -7,46 +7,6 @@
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#include <arm/nxp/nxp_s32z27x_r52.dtsi>
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#include "s32z270dc2_r52-pinctrl-common.dtsi"
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&spi0 {
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clock-frequency = <100000000>;
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};
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&spi1 {
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clock-frequency = <100000000>;
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};
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&spi2 {
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clock-frequency = <100000000>;
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};
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&spi3 {
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clock-frequency = <120000000>;
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};
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&spi4 {
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clock-frequency = <120000000>;
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};
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&spi5 {
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clock-frequency = <120000000>;
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};
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&spi6 {
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clock-frequency = <120000000>;
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};
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&spi7 {
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clock-frequency = <100000000>;
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};
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&spi8 {
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clock-frequency = <100000000>;
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};
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&spi9 {
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clock-frequency = <100000000>;
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};
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&stm0 {
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clock-frequency = <133333333>;
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};
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@ -4,6 +4,7 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include "spi_nxp_s32.h"
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@ -273,12 +274,20 @@ static int spi_nxp_s32_configure(const struct device *dev,
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uint8_t frame_size;
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struct spi_nxp_s32_baudrate_param best_baud = {0};
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uint32_t clock_rate;
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int err;
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if (spi_context_configured(&data->ctx, spi_cfg)) {
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/* This configuration is already in use */
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return 0;
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}
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err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate);
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if (err) {
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LOG_ERR("Failed to get clock frequency");
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return err;
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}
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clk_phase = !!(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA);
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clk_polarity = !!(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL);
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@ -340,7 +349,7 @@ static int spi_nxp_s32_configure(const struct device *dev,
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return -ENOTSUP;
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}
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spi_nxp_s32_getbestfreq(config->clock_frequency, spi_cfg->frequency, &best_baud);
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spi_nxp_s32_getbestfreq(clock_rate, spi_cfg->frequency, &best_baud);
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data->transfer_cfg.Ctar &= ~(SPI_CTAR_BR_MASK | SPI_CTAR_PBR_MASK);
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data->transfer_cfg.Ctar |= SPI_CTAR_BR(best_baud.scaler) |
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@ -486,12 +495,29 @@ static int spi_nxp_s32_init(const struct device *dev)
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{
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const struct spi_nxp_s32_config *config = dev->config;
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struct spi_nxp_s32_data *data = dev->data;
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uint32_t clock_rate;
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uint8_t scaler, prescaler;
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uint32_t ctar = 0;
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int ret = 0;
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if (!device_is_ready(config->clock_dev)) {
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LOG_ERR("Clock control device not ready");
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return -ENODEV;
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}
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ret = clock_control_on(config->clock_dev, config->clock_subsys);
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if (ret) {
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LOG_ERR("Failed to enable clock");
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return ret;
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}
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ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate);
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if (ret) {
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LOG_ERR("Failed to get clock frequency");
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return ret;
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}
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ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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@ -513,18 +539,15 @@ static int spi_nxp_s32_init(const struct device *dev)
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* Update the delay timings configuration that are
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* applied for all inner CS signals of SPI module.
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*/
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spi_nxp_s32_getbestdelay(config->clock_frequency,
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config->sck_cs_delay, &scaler, &prescaler);
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spi_nxp_s32_getbestdelay(clock_rate, config->sck_cs_delay, &scaler, &prescaler);
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ctar |= SPI_CTAR_ASC(scaler) | SPI_CTAR_PASC(prescaler);
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spi_nxp_s32_getbestdelay(config->clock_frequency,
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config->cs_sck_delay, &scaler, &prescaler);
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spi_nxp_s32_getbestdelay(clock_rate, config->cs_sck_delay, &scaler, &prescaler);
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ctar |= SPI_CTAR_CSSCK(scaler) | SPI_CTAR_PCSSCK(prescaler);
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spi_nxp_s32_getbestdelay(config->clock_frequency,
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config->cs_cs_delay, &scaler, &prescaler);
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spi_nxp_s32_getbestdelay(clock_rate, config->cs_cs_delay, &scaler, &prescaler);
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ctar |= SPI_CTAR_DT(scaler) | SPI_CTAR_PDT(prescaler);
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@ -654,7 +677,9 @@ static const struct spi_driver_api spi_nxp_s32_driver_api = {
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static const struct spi_nxp_s32_config spi_nxp_s32_config_##n = { \
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.instance = n, \
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.num_cs = SPI_NXP_S32_NUM_CS(n), \
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.clock_frequency = DT_PROP(SPI_NXP_S32_NODE(n), clock_frequency), \
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.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(SPI_NXP_S32_NODE(n))), \
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.clock_subsys = (clock_control_subsys_t) \
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DT_CLOCKS_CELL(SPI_NXP_S32_NODE(n), name), \
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.sck_cs_delay = DT_PROP_OR(SPI_NXP_S32_NODE(n), spi_sck_cs_delay, 0U), \
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.cs_sck_delay = DT_PROP_OR(SPI_NXP_S32_NODE(n), spi_cs_sck_delay, 0U), \
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.cs_cs_delay = DT_PROP_OR(SPI_NXP_S32_NODE(n), spi_cs_cs_delay, 0U), \
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@ -1,5 +1,5 @@
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/*
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* Copyright 2022 NXP
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* Copyright 2022-2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -49,7 +49,8 @@ struct spi_nxp_s32_data {
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struct spi_nxp_s32_config {
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uint8_t instance;
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uint8_t num_cs;
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uint32_t clock_frequency;
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const struct device *clock_dev;
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clock_control_subsys_t clock_subsys;
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uint32_t sck_cs_delay;
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uint32_t cs_sck_delay;
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uint32_t cs_cs_delay;
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@ -457,6 +457,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x40130000 0x10000>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI0_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -467,6 +468,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x40140000 0x10000>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI1_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -477,6 +479,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x40930000 0x10000>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI2_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -487,6 +490,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x40940000 0x10000>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI3_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -497,6 +501,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x40950000 0x10000>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI4_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -507,6 +512,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x42130000 0x10000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI5_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -517,6 +523,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x42140000 0x10000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI6_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -527,6 +534,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x42150000 0x10000>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI7_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -537,6 +545,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x42930000 0x10000>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI8_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -547,6 +556,7 @@
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compatible = "nxp,s32-spi";
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reg = <0x42940000 0x10000>;
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interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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clocks = <&clock NXP_S32_SPI9_CLK>;
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num-cs = <5>;
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#address-cells = <1>;
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#size-cells = <0>;
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@ -1,4 +1,4 @@
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# Copyright 2022 NXP
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# Copyright 2022-2023 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: NXP S32 SPI controller
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@ -20,11 +20,8 @@ properties:
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description: |
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The number of the Chip Select signals.
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clock-frequency:
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type: int
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clocks:
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required: true
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description: |
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Module clock frequency in Hz.
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pinctrl-0:
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required: true
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