Enable us bit to check user mode more efficienly.
US is read as zero in user mode. This will allow use mode sleep
instructions, and it enables a form of denial-of-service attack
by putting the processor in sleep mode, but since interrupt
level/mask can't be set from user space that's not worse than
executing a loop without yielding.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
* add the implementation of syscall
* based on 'trap_s' intruction, id = 3
* add the privilege stack
* the privilege stack is allocted with thread stack
* for the kernel thread, the privilege stack is also a
part of thread stack, the start of stack can be configured
as stack guard
* for the user thread, no stack guard, when the user stack is
overflow, it will fall into kernel memory area which requires
kernel privilege, privilege violation will be raised
* modify the linker template and add MPU_ADDR_ALIGN
* add user space corresponding codes in mpu
* the user sp aux reg will be part of thread context
* When user thread is interruptted for the 1st time, the context is
saved in user stack (U bit of IRQ_CTLR is set to 1). When nest
interrupt comes, the context is saved in thread's privilege stack
* the arc_mpu_regions.c is moved to board folder, as it's board
specific
* the above codes have been tested through tests/kernel/mem_protect/
userspace for MPU version 2
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
This patch adjusts the default permissions on the bus master 3 (NET).
Recent changes restricted this to supervisor only, and this caused
issues with the network controllers access to memory.
Restrictions on access should really be enforced on the ARM core bus
master.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support for userspace on ARM architectures. Arch
specific calls for transitioning threads to user mode, system calls,
and associated handlers.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds a configure_mpu_user_context API and implements
the required function placeholders in the NXP and ARM MPU files.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The STM32 has special Core Coupled Memory, ccm for short, that can
only be accessed through the CPU and can not be use for DMA.
The following 3 sections have been added.
- ccm_bss for zero initialized data
- ccm_data for initialized data
- ccm_noinit for uninitialized data
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
This feature is X86 only and is not used or being tested. It is legacy
feature and no one can prove it actually works. Remove it until we have
proper documentation and samples and multi architecture support.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit defines the Kconfig options for
ARM Cortex-M23 and Cortex-M33 CPUs. It also
udpates the generic memory map for M23 and M33
implementations.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This patch adds the generation and incorporation of privileged stack
regions that are used by ARM user mode threads. This patch adds the
infrastructure for privileged stacks. Later patches will utilize the
generated stacks and helper functions.
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds application data section alignment constraints
to match the region definition requirements for ARM MPUs. Most MPUs
require a minimum of 32 bytes of alignment for any regions, but some
require power of two alignment to the size of a region.
This requires that the linker align the application data section to
the size of the section. This requires a linker pass to determine the
size. Once this is accomplished the correct value is added to a linker
include file that is utilized in subsequent linker operations.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
For SoCs that don't support vector table relocation in hardware, may not
support bootloader like mcuboot.
We introduce a way to relocate vector table in software by forwarding
the control of incoming IRQs to a new vector table which address is save
at fixed SRAM address.
User can change the data in that fixed SRAM address in order to relocate
vector table in software way.
Signed-off-by: Ding Tao <miyatsu@qq.com>
Refering the ARM's implementation, the initial support of memory
domain in ARC is added:
* changes in MPU drivers
* changes in Kconfig
* codes to configure memory domain during thread swap
* changes in linker script template
* memory domain related macro definitions
the commited codes are simply tested through
samples/mpu/mem_domain_apis_test.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
The _vector_start was placed before the CONFIG_TEXT_SECTION_OFFSET, thus
adding the offset in the relocated vector table, making the table
invalid when relocated with a non null CONFIG_TEXT_SECTION_OFFSET.
This was tested using MCUboot with a 0x200 offset for the image header.
Fixes: eb48a0a73c ("arm: armv6-m: Support relocating vector table")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
A new arch (posix) which relies on pthreads to emulate the context
switching
A new soc for it (inf_clock) which emulates a CPU running at an
infinely high clock (so when the CPU is awaken it runs till completion
in 0 time)
A new board, which provides a trivial system tick timer and
irq generation.
Origin: Original
Fixes#1891
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add an architecure specfic code for the memory domain
configuration. This is needed to support a memory domain API
k_mem_domain_add_thread.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
MPU version 3 is included in em7d of em_starterkit 2.3.
The differences of MPU version 3 and version 2 are:
* different aux reg interface
* The address alignment requirement is 32 bytes
* supports secure mode
* supports SID (option)
* does not support memory region overlap
This commit adds the support MPU version 3 and also make some changes to
MPU version 2 to have an unified interface.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
In ARC's SecureShield, a new secure mode (currently only em) is added.
The secure/normal mode is orthogonal to kernel/user mode. The
differences between secure mode and normal mode are following:
* different irq stack frame. so need to change the definition of
_irq_stack_frame, assembly code.
* new aux regs, e.g, secure status(SEC_STAT), secure vector base
(VECT_BASE_S)
* interrupts and exceptions, secure mode has its own vector base;
interrupt can be configured as secure or normal through the
interrupt priority aux reg.
* secure timers. Two secure timers (secure timer 0 and timer 1) are
added.Here, for simplicity and backwards compatibility original
internal timers (timer 0 and timer1) are used as sys clock of zephyr
* on reset, the processor is in secure mode and secure vector base is
used.
Note: the mix of secure and normal mode is not supported, i.e. it's
assumed that the processor is always in secure mode.
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Define _image_rodata_start/end to match x86 and so that we can
refer to them in the userspace test among others.
Signed-off-by: Stephen Smalley <sds@tycho.nsa.gov>
Implement API to validate user buffer. This API will iterate
all MPU regions to check if the given buffer is user accessible
or not. For #3832.
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This is intended for memory-constrained systems and will save
4K per thread, since we will no longer reserve room for or
activate a kernel stack guard page.
If CONFIG_USERSPACE is enabled, stack overflows will still be
caught in some situations:
1) User mode threads overflowing stack, since it crashes into the
kernel stack page
2) Supervisor mode threads overflowing stack, since the kernel
stack page is marked non-present for non-user threads
Stack overflows will not be caught:
1) When handling a system call
2) When the interrupt stack overflows
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is an introductory port for Zephyr to be run as a Jailhouse
hypervisor[1]'s "inmate cell", on x86 64-bit CPUs (running on 32-bit
mode). This was tested with their "tiny-demo" inmate demo cell
configuration, which takes one of the CPUs of the QEMU-VM root cell
config, along with some RAM and serial controller access (it will even
do nice things like reserving some L3 cache for it via Intel CAT) and
Zephyr samples:
- hello_world
- philosophers
- synchronization
The final binary receives an additional boot sequence preamble that
conforms to Jailhouse's expectations (starts at 0x0 in real mode). It
will put the processor in 32-bit protected mode and then proceed to
Zephyr's __start function.
Testing it is just a matter of:
$ mmake -C samples/<sample_dir> BOARD=x86_jailhouse JAILHOUSE_QEMU_IMG_FILE=<path_to_image.qcow2> run
$ sudo insmod <path to jailhouse.ko>
$ sudo jailhouse enable <path to configs/qemu-x86.cell>
$ sudo jailhouse cell create <path to configs/tiny-demo.cell>
$ sudo mount -t 9p -o trans/virtio host /mnt
$ sudo jailhouse cell load tiny-demo /mnt/zephyr.bin
$ sudo jailhouse cell start tiny-demo
$ sudo jailhouse cell destroy tiny-demo
$ sudo jailhouse disable
$ sudo rmmod jailhouse
For the hello_world demo case, one should then get QEMU's serial port
output similar to:
"""
Created cell "tiny-demo"
Page pool usage after cell creation: mem 275/1480, remap 65607/131072
Cell "tiny-demo" can be loaded
CPU 3 received SIPI, vector 100
Started cell "tiny-demo"
***** BOOTING ZEPHYR OS v1.9.0 - BUILD: Sep 12 2017 20:03:22 *****
Hello World! x86
"""
Note that the Jailhouse's root cell *has to be started in xAPIC
mode* (kernel command line argument 'nox2apic') in order for this to
work. x2APIC support and its reasoning will come on a separate commit.
As a reminder, the make run target introduced for x86_jailhouse board
involves a root cell image with Jailhouse in it, to be launched and then
partitioned (with >= 2 64-bit CPUs in it).
Inmate cell configs with no JAILHOUSE_CELL_PASSIVE_COMMREG flag
set (e.g. apic-demo one) would need extra code in Zephyr to deal with
cell shutdown command responses from the hypervisor.
You may want to fine tune CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC for your
specific CPU—there is no detection from Zephyr with regard to that.
Other config differences from pristine QEMU defaults worth of mention
are:
- there is no HPET when running as Jailhouse guest. We use the LOAPIC
timer, instead
- there is no PIC_DISABLE, because there is no 8259A PIC when running
as a Jailhouse guest
- XIP makes no sense also when running as Jailhouse guest, and both
PHYS_RAM_ADDR/PHYS_LOAD_ADD are set to zero, what tiny-demo cell
config is set to
This opens up new possibilities for Zephyr, so that usages beyond just
MCUs come to the table. I see special demand coming from
functional-safety related use cases on industry, automotive, etc.
[1] https://github.com/siemens/jailhouse
Reference to Jailhouse's booting preamble code:
Origin: Jailhouse
License: BSD 2-Clause
URL: https://github.com/siemens/jailhouse
commit: 607251b44397666a3cbbf859d784dccf20aba016
Purpose: Dual-licensing of inmate lib code
Maintained-by: Zephyr
Signed-off-by: Gustavo Lima Chaves <gustavo.lima.chaves@intel.com>
This adds CONFIG_EXECUTE_XOR_WRITE, which is enabled by default on
systems that support controlling whether a page can contain executable
code. This is also known as W^X[1].
Trying to add a memory domain with a page that is both executable and
writable, either for supervisor mode threads, or for user mode threads,
will result in a kernel panic.
There are few cases where a writable page should also be executable
(JIT compilers, which are most likely out of scope for Zephyr), so an
option is provided to disable the check.
Since the memory domain APIs are executed in supervisor mode, a
determined person could bypass these checks with ease. This is seen
more as a way to avoid people shooting themselves in the foot.
[1] https://en.wikipedia.org/wiki/W%5EX
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
We were unnecessarily pulling in headers which resulted in kernel.h
being pulled in, which is undesirable since arch/cpu.h pulls in
these headers.
Added integral type headers since we do need those.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
kernel.h depends on arch.h, and reverse dependencies need to be
removed. Define k_tid_t as some opaque pointer type so that arch.h
doesn't have to pull in kernel.h.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This header needs Zephyr's specific type definitions. It also
needs struct k_mem_partition and struct k_mem_domain, but they
are defined opaquely here instead of pulling in kernel.h (which
would create nasty dependency loops)
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Created structures and unions needed to enable the software to
access these tables.
Also updated the helper macros to ease the usage of the MMU page
tables.
JIRA: ZEP-2511
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Some SOCs (e.g. STM32F0) can map the flash to address 0 and
the flash base address at the same time. Prevent writing to
duplicate flash address which stops the SOC.
Allow Cortex M SOCs to create their own vector table relocation
function.
Provide a relocation function for STM32F0x SOCs.
Fixes#3923
Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
arg6 is treated as a memory constraint. If that memory
address was expressed as an operand to 'mov' in the generated
code as an offset from the stack pointer, then the 'push'
instruction immediately before it could end up causing memory 4
bytes off from what was intended being passed in as the 6th
argument.
Add ESP register to the clobber list to fix this issue.
Fixes issues observed with k_thread_create() passing in a
NULL argument list with CONFIG_DEBUG=y.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We need to track permission on stack memory regions like we do
with other kernel objects. We want stacks to live in a memory
area that is outside the scope of memory domain permission
management. We need to be able track what stacks are in use,
and what stacks may be used by user threads trying to call
k_thread_create().
Some special handling is needed because thread stacks appear as
variously-sized arrays of struct _k_thread_stack_element which is
just a char. We need the entire array to be considered an object,
but also properly handle arrays of stacks.
Validation of stacks also requires that the bounds of the stack
are not exceeded. Various approaches were considered. Storing
the size in some header region of the stack itself would not allow
the stack to live in 'noinit'. Having a stack object be a data
structure that points to the stack buffer would confound our
current APIs for declaring stacks as arrays or struct members.
In the end, the struct _k_object was extended to store this size.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These needed "memory" clobbers otherwise the compiler would do
unnecessary optimizations for parameters passed in as pointer
values.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add the following application-facing memory domain APIs:
k_mem_domain_init() - to initialize a memory domain
k_mem_domain_destroy() - to destroy a memory domain
k_mem_domain_add_partition() - to add a partition into a domain
k_mem_domain_remove_partition() - to remove a partition from a domain
k_mem_domain_add_thread() - to add a thread into a domain
k_mem_domain_remove_thread() - to remove a thread from a domain
A memory domain would contain some number of memory partitions.
A memory partition is a memory region (might be RAM, peripheral
registers, flash...) with specific attributes (access permission,
e.g. privileged read/write, unprivileged read-only, execute never...).
Memory partitions would be defined by set of MPU regions or MMU tables
underneath.
A thread could only belong to a single memory domain any point in time
but a memory domain could contain multiple threads.
Threads in the same memory domain would have the same access permission
to the memory partitions belong to the memory domain.
The memory domain APIs are used by unprivileged threads to share data
to the threads in the same memory and protect sensitive data from
threads outside their domain. It is not only for improving the security
but also useful for debugging (unexpected access would cause exception).
Jira: ZEP-2281
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
The compiler was complaining about impossible constraints since register
constraint was provided, but there are no general purpose registers left
available.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This wasn't working properly with CONFIG_APPLICATION_MEMORY enabled as
the sections weren't handled in the linker script.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A quick look at "man syscall" shows that in Linux, all architectures
support at least 6 argument system calls, with a few supporting 7. We
can at least do 6 in Zephyr.
x86 port modified to use EBP register to carry the 6th system call
argument.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
* Instead of a common system call entry function, we instead create a
table mapping system call ids to handler skeleton functions which are
invoked directly by the architecture code which receives the system
call.
* system call handler prototype specified. All but the most trivial
system calls will implement one of these. They validate all the
arguments, including verifying kernel/device object pointers, ensuring
that the calling thread has appropriate access to any memory buffers
passed in, and performing other parameter checks that the base system
call implementation does not check, or only checks with __ASSERT().
It's only possible to install a system call implementation directly
inside this table if the implementation has a return value and requires
no validation of any of its arguments.
A sample handler implementation for k_mutex_unlock() might look like:
u32_t _syscall_k_mutex_unlock(u32_t mutex_arg, u32_t arg2, u32_t arg3,
u32_t arg4, u32_t arg5, void *ssf)
{
struct k_mutex *mutex = (struct k_mutex *)mutex_arg;
_SYSCALL_ARG1;
_SYSCALL_IS_OBJ(mutex, K_OBJ_MUTEX, 0, ssf);
_SYSCALL_VERIFY(mutex->lock_count > 0, ssf);
_SYSCALL_VERIFY(mutex->owner == _current, ssf);
k_mutex_unlock(mutex);
return 0;
}
* the x86 port modified to work with the system call table instead of
calling a common handler function. fixed an issue where registers being
changed could confuse the compiler has been fixed; all registers, even
ones used for parameters, must be preserved across the system call.
* a new arch API for producing a kernel oops when validating system call
arguments added. The debug information reported will be from the system
call site and not inside the handler function.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
- _arch_user_mode_enter() implemented
- _arch_is_user_context() implemented
- _new_thread() will honor K_USER option if passed in
- System call triggering macros implemented
- _thread_entry_wrapper moved and now looks for the next function to
call in EDI
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
- There's no point in building up "validity" (declared volatile for some
strange reason), just exit with false return value if any of the page
directory or page table checks don't come out as expected
- The function was returning the opposite value as its documentation
(0 on success, -EPERM on failure). Documentation updated.
- This function will only be used to verify buffers from user-space.
There's no need for a flags parameter, the only option that needs to
be passed in is whether the buffer has write permissions or not.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The byte ones are required for ns16550 uart driver which is
present on some arm socs. Add half-word ones for completeness.
Signed-off-by: Timo Teräs <timo.teras@iki.fi>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This was felt to be necessary at one point but actually isn't.
- When a thread is initialized to use a particular stack, calls will be
made to the MMU/MPU to restrict access to that stack to only that
thread. Once a stack is in use, it will not be generally readable even
if the buffer exists in application memory space.
- If a user thread wants to create a thread, we will need to have some
way to ensure that whatever stack buffer passed in is unused and
appropriate. Since unused stacks in application memory will be generally
accessible, we can just check that the calling thread to
k_thread_create() has access to the stack buffer passed in, it won't if
the stack is in use.
On ARM we had a linker definition for .stacks, but currently stacks are
just tagged with __noinit (which is fine).
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, this was only done if an essential thread self-exited,
and was a runtime check that generated a kernel panic.
Now if any thread has k_thread_abort() called on it, and that thread
is essential to the system operation, this check is made. It is now
an assertion.
_NANO_ERR_INVALID_TASK_EXIT checks and printouts removed since this
is now an assertion.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All system calls made from userspace which involve pointers to kernel
objects (including device drivers) will need to have those pointers
validated; userspace should never be able to crash the kernel by passing
it garbage.
The actual validation with _k_object_validate() will be in the system
call receiver code, which doesn't exist yet.
- CONFIG_USERSPACE introduced. We are somewhat far away from having an
end-to-end implementation, but at least need a Kconfig symbol to
guard the incoming code with. Formal documentation doesn't exist yet
either, but will appear later down the road once the implementation is
mostly finalized.
- In the memory region for RAM, the data section has been moved last,
past bss and noinit. This ensures that inserting generated tables
with addresses of kernel objects does not change the addresses of
those objects (which would make the table invalid)
- The DWARF debug information in the generated ELF binary is parsed to
fetch the locations of all kernel objects and pass this to gperf to
create a perfect hash table of their memory addresses.
- The generated gperf code doesn't know that we are exclusively working
with memory addresses and uses memory inefficently. A post-processing
script process_gperf.py adjusts the generated code before it is
compiled to work with pointer values directly and not strings
containing them.
- _k_object_init() calls inserted into the init functions for the set of
kernel object types we are going to support so far
Issue: ZEP-2187
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch fixes a couple of issues with the stack guard size and
properly constructs the STACK_ALIGN and STACK_ALIGN_SIZE definitions.
The ARM AAPCS requires that the stack pointers be 8 byte aligned. The
STACK_ALIGN_SIZE definition is meant to contain the stack pointer
alignment requirements. This is the required alignment at public API
boundaries (ie stack frames).
The STACK_ALIGN definition is the required alignment for the start
address for stack buffer storage. STACK_ALIGN is used to validate
the allocation sizes for stack buffers.
The MPU_GUARD_ALIGN_AND_SIZE definition is the minimum alignment and
size for the MPU. The minimum size and alignment just so happen to be
32 bytes for vanilla ARM MPU implementations.
When defining stack buffers, the stack guard alignment requirements
must be taken into consideration when allocating the stack memory.
The __align() must be filled in with either STACK_ALIGN_SIZE or the
align/size of the MPU stack guard. The align/size for the guard region
will be 0 when CONFIG_MPU_STACK_GUARD is not set, and 32 bytes when it
is.
The _ARCH_THREAD_STACK_XXXXXX APIs need to know the minimum alignment
requirements for the stack buffer memory and the stack guard size to
correctly allocate and reference the stack memory. This is reflected
in the macros with the use of the STACK_ALIGN definition and the
MPU_GUARD_ALIGN_AND_SIZE definition.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
* apply STACK_GUARD_SIZE, no extra space will be added if
MPU_STACK_GUARD is disabled
* When ARC_STACK_CHECKING is enabled, MPU_STACK_GUARD will be
disabled
* add two new api: arc_core_mpu_default and arc_core_mpu_region
to configure mpu regions
* improve arc_core_mpu_enable and arc_core_mpu_disable
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
* add arc mpu driver
* modify the corresponding kconfig and kbuild
* currently only em_starterkit 2.2's em7d configuration
has mpu feature (mpu version 2)
* as the minimum region size of arc mpu version 2 is 2048 bytes and
region size should be power of 2, the stack size of threads
(including main thread and idle thread) should be at least
2048 bytes and power of 2
* for mpu stack guard feature, a stack guard region of 2048 bytes
is generated. This brings more memory footprint
* For arc mpu version 3, the minimum region size is 32 bytes.
* the codes are tested by the mpu_stack_guard_test and stackprot
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
Fix misspellings in .h files missed during code reviews
and affecting generated API documentation
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
An abnormal crash was encountered in ARMv6-M SoCs that don't have flash
starting at 0. With Zephyr OS the reason for this crash is that, on
ARMv6-M the system requires an exception vector table at the 0 address.
We implement the relocate_vector_table function to move the vector table
code to address 0 on systems which don't have the start of code already
at 0.
[kumar.gala: reworderd commit message, tweaked how we check if we need
to copy vector table]
Signed-off-by: Xiaorui Hu <xiaorui.hu@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Xtensa port was the only one remaining to be converted to the new
way of connecting interrupts in Zephyr. Some things are still
unconverted, mainly the exception table, and this will be performed
another time.
Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since
IRQs can't change priority on Xtensa: while the architecture has the
concept of interrupt priority levels, each line has a fixed level and
can't be changed.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This patch adjusts the ARM MPU implementation to be compliant to the
recent changes that introduced the opaque kernel data types.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch always defines the ARCH_THREAD_STACK_XXX macros/functions
regardless of the MPU_STACK_GUARD usage. Only use MPU_STACK_GUARD when
determining the minimum stack alignment.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The mimimum mpu size is 32 bytes, but requires mpu base address to be
aligned on 32 bytes to work. Define architecture thread macro when
MPU_STACK_GUARD config to allocate stack with 32 more bytes.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
This patch adds the allow flash write CONFIG option to the ARM MPU
configuration in privileged mode.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
This patch adds the allow flash write CONFIG option to the NXP MPU
configuration in privileged mode.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
This is a simpler memory arrangement; RAM will start with
app data, and everything after it is either kernel data or
unclaimed memory reserved for the kernel's use.
New linker variables are also implemented here.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Kernel data size shifts in between linker passes due to the addition
of the page tables. We would like application memory bounds to
remain fixed so that we can program the MMU permissions for it
at build time.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Page faults will additionally dump out some interesting
page directory and page table flags for the faulting
memory address.
Intended to help determine whether the page tables have been
configured incorrectly as we enable memory protection features.
This only happens if CONFIG_EXCEPTION_DEBUG is turned on.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Historically, stacks were just character buffers and could be treated
as such if the user wanted to look inside the stack data, and also
declared as an array of the desired stack size.
This is no longer the case. Certain architectures will create a memory
region much larger to account for MPU/MMU guard pages. Unfortunately,
the kernel interfaces treat both the declared stack, and the valid
stack buffer within it as the same char * data type, even though these
absolutely cannot be used interchangeably.
We introduce an opaque k_thread_stack_t which gets instantiated by
K_THREAD_STACK_DECLARE(), this is no longer treated by the compiler
as a character pointer, even though it really is.
To access the real stack buffer within, the result of
K_THREAD_STACK_BUFFER() can be used, which will return a char * type.
This should catch a bunch of programming mistakes at build time:
- Declaring a character array outside of K_THREAD_STACK_DECLARE() and
passing it to K_THREAD_CREATE
- Directly examining the stack created by K_THREAD_STACK_DECLARE()
which is not actually the memory desired and may trigger a CPU
exception
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Subsequent patches will set this guard page as unmapped,
triggering a page fault on access. If this is due to
stack overflow, a double fault will be triggered,
which we are now capable of handling with a switch to
a know good stack.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now create a special IA hardware task for handling
double faults. This has a known good stack so that if
the kernel tries to push stack data onto an unmapped page,
we don't triple-fault and reset the system.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We will need this for stack memory protection scenarios
where a writable GDT with Task State Segment descriptors
will be used. The addresses of the TSS segments cannot be
put in the GDT via preprocessor magic due to architecture
requirments that the address be split up into different
fields in the segment descriptor.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This has one use-case: configuring the double-fault #DF
exception handler to do an IA task switch to a special
IA task with a known good stack, such that we can dump
diagnostic information and then panic.
Will be used for stack overflow detection in kernel mode,
as otherwise the CPU will triple-fault and reset.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A user space buffer must be validated before required operation
can proceed. This API will check the current MMU
configuration to determine if the buffer held by the user is valid.
Jira: ZEP-2326
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This needs to be in <arch/cpu.h> so that it can be called
from the k_panic()/k_oops() macros in kernel.h.
Fixes build errors on these arches when using k_panic() or
k_oops().
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Different areas of memory will need to have different access
policies programmed into the MMU. We introduce MMU page alignment
to the following areas:
- The boundaries of the image "ROM" area
- The beginning of RAM representing kernel datas/bss/nonit
- The beginning of RAM representing app datas/bss/noinit
Some old alignment directives that are no longer necessary have
been removed.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch splits out the application data and bss from the
rest of the kernel. Choosing CONFIG_APPLICATION_MEMORY will
result in the application and kernel being split.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Implements CONFIG_APPLICATION_MEMORY for x86. Working in
XIP and non-XIP configurations.
This patch does *not* implement any alignment constraints
imposed by the x86 MMU, such enabling will be done later.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
patch adds necessary files and does the modification to the existing
files to add device support for x86 based intel quark microcontroller
Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
This is unmaintained and currently has no known users. It was
added to support a Wind River project. If in the future we need it
again, we should re-introduce it with an exception-based mechanism
for catching out-of-bounds memory queries from the debugger.
The mem_safe subsystem is also removed, it is only used by the
GDB server. If its functionality is needed in the future, it
shoudl be replaced with an exception-based mechanism.
The _image_{ram, rom, text}_{start, end} linker variables have
been left in place, they will be re-purposed and expanded to
support memory protection.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The porting of the TI CC2650 SoC introduces the need to
write a specific configuration area (CCFG) at the end of the
flash. It is read by the bootloader ROM of the SoC.
For now, this is a quick hack and not a generic solution;
similar needs may arise with other hardware.
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
Clearing fields in the region descriptor attributes doesn't always have
the expected effect of revoking permissions. In the case of bus master
supervisor mode fields (MxSM), setting to zero actually enables read,
write, and execute access.
When we reworked handling of region descriptor 0, we inadvertently
enabled execution from RAM by clearing the MxSM fields and enabling the
descriptor. This caused samples/mpu_test run to throw a usage fault
instead of an MPU-triggered bus fault.
Fix this by setting all the MxSM fields to 2'b11, which gives supervisor
mode the same access as user mode.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
We need to make sure that __NVIC_PRIO_BITS & CONFIG_NUM_IRQ_PRIO_BITS
are set to the same value. Add a simple build time check to ensure
this is the case. This is to catch future cases of issues like
ZEP-2243. This is a stop gap til we resolve ZEP-2262, which covers use
of both __NVIC_PRIO_BITS & CONFIG_NUM_IRQ_PRIO_BITS.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Macro is used to create a structure to specify the boot time
page table configuration. Needed by the gen_mmu.py script to generate
the actual page tables.
Linker script is needed for the following:
1. To place the MMU page tables at 4KByte boundary.
2. To keep the configuration structure created by
the Macro(mentioned above).
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Fixes an issue where if a thread calls k_panic() or k_oops()
with interrupts locked, control would return to the thread
and it would only be aborted after interrupts were unlocked
again.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The REGION bits (bit[3:0]) of MPU_RBAR register can specify the number
of the region to update if the VALID bit (bit[4]) is also set.
If the bit[3:0] of "region_addr" are not zero, might cause to update
unexpected region. This could happen since we might not declare stack
memory with specific alignment.
This patch will mask the bit[4:0] of "region_addr" to prevent updating
unexpected region.
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Inserting the IDT results in any data afterwards being shifted.
We want the memory addresses between the zephyr_prebuilt.elf
and zephyr.elf to be as close as possible. Insert some dummy
data in the linker script the same size as the gen_idt data
structures. Needed for forthcoming patches which generate MMU
page tables at build time.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Calling 'svc' on ARMv6 causes a hard fault if interrups are locked.
Force them unlocked before making the svc call.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Ethernet on K64F is connected via Logical Bus Master 3.
Section 19.3.8 of K64F reference manual establishes bits 20-18
(M3UM) on page 427 as "Bus Master 3 User Mode Access Control".
To fix RWX user mode access via Bus Master 3 when MPU is enabled,
we need to add these bits to the MPU region descriptors.
This fixes ETH0 on K64F when MPU is enabled.
Fix recommended by Maureen Helm <maureen.helm@nxp.com>
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Let's clarify what bits are being set by removing magic numbers in the
MPU READ/WRITE/EXECUTE User Mode and Supervisor Mode defines.
Signed-off-by: Michael Scott <michael.scott@linaro.org>
This patch add arm core MPU support to NXP MPU driver.
With this feature it is now possible to enable stack guarding on NXP
MPUs.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Here are the main changes:
* board: Update EMSK onboard resources such as Button, Switch and LEDs
+ update soc.h for em7d, em9d, em11d
+ update board.h for em_starterkit board
* arc: Add floating point support and code density support
+ add kconfig configuration
+ add compiler options
+ add register definitions, marcos, assembly codes
+ fixes in existing codes and configurations.
* arc: Update detailed board configurations for cores of emsk 2.3
* script: Provide arc_debugger.sh for debugging em_starterkit board
+ make BOARD=em_starterkit debug
This will start openocd server for emsk, and arc gdb will connect
to this debug server, user can run `continue` command if user just
want to run the application, or other commands if debugging needed.
+ make BOARD=em_starterkit debugserver
This will start an openocd debugger server for emsk, and user can
connect to this debugserver using arc gdb and do what they want to.
+ make BOARD=em_starterkit flash
This will download the zephyr application elf file to emsk,
and run it.
Signed-off-by: Huaqi Fang <huaqi.fang@synopsys.com>
This patch add arm core MPU support to ARM MPU driver.
Change-Id: I5a61da4615ae687bf42f1c9947e291ebfd2d2c1d
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds the arm core MPU interface, a common way to access the
pu functionalities by the arm zephyr kernel.
The interface can be divided in two parts:
- a core part that will be implemented by the arm_core_mpu driver and
used directly by the kernel
- a driver part that will be implemented by the mpu drivers and used by
the arm_core_mpu driver
Change-Id: I590bd284abc40d98b06fdf1efb5800903313aa00
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This patch adds initial MPU support to NXP K6x family.
The boot configuration prevents the following security issues:
* Prevent to read at an address that is reserved in the memory map.
* Prevent to write into the boot Flash/ROM.
* Prevent from running code located in SRAM.
This driver has been tested on FRDM-K64F.
Change-Id: I907168fff0c6028f1c665f1d3c224cbeec31be32
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
For various reasons its often necessary to generate certain
complex data structures at build-time by separate tools outside
of the C compiler. Data is populated to these tools by way of
special binary sections not intended to be included in the final
binary. We currently do this to generate interrupt tables, forthcoming
work will also use this to generate MMU page tables.
The way we have been doing this is to generatea "kernel_prebuilt.elf",
extract the metadata sections with objcopy, run the tool, and then
re-link the kernel with the extra data *and* use objcopy to pull
out the unwanted sections.
This doesn't scale well if multiple post-build steps are needed.
Now this is much simpler; in any Makefile, a special
GENERATED_KERNEL_OBJECT_FILES variable may be appended to containing
the filenames to the generated object files, which will be generated
by Make in the usual fashion.
Instead of using objcopy to pull out, we now create a linker-pass2.cmd
which additionally defines LINKER_PASS2. The source linker script
can #ifdef around this to use the special /DISCARD/ section target
to not include metadata sections in the final binary.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are macros that are expected to be defined at all times by
the compiler. We need them at the very beginning of kernel.h for
the k_thread definition, before it's possible to include arch.h.
Make a special toolchain header for XCC compiler and place these
defines in there. Otherwise inherit all the other GCC defines.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We don't use __scs or __scp anymore so we can remove the related linker
script and various defines and such associated with them.
Change-Id: Ibbbe27c23a3f2b816b992dfdeb4f80cf798e0d40
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
CC3220SF_LAUNCHXL effectively replaces the CC3200_LAUNCHXL,
with support for the CC3220SF SoC, which is an update for
the CC3200 SoC.
This is supported by the Texas Instruments CC3220 SDK.
Jira: ZEP-1958
Change-Id: I2484d3ee87b7f909c783597d95128f2b45db36f2
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Historically, space for struct k_thread was always carved out of the
thread's stack region. However, we want more control on where this data
will reside; in memory protection scenarios the stack may only be used
for actual stack data and nothing else.
On some platforms (particularly ARM), including kernel_arch_data.h from
the toplevel kernel.h exposes intractable circular dependency issues.
We create a new per-arch header "kernel_arch_thread.h" with very limited
scope; it only defines the three data structures necessary to instantiate
the arch-specific bits of a struct k_thread.
Change-Id: I3a55b4ed4270512e58cf671f327bb033ad7f4a4f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch add the Memory Protection Unit parameter to the arm core
configuration.
Change-Id: Ifee8cdd5738391a6f182e8d0382d27eeb8c546ba
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Marc Moreno <marc.morenoberengue@linaro.org>
Put the reason code in r0 and make a SVC #2 call, which will be
propagated to _fatal_error_handler as an exception.
The _is_in_isr() implementation had to be tweaked a bit. User-generated
SVC exception no longer just used for irq_offload(); just because we are
in it does not mean we are in interrupt context. Instead, have the
irq_offload code set and clear the offload_routine global; it will be
non-NULL only if it's in use. Upcoming changes to support memory
protection (which will require system calls) will need this too.
We free up some small amount of ROM deleting _default_esf struct as it's
no longer needed.
Issue: ZEP-843
Change-Id: Ie82bd708575934cffe41e64f5c128c8704ca4e48
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We reserve a specific vector in the IDT to trigger when we want to
enter a fatal exception state from software.
Disabled for drivers/build_all tests as we were up to the ROM limit
on Quark D2000.
Issue: ZEP-843
Change-Id: I4de7f025fba0691d07bcc3b3f0925973834496a0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Unlike assertions, these APIs are active at all times. The kernel will
treat these errors in the same way as fatal CPU exceptions. Ultimately,
the policy of what to do with these errors is implemented in
_SysFatalErrorHandler.
If the archtecture supports it, a real CPU exception can be triggered
which will provide a complete register dump and PC value when the
problem occurs. This will provide more helpful information than a fake
exception stack frame (_default_esf) passed to the arch-specific exception
handling code.
Issue: ZEP-843
Change-Id: I8f136905c05bb84772e1c5ed53b8e920d24eb6fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For exceptions where we are just going to abort the current thread, we
need to exit handler mode properly so that PendSV can run and perform a
context switch. For ARM architecture this means that the fatal error
handling code path can indeed return if we were 1) in handler mode and
2) only wish to abort the current thread.
Fixes a very long-standing bug where a thread that generates an
exception, and should only abort the thread, instead takes down the
entire system.
Issue: ZEP-2052
Change-Id: Ib356a34a6fda2e0f8aff39c4b3270efceb81e54d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types. This handles the remaining includes and kernel, plus
touching up various points that we skipped because of include
dependancies. We also convert the PRI printf formatters in the arch
code over to normal formatters.
Jira: ZEP-2051
Change-Id: Iecbb12601a3ee4ea936fd7ddea37788a645b08b0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This is a start to move away from the C99 {u}int{8,16,32,64}_t types to
Zephyr defined u{8,16,32,64}_t and s{8,16,32,64}_t. This allows Zephyr
to define the sized types in a consistent manor across all the
architectures we support and not conflict with what various compilers
and libc might do with regards to the C99 types.
We introduce <zephyr/types.h> as part of this and have it include
<stdint.h> for now until we transition all the code away from the C99
types.
We go with u{8,16,32,64}_t and s{8,16,32,64}_t as there are some
existing variables defined u8 & u16 as well as to be consistent with
Zephyr naming conventions.
Jira: ZEP-2051
Change-Id: I451fed0623b029d65866622e478225dfab2c0ca8
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Scanning for typos in comments and strings.
Change-Id: I3d4db89e0824959252c79c19baa50028354247bd
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
The CONFIG_FLASH_LOAD_OFFSET allows the zephyr image to be placed at
an offset from the start of flash. This is useful for situations,
such as with a bootloader, to allow the image to not occupy the very
beginning of flash.
Complement this by adding a CONFIG_FLASH_LOAD_SIZE config, that can
constrain the size of the flash image. With the default of zero, the
behavior is as before, with the image allowed to occupy the rest of
the flash. It can also be defined to a non-zero value which will
constrain the image to occupy that many bytes of flash.
Although this is defined generally, it is currently only supported on
cortex-m targets.
Change-Id: I6e4a0e79c8459f931cd4757c932d20dac740f5f6
Signed-off-by: David Brown <david.brown@linaro.org>
__BYTE_ORDER__, __ORDER_BIG_ENDIAN__ and __ORDER_LITTLE_ENDIAN__ are not
defined when building with xcc, but are defined when building with gcc.
Define them conditionally.
Change-Id: Ib205ffee28360aa240d61731b7a3d6f45401b4c1
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
The SiFive Freedom E310 SOC follows the riscv privilege
architecture specification and hence is declared within
the riscv privilege SOC family.
It also provides support for a riscv
Platform Level Interrupt Controller (PLIC)
Change-Id: I19ff0997eacc248f48444fc96566a105c6c02663
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Updated the riscv-privilege SOC family to account for SOCs supporting
a Platform-level Interrupt Controller (PLIC) as specified by the
riscv privilege architecture.
riscv-privilege SOCs supporting a PLIC have to implement the following
list of APIs:
void riscv_plic_irq_enable(uint32_t irq);
void riscv_plic_irq_disable(uint32_t irq);
int riscv_plic_irq_is_enabled(uint32_t irq);
void riscv_plic_set_priority(uint32_t irq, uint32_t priority);
int riscv_plic_get_irq(void);
Change-Id: I0228574967348d572afc98a79257c697efc4309e
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
Current users of sys_bitfield*() are bending over backwards to cast
what is most of the times a pointer into an integer.
Bitfields can be better described with an void *, so
uint{8,16,32,64}_t or any other container can be used. Most
sys_bitfield*() operations, by extension, can do the same. Note void *
has byte arithmetic, like char *.
This change will also make it implicit, for any future split of the
address space between virtual (what the SW is seeing) and physical
(what the HW is seeing) way clearer, as the functions dealing with
physical, non directly referentiable/mappeable addreses to use an
integer type, like mem_addr_t.
- include/arch/ARCH/*asm_inline*:
- sys_bitfield*() all modified to take 'void *'
Note 'void *' arihtmethic is byte based, which makes some things
easier.
- include/sys_io.h:
- introduces DEFINE_BITFIELD
- update docs
- tests/kernel/bitfield: remove all the cast contortions, use DEFINE_BITFIELD
PENDING: update other TCs
- include/arch/nios/nios2.h, drivers/interrupt_controller/ioapic_intr.c:
remove cast contortions
Change-Id: I901e62c76af46f26ff0d29cdc37099597f884511
Jira: ZEP-1347
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
It's not entirely clear where the '%P' came from, but the proper,
documented operand modifier for inserting an immediate value without
punctuation is '%c'.
Change-Id: I17346a6c70183ce79e91faa2fbe61e7761dfd513
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Currently, ARM Cortex-M image ROMs are linked starting at the flash
device's base address (CONFIG_FLASH_BASE_ADDRESS). This prevents XIP
Zephyr applications from being linked to run from elsewhere on the
flash device. Linking Zephyr applications to run from elsewhere can be
necessary when running under a bootloader (i.e., booting into a Zephyr
application from a bootloader, not using Zephyr as a bootloader).
To enable this use case, add a new config option: FLASH_LOAD_OFFSET.
This option directs the linker to treat ROM as if it started that many
bytes from the base of flash on Cortex-M targets. The option defaults
to zero to preserve backwards compatibility.
Change-Id: I64f82aee257c19c2451f9789b0ab56999775b761
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Some arches may want to define this as an inline function, or
define in core arch code instead of timer driver code.
Unfortunately, this means we need to remove from the footprint
tests, but this is not typically a large function.
Issue: ZEP-1546
Change-Id: Ic0d7a33507da855995838f4703d872cd613a2ca2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This implementation of _tsc_read returns a 64-bit value that
is derived from the 64-bit tick count multiplied by hwcycles per tick,
and then it adds the current value from the 32-bit timer.
This produces a 64-bit time. There is a bunch of math here, which
could be avoided if the CPU is built with Real-Time-Clock option.
EM Starter Kit SOCs don't have this. I don't think Arduino 101 does
either.
See ZEP-1559
Change-Id: I9f846d170246556ac40fe2f45809e457c6375d8c
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Its current placement was splitting the vector table in half.
Move to rodata, a better place for it. There's no requirement for
it to be in the text section.
Change-Id: I67724b2a26a9cb62c2ccd473cb54c53e4f74dc32
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The BSS section needs to use AT> in XIP systems otherwise the LMA
addresses in the ELF binary are wrong, leading to issues if we
try to manipulate the binary with objcopy. The GROUP_DATA_LINK_IN
macro does the right thing here.
This was already done on other arches but ARC was missed.
Change-Id: I93748e919e0b68c1ff2dfb4b85b7064a8d980f3a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
XCC does neither define __BYTE_ORDER__ nor __ORDER_LITTLE/BIG_ENDIAN__ macros.
This resulted in field preempt of thread.base not correctly built from other
union fields prio and sched_locked, which caused wrong scheduling.
Change-Id: I8566ef4a5cf555906c012c4adc488f9afb26c053
Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
1) Fatal errors now all go through _SysFatalErrorHandler. When the
simulator is used, only the death of 'essential' threads will result
in the simulator exiting; some test cases that test exceptions may
actually expect a thread to terminate abnormally.
2) The human readability of the exception errors is improved.
Change-Id: I77f57ea0eae15b0c55237681b959cd21e3fe8c1c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
find_msb_set logic was wrong. find_lsb_set() is now an inline function.
Change-Id: I2c19540907723589298b2f6af2ce1d68704bf1d7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Master branch changed requirements for license headers while this
branch has been in development.
Change-Id: I9bce16ff275057a4bb664019628fc9b6de7aef7c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In order for OpenOCD to have a high-level view of an RTOS, it uses the
GDB protocol to obtain symbols from the system.
The GDB protocol, however, does not allow obtaining fields from
structures directly, and hardcoding offsets is not only brittle (due to
possibly different architectures or changes in the code), it's also
infeasible considering Zephyr is highly-configurable and parts of key
structs can be compiled in or out.
Export an array with offsets for these key structs. Also add a version
element in that array to allow changes in those structs.
Change-Id: I83bcfa0a7bd57d85582e5ec6efe70e1cceb1fc51
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This replaces the hard-coded vector table, as well as the
software ISR table created by the linker. Now both are generated
in build via script.
Issue: ZEP-1038, ZEP-1165
Change-Id: Ie6faaf8f7ea3a7a25ecb542f6cf7740836ad7da3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch moves the include for the generated_dts_board.h inside of
the include/arch/arm/arch.h file. This was done to simplify the
includes required for files. Only two files will include the dts
generated include file directly: arch.h and the linker.ld
Change-Id: I2614f4fd4eeed2ab635a3264d7dac8b83f97b760
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We now use CMSIS for ARM Cortex-M SoCs so we can remove the last bits of
scs and scb.
Jira: ZEP-1568
Change-Id: I0c7c45b0321dc402ed594e9faffb5109922edcf0
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
_SCS_CPACR_CP10_Pos and _SCS_CPACR_CP11_Pos come from scs.h, we have
versions defined in cmsis.h we should be using instead.
Change-Id: Icd8db02000bbc9ef8b2cf89d359e008f62a7d5e9
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Coverted:
_ScbMemFaultMmfarReset
_ScbBusFaultBfarReset
_ScbUsageFaultAllFaultsReset
To use direct CMSIS register access.
Also removed scb.h and references as there is no longer any code in it.
Jira: ZEP-1568
Change-Id: I469f6af39d1bd41db712454b0b3e5ab331979033
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The previous code incorrectly used the value 0xfe to clear the mem and
bus faults. It attempted to handle the address register valid bits
separately, but reversed the bit order.
Jira: ZEP-1568
Change-Id: I240d072610af9979ca93c0081ed862df08929372
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Coverted:
_ScbBusFaultAddrGet
_ScbMemFaultAddrGet
To use direct CMSIS register access
Jira: ZEP-1568
Change-Id: Ic49b3ac3fc4fb63d413f273569c77f6539e4e572
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds support for using device tree configuration files for
configuring ARM platforms.
In this patch, only the FLASH_SIZE, SRAM_SIZE, NUM_IRQS, and
NUM_IRQ_PRIO_BITS were removed from the Kconfig options. A minimal set
of options were removed so that it would be easier to work through the
plumbing of the build system.
It should be noted that the host system must provide access to the
device tree compiler (DTC). The DTC can usually be installed on host
systems through distribution packages or by downloading and compiling
from https://git.kernel.org/pub/scm/utils/dtc/dtc.git
This patch also requires the Python yaml package.
This change implements parts of each of the following Jira:
ZEP-1304
ZEP-1305
ZEP-1306
ZEP-1307
ZEP-1589
Change-Id: If1403801e19d9d85031401b55308935dadf8c9d8
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This private data structure now no longer introduces a typedef or
uses CamelCase. It's not necessary to specify the size of extern
arrays, so we don't need a block of #ifdefs for every arch.
Change-Id: I71fe61822ecef29820280a43d5ac2822a61f7082
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Added a linker script that shall be common to most riscv SOCs.
Linker script also accounts for execution in place in ROM, when
CONFIG_XIP is set.
Nonetheless, riscv32 SOCs (like pulpino) requiring a different
system layout can still define their own linker script.
Change-Id: I3ad670446d439772c29a8204e307ac79643dc650
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
As cpu_idle.S is the only bit of code that is using the SCB asm defines,
so to allow us to remove scb.h in the future lets move the defines that
are used just into cpu_idle.S
Jira: ZEP-1568
Change-Id: I3c3a6f145ec4c1a43f076d079d5fe1694c255b78
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Kill of nvic.h and use either CMSIS helper functions for NVIC or direct
NVIC register access via CMSIS for IRQ handling code.
Jira: ZEP-1568
Change-Id: If21910b9293121efe85c3c9076a1c2b475ef91ef
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move the exception priority related defines into exc.h out of nvic.h
Change-Id: I7ded917a3f6f7cdbc506b2f70c22f37eddc5f5c7
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both
interrupt and exception priorities. We don't need to shift around the
priority values for NVIC_SetPriority.
Jira: ZEP-1568
Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Renames the flash security section so it makes sense for other Kinetis
devices, not just k64. In Kinetis reference manuals, this section is
referred to as the 'flash configuration field'.
Change-Id: I2b7c7cc1ec2541419d77878d367d96c9ceb7a0cf
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Replace _scs_relocate_vector_table with direct CMSIS register access and
use of __ISB/__DSB routinues. We also cleanup the code a little bit to
just have one implentation of relocate_vector_table() on ARMv7-M.
Jira: ZEP-1568
Change-Id: I088c30e680a7ba198c1527a5822114b70f10c510
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
As a first step towards removing the custom ARM Cortex-M Core code
present in Zephyr in benefit of using CMSIS, this change replaces
the use of the custom core code with CMSIS macros in
enable_floating_point().
Jira: ZEP-1568
Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Support using CMSIS defines and functions, we either pull the expect
defines/enum from the SoC HAL layers via <soc.h> for the SoC or we
provide a default set based on __NVIC_PRIO_BITS is defined.
We provide defaults in the case for:
IRQn_Type enum
*_REV define (set to 0)
__MPU_PRESENT define (set to 0 - no MPU)
__NVIC_PRIO_BITS define (set to CONFIG_NUM_IRQ_PRIO_BITS)
__Vendor_SysTickConfig (set to 0 - standard SysTick)
Jira: ZEP-1568
Change-Id: Ibc203de79f4697b14849b69c0e8c5c43677b5c6e
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In preperation for removing the scb/scs layers and using CMSIS directly
lets remove all the _Scb* and _Scs* functions that are not currently
used.
Jira: ZEP-1568
Change-Id: If4641fb9a6de616b4b8793d4678aaaed48e794bc
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
On other targets, CONFIG_TEXT_SECTION_OFFSET allows the entire image to
be moved in memory to allow space for some type of header. The Mynewt
project bootloader prepends a small header, and this config needs to be
supported for this to work.
The specific alignment requirements of the vector table are chip
specific, and generally will be a power of two larger than the size of
the vector table.
Change-Id: I631a42ff64fb8ab86bd177659f2eac5208527653
Signed-off-by: David Brown <david.brown@linaro.org>
_NvicSwInterruptTrigger is only utilized by a testcase for irq handling
on ARM-V7M. Just put the code into the testcase so we dont need to
support an additional interface.
Change-Id: I763c63c32a7a52918250458351d08b8fa54069dd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Replace the existing Apache 2.0 boilerplate header with an SPDX tag
throughout the zephyr code tree. This patch was generated via a
script run over the master branch.
Also updated doc/porting/application.rst that had a dependency on
line numbers in a literal include.
Manually updated subsys/logging/sys_log.c that had a malformed
header in the original file. Also cleanup several cases that already
had a SPDX tag and we either got a duplicate or missed updating.
Jira: ZEP-1457
Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
pulpino soc has custom-extended riscv ISA that is accounted
for if CONFIG_RISCV_GENERIC_TOOLCHAIN is not set.
(ex: bit manipulation asm opcodes)
Change-Id: I4dafc4ebc2fedcc4eb6a3dedd0412816afea6004
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
RISC-V is an open-source instruction set architecture.
Added support for the 32bit version of RISC-V to Zephyr.
1) exceptions/interrupts/faults are handled at the architecture
level via the __irq_wrapper handler. Context saving/restoring
of registers can be handled at both architecture and SOC levels.
If SOC-specific registers need to be saved, SOC level needs to
provide __soc_save_context and __soc_restore_context functions
that shall be accounted by the architecture level, when
corresponding config variable RISCV_SOC_CONTEXT_SAVE is set.
2) As RISC-V architecture does not provide a clear ISA specification
about interrupt handling, each RISC-V SOC handles it in its own
way. Hence, at the architecture level, the __irq_wrapper handler
expects the following functions to be provided by the SOC level:
__soc_is_irq: to check if the exception is the result of an
interrupt or not.
__soc_handle_irq: handle pending IRQ at SOC level (ex: clear
pending IRQ in SOC-specific IRQ register)
3) Thread/task scheduling, as well as IRQ offloading are handled via
the RISC-V system call ("ecall"), which is also handled via the
__irq_wrapper handler. The _Swap asm function just calls "ecall"
to generate an exception.
4) As there is no conventional way of handling CPU power save in
RISC-V, the default nano_cpu_idle and nano_cpu_atomic_idle
functions just unlock interrupts and return to the caller, without
issuing any CPU power saving instruction. Nonetheless, to allow
SOC-level to implement proper CPU power save, nano_cpu_idle and
nano_cpu_atomic_idle functions are defined as __weak
at the architecture level.
Change-Id: I980a161d0009f3f404ad22b226a6229fbb492389
Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
The cortex-m7 is an implementation of armv7-m. Adjust the Kconfig
support for cortex-m7 to reflect this and drop the unnecessary,
explicit, conditional compilation.
Change-Id: I6ec20e69c8c83c5a80b1f714506f7f9e295b15d5
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Precursor patches have arranged that conditional compilation hanging
on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the
config variable to reflect this.
Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Precursor patches have arranged all conditional compilation hanging on
CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support
for ARM ARMv6-M, rename the config variable to reflect this.
Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The ARM code base provides for three mutually exclusive ARM
architecture related conditional compilation choices. M0_M0PLUS,
M3_M4 and M7. Throughout the code base we have conditional
compilation gated around these three choices. Adjust the form of this
conditional compilation to adopt a uniform structure. The uniform
structure always selects code based on the definition of an
appropriate config option rather the the absence of a definition.
Removing the extensive use of #else ensures that when support for
other ARM architecture versions is added we get hard compilation
failures rather than attempting to compile inappropriate code for the
added architecture with unexpected runtime consequences.
Adopting this uniform structure makes it straight forward to replace
the adhoc CPU_CORTEX_M3_M4 and CPU_CORTEX_M0_M0PLUS configuration
variables with ones that directly represent the actual underlying ARM
architectures we provide support for. This change also paves the way
for folding adhoc conditional compilation related to CPU_CORTEX_M7
directly in support for ARMv7-M.
This change is mechanical in nature involving two transforms:
1)
#if !defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
is transformed to:
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
...
2)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
#else
...
#endif
is transformed to:
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
...
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
...
#else
#error Unknown ARM architecture
#endif
Change-Id: I7229029b174da3a8b3c6fb2eec63d776f1d11e24
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The cortex-m related memory map definitions in memory-map.h are all
CPU specific. In preparation for replacing
CONFIG_CPU_CORTEX_M0_M0PLUS with CONFIG_ARMV6_M and
CONFIG_CPU_CORTEX_M4_M4 with CONFIG_ARMV7_M, adjust memory_map.h
conditional compilation to hang on CONFIG_* variables for specific
cortex CPUs.
Change-Id: I2af0b75eaa5b16f88836dbdae41446beacaeba71
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The ICCM memory, when present, can be both written and read,
so changing the attributes to be read-write-execute.
Change-Id: I432bd36f4a6ef632b7c4ce3bf8aa138895d52642
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set have a reduced set of registers and fields compared to
the ARMv7-M compliant processors.
This change goes through all core registers and disables or removes
everything that is not part of the ARMv6-M architecture when compiling
for Cortex-M0.
Jira: ZEP-1497
Change-id: I13e2637bb730e69d02f2a5ee687038dc69ad28a8
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The Cortex-M0(+) and in general processors that support only the ARMv6-M
instruction set can only access the NVIC_IPRn registers with word
accesses, and not with byte ones like the Cortex-M3 and onwards. This
patch addresses the issue by modifying the way that _NvicIrqPrioSet()
writes to the IPRn register, using a word access for Cortex-M0(+).
A similar issue is addressed for internal exceptions, this time for the
SHPR registers that are accessed differently on ARMv6-M.
Reference code taken from CMSIS.
Jira: ZEP-1497
Change-id: I08e1bf60b3b70579b42f4ab926ee835c18bb65bb
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Since the value is treated as uint8_t internally anyway, just use
uint8_t for the input and output parameter types.
Jira: ZEP-1497
Change-Id: I61d68eb39cba5d82dad6ab7593b267c26e003d2b
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
That module is not used anymore: it was introduced pre-Zephyr to add
some kind of awareness when debugging ARM Cortex-M3 code with GDB but
was never really used by anyone. It has bitrotted, and with the recent
move of the tTCS and tNANO data structures to common _kernel and
k_thread, it does not even compile anymore.
Jira: ZEP-1284, ZEP-951
Change-Id: Ic9afed00f4229324fe5d2aa97dc6f1c935953244
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
nano_cpu_idle/nano_cpu_atomic_idle were not ported to the unified
kernel, and only the old APIs were available. There was no real impact
since, in the unified kernel, only the idle thread should really be
doing power management. However, with a single-threaded kernel, these
functions can be useful again.
The kernel internals now make use of these APIs instead of the legacy
ones.
Change-Id: Ie8a6396ba378d3ddda27b8dd32fa4711bf53eb36
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The Cortex-M3/4 kernel was reserving priorities 0 and 1 for itself, but
was not registering any exception on priority 0. Only reserve priority 0
and use it for SVC and fault exceptions instead of priority 1.
Change-Id: Iff2405e27fd4bed4e49ab90ec2ae984f2c0a83a6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
There are now three flags that decide how many priorities are reserved
by the kernel, each one requiring one priority level: Zero Latency
Interrupts, BASEPRI locking (for SVC usage) and faults that are not at
priority -1, so that taking them in an ISR actually triggers the fault
synchronously.
Change-Id: I7f4d760c9110051aeb82dcfd8cd68026a9b74b54
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This allows using it in _EXC_PRIO() instead of hardcoding 2 and 3.
Change-Id: I3549be54602643e06823ba63beb6a6992f39f776
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Move interrupt initialization for the ARC to its own
device. The init function for the arc will be only
doing platform specific operations
Jira: ZEP-1288
Change-Id: Icb04c3622890021c65cd24cecf6cafee6c37caf9
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Drop the unnecessary trailing whitespace formatting in inline asm.
Change-Id: I351df91b7175fe21d268d325865838b4840def8d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Replace the use of a hardwired temporary register in the irq_lock()
implementation with a local variable. This will allow the compiler
more flexibility in register allocation.
Change-Id: Ifbdb52fca1d40404d55934343ac2a8153df7e1a8
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The cortex-m4 irq_lock() implementation uses a movs instruction, thus
clobbering the condition code, but does not include the clobber in the
asm clobber list. This is a bug in the situation where the compiler
schedules a live condition code over the inline lock instructions.
Since the irq_lock() implementation does not need to kill the CC we
simply switch to mov from movs.
Take the opportunity to drop the unnecessay .n and let the assembler
choose an appropriate encoding.
This fixes a bug found by inspection, it has not actually been
observed in real code.
Change-Id: Id60fa3362df9d4bf05c3d5e23066410ede92d73c
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Memory accesses could be reordered before an irq_lock() or
after an irq_unlock() without the memory barriers.
See commit 15bc537712 for the
ARM fix for a complete description of the issue and fix.
Change-Id: I1d96fe0088d90150f0888c2893d017155fc0a0a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Memory accesses could be reordered before an irq_lock() or after an
irq_unlock() without the memory barriers.
See commit 15bc537712 for the ARM fix for
a complete description of the issue and fix.
Change-Id: I056afb0406cabe0e1ce2612904e727ccce5f6308
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Memory accesses could be reordered before an irq_lock() or after an
irq_unlock() without the memory barriers.
See commit 15bc537712 for the ARM fix for
a complete description of the issue and fix.
Change-Id: Ic92a6b33f62a938d2252d68eccc55a5fb07c9114
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Add the missing memory clobber to irq_unlock() in order to prevent the
compiler reordering memory operations over the unlock.
Change-Id: If1d664079796618ed247ff5b33b8b3f85fb7e680
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
The inline asm definition of irq_lock() on the ARM architecture marks
the ASM as volatile which prevents the compiler from removing the
isntruction but does provide any information to the compiler to
prevent the inline ASM instruction being re-ordered relative to other
instructions. The instruction used in irq_lock() do not touch memory,
however in order to acheive their intended purpose they must be
ordered relative to other memory access instruction. This is acheived
by adding the "memory" clobber.
Instances of the compiler inappropriately re-ordering irq_lock() calls
relative to other instructions without this patch can be observed in
the code generated for k_sleep() on NRF51 target boards.
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Change-Id: I9d42d54cd9a50e8150c10ce6715af7ca2f5cfe51
If a particular project needs to add additional data to the
binary image, in most cases the entire linker script needs to
forked into the project space, causing maintenance issues if
the main linker script is changed.
Now we add some Kconfig options to allow a project to specify
some additional linker scripts which get included by the main
one in a few key areas:
1) In the definition to the 'rodata' section, which can allow
additional data to be included in this ROM section.
2) In the definition to the 'datas' section, which allows
additional data to be included in this RAM section.
3) Arbitrary additional sections to be included at the end of
the binary.
For 1 and 2, this is useful to include data generated outside of
the normal C compilation, such as data structures that are created
by special build tools.
3 is useful for including arbitrary binary blobs inside the final
image, such as for peripheral or co-processor firmware.
Change-Id: I5738d3d6da25f5bc96cda8ae806bf1a3fb34bd5d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Sets the interrupt descriptor table in C domain.
Change-Id: Ia8d2f585ebf60464aeedf2a54363e4683cf257a5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The pointer value needs to be dereferenced first.
Change-Id: I80d8a9b4837adfc7d0efc69c229c863d05e52a93
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It is referred to as D/B in the Intel manuals.
Change-Id: If021d875da2d83a256926d9233f1559c8c2ed1db
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Zephyr kernel is unable to compile when CONFIG_RUNTIME_NMI is enabled in
defconfig on ARM's architectures.
This patch addresses the following issues:
* In nmi.c _DefaultHandler() is referencing a function
(_ScbSystemReset()) not defined in Zephyr. This has now been replaced
with sys_arch_reboot.
* nmi.h is included in ASM files and due to the usage of "extern" the
compilation ends with an error. Added the directive _ASMLANGUAGE to
prevent the problem.
Jira: ZEP-1319
Change-Id: I7623ca97523cde04e4c6db40dc332d93ca801928
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Most kernel APIs are now ready for inclusion in the API guide.
The APIs largely follow a standard template to provide users
of the API guide with a consistent look-and-feel.
Change-Id: Ib682c31f912e19f5f6d8545d74c5f675b1741058
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Add Low Power States support to the power shim layer
and show the usage in the quark_se sample.
States are defined as follow:
- SYS_POWER_STATE_CPU_LPS: SS2 with LPSS enabled
- SYS_POWER_STATE_CPU_LPS_1: SS2 with LPSS disabled
- SYS_POWER_STATE_CPU_LPS_2: SS1 with LPSS disabled
Jira: ZEP-994
Change-Id: Ie4b93f6e539cb53fc035be00280b66b2cb0d9fea
Signed-off-by: Julien Delayen <julien.delayen@intel.com>
Updates x86 floating point support to reflect changes that have
been made in recent months.
* Many, many, many cosmetic changes (mostly revisions to comments).
* Elimination of unnecessary function aliases that were needed
to support the task and fiber versions of certain APIs.
* Elimination of run-time code to enable a thread's "FP regs"
option bit if the "SSE regs" option bit was set. The kernel
now recognizes that the thread is using the FPU as long as
either option bit is set. (If the thread has both option bits
enabled this is the same as if only the "SSE regs" bit is set.)
Change-Id: Ic12abc54b6fa78921749b546d8debf23e7ad232d
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
C++ support moved from nanokernel.h to kernel.h.
Change-Id: I5e1631941e26f4ab3f311b680267b743bab15e40
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Symbols now use the K_ prefix which is now standard for the
unified kernel. Legacy support for these symbols is retained
to allow existing applications to build successfully.
Change-Id: I3ff12c96f729b535eecc940502892cbaa52526b6
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
There are a number of data sections that are repeated across
all the linker scripts for various architecture. In practice these
don't always get updated and we have had problems with bit-rot.
Consolidate these to make maintenance easier.
x86 linker scripts now follow the same naming convention and we
get rid of a linker-epilog.h that wasn't necessary and whose purpose
has been lost to the mists of time. If applications want to define their
own sections they should be allowed to. Linker scripts for x86 do not
end with .h any more, they are not C header files even though we use
C's preprocessor.
Issue: ZEP-688
Change-Id: I893eb4619969695c1f980efd7c2ec9fa5dad136d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
All M7 features common to M3/M4 are working. New features like Tightly
Coupled Memory (TCM) are not yet supported.
Change-Id: I5f7b292e70843aec415728f24c973bb003014f4b
Jira: ZEP-977
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Support Cortex-M0, M3/M4, M7 is easier when the memory map is defined in
terms of absolute addresses.
Based work from: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
Change-Id: I860860c369e8bed6c6c23661a15ce464d87ff221
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With this patch we introduce unified kernel support for NIOS II.
Not all test cases have been ported, but the following command
currently succeeds with 43/43 passing test cases:
$ sanitycheck --arch=nios2 -xKERNEL_TYPE=unified \
--tag=unified_capable
Issue: ZEP-934
Change-Id: Id8effa0369a6a22c4d0a789fa2a8e108af0e0786
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ARC does not align data structures by 4 bytes by default.
Add necessary linker sections.
Change-Id: I3bf7aa38b9bc8cba56f824469040c027968fa564
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Not disabling SysTick as it is optional by the spec.
SVC not used as there is no priority-based interrupt masking (only
PendSV is used).
Largely based on a previous work done by Euan Mutch <euan@abelon.com>.
Jira: ZEP-783
Change-Id: I38e29bfcf0624c1aea5f9fd7a74230faa1b59e8b
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
This is used by a test case, and it's better to just put this
here instead of forking the linker scripts.
Change-Id: Ifbb90b73bb26118ae2422cc6feccb3db58a26f2c
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This mechanism was intended to reserve space during the first pass for
certain data structures created by gen_idt, but this is unnecessary.
The only memory addresses that must be fixed between the two passes are the
locations of the interrupt stubs, which are in the .text section much
earlier than the generated data structures; they do not shift.
Change-Id: I3aab00e171e6a9ff439a7af8d69769e4c29337a7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
For XIP images, in order to avoid the situation when
__data_rom_start is 32-bit aligned, but the actual data is placed
after rodata section, which may not end exactly at 32-bit border,
pad rodata section, so __data_rom_start points at data and it is
32-bit aligned.
On non-XIP images this may enlarge image size up to 3 bytes.
This is generally not an issue, since modern ROM and FLASH
memory is usually 4k aligned.
Change-Id: I3d37fccbc610615585d776144ab9e281368258d6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
ARC interrupts can be either level or pulse.
Level interrupts remain asserted until the interrupt service routine
clears the interrupt at the peripheral. This is the default and most
common case.
Pulse interrupts have an extra flip-flop that converts a pulse to a
level. The ARC auto-clears this level as the interrupt service routine
is entered. As such, an interrupt handler for a pulse interrupt need
not clear the interrupt.
It is the rare device that uses pulse interrupts.
Nothing currently calls this inline function so ARC interrupts are
LEVEL by default.
(see ZEP-83)
Change-Id: I09ef86aae1926c1327e82ff99c2f8aa7eabde684
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Binutils ld has an annoying misfeature (apparently a regression from a
few years ago) that alignment directives (and alignment specifiers on
symbols) apply only to the runtime addresses and not, apparently, to
the load address region specified with the "AT>" syntax. The net
result is that by default the LMA output ends up too small for the
addresses generated in RAM. See here for some details:
https://sourceware.org/ml/binutils/2013-06/msg00246.htmlhttps://sourceware.org/ml/binutils/2014-01/msg00350.html
The required workaround/fix is that AFAICT any section which can have
inherit a separate VMA vs. LMA from a previous section must specify an
"ALIGN_WITH_INPUT" attribute. Otherwise the sections will get out of
sync and the XIP data will be wrong at runtime.
No, I don't know why this isn't the default behavior.
A further complexity is that this feature only works as advertised
when the section is declared with the "AT> region" syntax after the
block and not "AT(address)" in the header. If you use the header
syntax (with or without ALIGN_WITH_INPUT), ld appears to DOUBLE-apply
padding and the LMA ends up to big. This is almost certainly a
binutils bug, but it's trivial to work around (and the working syntax
is actually cleaner) so we adjust the usage here.
Note finally that this patch includes an effective reversion of commit
d82e9dd9 ("x86: HACK force alignment for _k_task_list section"), which
was an earlier workaround for what seems to be the same issue.
Jira: ZEP-955
Change-Id: I2accd92901cb61fb546658b87d6752c1cd14de3a
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Interrupt stubs now just push the ISR and parameter onto the stack
and jump to the common interrupt code, never to return.
Change-Id: I82543d8148b5c7dfe116c43f41791f852614bb28
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Merge the Cortex-M3/M4 memory map bits into the master memory map in
prep for it being shared with Cortex-M7 support and Cortex-M0 support
going forward.
Change-Id: I211fc2a2d7d49082b51463f06e6e71cca75d886f
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Due to the memory pool structure only static declaration of
memory pool is possible.
Change-Id: I4797ed88fd2ac3b7812ff26e552e1745611c4575
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
This header has a bunch of data structure definitions and macros useful
for manipulating segment descriptors on X86. The old IDT_ENTRY defintion
is removed in favor of the new 'struct segment_descriptor' which can be
used for all segment descriptor types and not just IRQ gates.
We also add some inline helper functions for examining segment registers,
descriptor tables, and doing far jumps/calls.
Change-Id: I640879073afa9765d2a214c3fb3c3305fef94b5e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add _arch_irq_is_enabled external interrupt API to find out
if an IRQ is enabled.
Change-id: I8ccbaa6d4640c1ab8369d2d35c01a2cfbb02f6cd
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
The Arduino 101 comes with a bootloader that supports DFU
and flashing of all cores using the dfu-util package.
This changes the memory layout of the image built for the
Arduino 101 and remove previous work-arounds to allow booting,
including the version-header section in the linker script.
The bootloader expects the text section at +0x30 from the physical
load address and thus requires special treatment in the linker
script.
Other changes by Andrew Boie:
The flash size parameters were both wrong. X86 side has 192K
of flash from 0x4003000 - 0x40060000, the entire span of
sys_flash1.
ARC side is now the span from 0x40010000 - 0x40030000, 128K.
Change-Id: Iecfa5d2b84a3f522d9eca06268d6b8b71a094aaa
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In 1.0 you could set only one callback on the whole gpio controller. It
was impossible for another sub-system to add another callback, without
overwritting an existing one.
Such API has been obsolete for a long time and no one is using it
anymore. Thus removing it entirely.
Change-Id: I6a17fd99373dc6cef1fa2ebb421e992412d5015e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
The x86 architecture port is fitted with support for the unified kernel,
namely:
- the interrupt exit code now calls _Swap() if the current
thread is not a coop thread and if the scheduler is not locked
- there is no 'task' fields in the _nanokernel anymore: _Swap()
now calls _get_next_ready_thread instead
- the _nanokernel.fiber field is replaced by a more sophisticated
ready_q, based on the microkernel's priority-bitmap-based one
- nano_private includes nano_internal.h from the unified directory
- the FIBER, TASK and PREEMPTIBLE flags do not exist anymore: the thread
priority drives the behaviour
- the tcs uses a dlist for queuing in both ready and wait queues instead
of a custom singly-linked list
- other new fields in the tcs include a schedule-lock count, a
back-pointer to init data (when the task is static) and a pointer to
swap data, needed when a thread pending on _Swap() must be passed more
then just one value (e.g. k_stack_pop() needs an error code and data)
- fiberRtnValueSet() is aliased to _set_thread_return_value since it
also operates on preempt threads now
- _set_thread_return_value_with_data() sets the swap_data field in
addition to a return value from _Swap()
- convenience aliases are created for shorter names:
- _current is defined as _nanokernel.current
- _ready_q is defined as _nanokernel.ready_q
- _Swap() sets the threads's return code to -EAGAIN before swapping out
to prevent timeouts to have to set it (solves hard issues in some
kernel objects).
- Floating point support.
Note that, in _Swap(), the register holding the thread to be swapped in has
been changed from %ecx to %eax in both the legacy kernel and the unified kernel
to take advantage of the fact that the return value of _get_next_ready_thread()
is stored in %eax, and this avoids moving it to %ecx.
Work by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Allan Stephens <allan.stephens@windriver.com>
Benjamin Walsh <benjamin.walsh@windriver.com>
Change-Id: I4ce2bd47bcdc62034c669b5e889fc0f29480c43b
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Commit 3e63a74514 did not revert properly
things.
Change-Id: I792d5698966542ce2cfb9f858c56b30c392f02a2
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
You can't query the LOAPIC for every kind of interrupt that fires,
it has no idea about IRQs that were generated by an 'int' instruction
for example. Extend the semantics of _irq_controller_isr_vector_get()
to return -1 if the vector can't be identified.
Issue: ZEP-602
Change-Id: I1174aa62fbedffdcd329d60da8ef14fabb042dc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These files were almost exactly the same and had already started
bit-rotting (note the missing net_l2 section in linker_harvard.ld)
Issue: ZEP-528
Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This reverts commit d73a9bb9c6.
The patch was intended for 1.6.0 release.
Change-Id: Id42058b746a3d2a54e4b1a2983eb58bd10b1ed40
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:
_EXCEPTION_CONNECT_CODE(handler, vector)
_EXCEPTION_CONNECT_NOCODE(handler, vector)
For x86 exceptions that do and do not push error codes onto
the stack respectively.
In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c
Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.
CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.
Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rather than embedding the ISR stub directly inside the function that
invokes IRQ_CONNECT(), stick all the generated stubs in the
.text.irqstubs section.
In this way, we make things easier to debug since the stub code isn't
mixed in with the "calling" function's assembly, and we no longer
need an instruction to jump over it.
Since these are now in their own section and not embedded inside an
unrelated init function, we unconditionally generate descriptive
symbol names for each stub based on the name of the handler and the
IRQ line.
Example for HPET timer on IRQ #2:
00100440 T _timer_int_handler <-- driver ISR
00100590 T _timer_int_handler_irq2_stub <-- generated stub
Change-Id: I49425aef7775edbca8ad7f61d2d4f9c41cb0d39d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Follow up to TSC decission for further discussion in the networking
WIG.
Change-Id: I148b484dfe308661573e47ed3e60cceed673bddf
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
Nios II appears to have an issue with the 'stbio' instruction.
When executing this code:
0x00400848 <+136>: stbio r3,0(r2)
With these registers:
r2 0x44000c 4456460
r3 0x3 3
The memory location (which is a memory-mapped register in the
NS16550 IP block) ends up with the value 0x103 instead of 0x3 as
expected. Before the instruction ran, the register had 0 in it.
32-bit version doesn't seem to have this problem, use that
everywhere for now. This issue has been reported to Altera.
Change-Id: I4ff0ff4cc7f9b18006d3f7a777eb292924843644
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having two parallel implementations is a maintenance issue, especially
when some strategically placed #ifdefs will suffice.
We prefer the ASM versions for SYS V, as we need complete control of
the emitted assembly for interrupt handling and context switching.
The SYS V code is far more mature. IAMCU C code has known issues with
-fomit-frame-pointer.
The only difference between the two calling conventions is that the
first three function arguments are provided in eax, edx, ecx instead
of on the stack.
Issue: ZEP-49
Change-Id: I9245e4b0ffbeb6d890a4f08bc8a3a49faa6d8e7b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Net core then does not know anything about l2 related logic.
For instance ARP is used in ethernet l2 API and nowhere else.
This will be helpful when adding different technologies altogether.
Currently, only SLIP driver is enabled to use relevant l2 layer.
Change-Id: I03c93326321028d04222733ca4083e3c6b785202
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will be used by the new network stack to relate a device to actual
network context, and used in the different layers (mac, ip ...).
Change-Id: I30c08fa975314544c36b71636fd9653d562891b3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Used by ARC, ARM, Nios II. x86 has alternate code done in assembly.
Linker scripts had some alarming comments about data/BSS overlap,
but the beginning of BSS is aligned so this can't happen even if
the end of data isn't.
The common code doesn't use fake pointer values for the number of
words in these sections, don't compute or export them.
Change-Id: I4291c2a6d0222d0a3e95c140deae7539ebab3cc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We now allow use of -mgpopt=global and -mgpopt=data. The 'global'
option is now the default instead of compiler-default local, expanding
global pointer usage to all small data in the system.
For systems where all RAM is less than 64K, the 'data' option may be
appropriate.
Some fixes had to be made to the system in order to get around some
issues:
* prep_c.c no longer uses fake linker variables to figure out the size
of data or BSS, as these gave the linker fits as it tried to compute
relative addresses to them.
* _k_task_ptr_idle is create by sysgen and placed in a special section.
Any small data in a special section needs to be declared extern
with __attribute__((section)) else the compiler will assume it's in
.sdata.
* same situation with extern references to k_pipe_t (fixed pipe_priv
test)
For legacy applications being ported to Nios II which do things that
freak out global pointer calculation, it can be disabled entirely.
Change-Id: I5eb86ee8aefb8e2fac49c5cdd104ee19cea23f6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
needs to be 0x8000 after .sdata and .sbss sections since
register offsets are 16-bit signed values.
Change-Id: Ia7486d32af81e54a6ebac6be7ec308dfdeafe79e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The caches get initialized on boot and flushed after XIP copy
takes place.
Change-Id: I642a14232835a0cf41e007860f5cdb8a2ade1f50
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Updates the exception stack frame structure to include floating point
registers.
Change-Id: I0fef784cf4d91dda245180abd75bfd9221825fba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We are not going to handle unimplemented math instruction
exceptions at runtime. Remove remaining comments and exports
related to this. We don't need to leave a gap in the exception
stack frame for it either.
Change-Id: I4f1f3980a0e43bbf6f2f7488a9182f7acb06be05
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are no-ops since this is not an arch that isn't byte-
addressable.
Change-Id: I09b0fd8b8d85f67bcca2dcb6ebc35843c19afa45
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Supports Internal Interrupt Controller only for now; EIC
supoort tracked in ZEP-258.
Change-Id: I2d9c5180e61c06b377fce4bda8a59042b68d58f2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The technical manuals and example HAL code frequently refer to
register bank numbers from some base address. Add these helper
functions to read and write registers correctly using this
notation.
Change-Id: Ia082f5cc89081fcea2cb6ad8204c1b9b2650d3fd
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The KEEP() is only necessary for the exception entry point
as it sits at a magic memory address and isn't referenced by
other code.
Change-Id: I8443e8aa23059b65eaf9c5a1cf3f9b14b04737d5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This isn't directly referenced by other code in the binary,
it just sits at a magic memory address. Make sure gc-sections
doesn't throw it away.
Change-Id: I1c00a163dbf2eb4866ebadc7f1d70bcc6845b8d1
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These aren't valid in all circumstances; the reset vector in most cases
needs to be in ROM.
Change-Id: I83df8762eecc53c99af92f3b0972dfbafac457fb
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The problem is doxygen's parser is getting confused by constructs as:
static inline __attribute__((always_inline))
void sys_out8(uint8_t data, io_port_t port)
{
_arc_v2_aux_reg_write(port, data);
}
Too many words at the beginning of the function definition. So change
to use the macro ALWAYS_INLINE (which is already defined to mean
'inline __attribute__((always_inline))`.
Kills:
sys_io.h:37: warning: documented symbol `static inline void sys_out8' was not declared or defined.
sys_io.h:47: warning: documented symbol `static inline uint8_t sys_in8' was not declared or defined.
sys_io.h:58: warning: documented symbol `static inline void sys_out16' was not declared or defined.
sys_io.h:68: warning: documented symbol `static inline uint16_t sys_in16' was not declared or defined.
sys_io.h:79: warning: documented symbol `static inline void sys_out32' was not declared or defined.
sys_io.h:89: warning: documented symbol `static inline uint32_t sys_in32' was not declared or defined.
sys_io.h:120: warning: documented symbol `static inline int sys_io_test_bit' was not declared or defined.
sys_io.h:133: warning: documented symbol `static inline int sys_io_test_and_set_bit' was not declared or defined.
sys_io.h:146: warning: documented symbol `static inline int sys_io_test_and_clear_bit' was not declared or defined.
sys_io.h:161: warning: documented symbol `static inline void sys_write8' was not declared or defined.
sys_io.h:171: warning: documented symbol `static inline uint8_t sys_read8' was not declared or defined.
sys_io.h:182: warning: documented symbol `static inline void sys_write16' was not declared or defined.
sys_io.h:192: warning: documented symbol `static inline uint16_t sys_read16' was not declared or defined.
sys_io.h:248: warning: documented symbol `static inline int sys_test_bit' was not declared or defined.
sys_io.h:261: warning: documented symbol `static inline int sys_test_and_set_bit' was not declared or defined.
sys_io.h:274: warning: documented symbol `static inline int sys_test_and_clear_bit' was not declared or defined.
Change-Id: Id10e9b6cd44a370ccc732c17b23fb66bd1845205
Signed-off-by: Inaky Perez-Gonzalez <inaky.perez-gonzalez@intel.com>
We will require 6 variables to be defined by SOC-specific
linker script; these values in turn can be pulled from
defines in layout.h.
To help position code correctly we define two new ELF sections
for this arch, 'reset' and 'exceptions'.
Change-Id: Idffbd53895945b7d0ec0aac281e5bf7c85b4b2c2
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This header was pulled in verbatim from Altera HAL and had
some style and naming issues. The inline functions or macros
which read registers can now be used in expressions.
Change-Id: I7a463717051efd2f9dd36e8a84d357852fbf9215
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In scenarios where device PM is enabled and dynamic irqs are
used, move the irq to vector table to RAM and keep it updated,
so that we can use this to restore IOAPIC/LOAPIC vector entries.
Jira: ZEP-224
Change-Id: I0d4350d4e30f8ca337a2a1d4f012748c3cb450f4
Signed-off-by: Jithu Joseph <jithu.joseph@intel.com>
For EM Starter Kit, one of the SOC choices has DRAM and no FLASH.
If FLASH_SIZE is 0, the linker command file will create
SRAM, ICCM and DCCM memories (and no FLASH). SRAM is really DRAM.
Also, the linker.ld file is extended to handle microkernel
objects.
linker_harvard.ld has "all rights reserved". added to banner.
Change-Id: Ia433578b94ce91722f3670819f44befafeecf878
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
I've tested that CONFIG_XIP does work with Harvard.
User's can build CONFIG_XIP=y, and then have their bootable image
be placed in SPI-FLASH. A bootloader will load up ICCM contents.
Zephyr will then copy remaining data from ICCM to DCCM.
This takes a bit of ICCM memory to do it, but it will work.
Change-Id: Ic1cd201d19aab9083d63334527d9d68f4edc6075
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Some ARC CPUs can be built with separate instruction bus
and data bus (i.e. Harvard Architecture). Such systems
have only ICCM and DCCM memories. When CONFIG_HARVARD
is defined, the initial stack pointer is set to the
TOP of the DCCM memory. Currently there is no SOC that
existing in Zephyr tree that sets CONFIG_HARVARD, but
this will be coming soon.
Change-Id: I2016d1f472fbdad683a964aa0b65c5263ecfb6cf
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
The stub label is created with ISR and IRQ number since the same
ISR can be used by several IRQs
Change-Id: I0ea909fddbce7a70c754befd095b7a3b36fffab4
Signed-off-by: Fabrice Olivero <fabrice.olivero@intel.com>
The ARC CPUs have several other features controlled by aux registers.
Specifically, I will be needing ones for i-cache, d-cache and various
BUILD registers that indicate which features are present.
Change-Id: If15a330f4ea5aa519655f88526fbb5f600d7cc0b
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
Nios II has no special instructions for testing bits, ffs, etc.
However, when poking memory-mapped peripherals, special *io variants
of ld and st instructions must be used to avoid issues with the
caches.
find_msb_set / find_lsb_set are implemented using universal GCC
compiler built-ins. It's not clear why this approach was not taken
on other arches.
The sys_in/sys_out/sys_io functions are completely removed as there
is no concept of these on Nios II.
sys_read/sys_write functions implemented using special GCC builtins
for the Nios II so that we don't have to use inline assembly.
Rest of the operations implemented in C, there is no requirement that
they be atomic.
Change-Id: Ic251fc7d7f342543dace4ccb3e429937b303215e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This file is taken verbatim from the Altera Nios II HAL
source and includes various useful processor defines
and macros.
Change-Id: Idbf0b49bebe33bb5a53f5155d927bafadda9a2fe
Origin: nios2.h Altera Nios II HAL
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
BSP builds for Nios II generate a linker.h and system.h which reflects
the configuration for that CPU. This can vary depending on how the CPU
is wired up in QSYS, so it needs to be at the SOC level--we essentially
treat any given CPU configuration as a SOC in Zephyr build terms.
Include these files from <arch/cpu.h>.
Change-Id: I12f76600107fec1a14a2f9cb82b0f55915ec03a6
Origin: Altera Quartus tools, machine generated
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Got lost in the .gitignore when these files had .cmd
extension.
Change-Id: I8a8d51014b621026b739525f3f9a3e8a20cb5ad0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ZEP-252 will handle implementation of the code here.
Change-Id: I3e9a6c7cdf2d5a3b0240317b772628fead528095
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
At the moment this just jumps into prep_c, with comments left
on other things that need to be done. Having this here ensures that
the early boot code isn't discarded by gc-sections.
vector_table.c removed, it isn't the right approach for this CPU.
Proper method for initializing reset and exception vectors still
being investigated.
Change-Id: Id7965c671f1a55c42ecfb65119497405a646bec4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Avoids confusion with .gitignore rules, which were inadequate to
cover all the places where these files are found. At least in
VIM, these files are now syntax highlighted correctly.
Change-Id: I23810b0ed34129320cc2760e19ed1a610afe039e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Basic build framework for Nios2. Everything is stubbed out,
we just want to have a build going so that we can start to
parallelize implementation tasks.
This patch is not intended to be functional, but should be
able to produce a binary for all the nanokernel-based
sanity checks.
Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Indentation should be with tabs only (these lines were with tab +
spaces).
Change-Id: I8f199b1d6972b02513e4c293636606f481641266
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
To boot zephyr on the Arduino 101 running the original bootloader
which supports DFU, set the following in your application configuration
file:
CONFIG_SS_RESET_VECTOR=0x40034000
CONFIG_PHYS_LOAD_ADDR=0x40010000
CONFIG_VERSION_HEADER=y
Jira: ZEP-219
Change-Id: Ia015a7b6fce888b49ed22c558de992132d4713ea
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove hardcoding and make the values configurable. Also make the
Kconfig variables consistent with other architectures.
Change-Id: I69334002303d4d8abaf7363d9134fd5f46ce4eeb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Many sub-systems might require to set a callback on different pins.
Thus enabling it via changing the API.
It is also possible to retrieve private-data in the callback handler
using CONTAINER_OF() macro (include/misc/util.h).
Former API is still available, and is emulated through the new one.
Using both should not be a problem as it's using new API calls.
However, it's now better to start using the new API.
Change-Id: Id16594202905976cc524775d1cd3592b54a84514
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Introduce an x86 interrupt stack frame that contains more information
than the non-debug one, namely the caller-saved GPRs, as well as an API
to retrieve it. Able to handle nested interrupts stack frames.
Change-Id: If182aaa2f34e4714b16ca65ff79da63b72d962f7
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
It wasn't correct to add the size of the long jump instruction
as it *replaces* a short jump instead of just being after it.
So redefine this to be the difference in size between these
two instructions.
Change-Id: I65be2afab19d9cd8b096551acde0156f0503df87
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
ARC CPU has stack checking feature that allows to trigger an exception
whenever the stack is incorrectly accessed.
This patch implements the stack_top and stack_base register updates on
context switches, and activates the Stack Checking bit of STATUS32
register when the CPU is in the context of a fiber or task.
As GCC accesses the non-yet allocated stack with frame pointer enabled,
this patch also add the omit-frame-pointer gcc flag in order to work
properly.
Change-Id: Ia9e224085a03bd29d682fb8f51f8e712f2ccb556
Signed-off-by: Alexandre d'Alton <alexandre.dalton@intel.com>
The nmi_on_reset.S functions are used by all ARM platforms. It
makes no sense to repeat the same code for all platforms. Moving
the code from each SOC implementation to arch/arm/core.
The same treatment for the NMI_INIT() macro. Moving it from a per
SOC implementation to the include/arch/arm/cortex_m/nmi.h.
Change-Id: I574d8880a44046cc7b9e1b635e80d6e83657b8c1
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Use of these is the mark of a deranged imagination.
Change-Id: Ib4b5f78cf61c016e333288090b397e9a3e0b8a40
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
These are guaranteed to work for bitfields that are
larger then 32 bits wide.
Change-Id: I39a641f08a255478fae583947bced762950d12ff
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The app-facing interface for configuring interrupts was never
formally defined, instead it was defined separately for each arch
in their respective arch-specific header files. Occasionally these
would go out of sync.
Now there is a single irq.h header which defines this interface.
To avoid runtime overhead, these map to _arch_* implementations of
each that must be defined in headers pulled in by arch/cpu.h.
Change-Id: I69afbeff31fd07f981b5b291f3c427296b00a4ef
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Looking at the IDT in a debugger is confusing, add a pretty-printing
function.
Change-Id: Iacc5e204e5d11e3e875c75ddf6d2e2e80b230299
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We have a new policy: users should not be able to configure
an interrupt with "forbidden" priority levels, and any priority
levels with special semantics will be activated by flags.
Change-Id: I757c19cfedcb1d0938eaf4da348ddafb71b3e001
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Having priority levels 0 and 1 reserved on x86 due to implementation
details on how the CPU uses the vector table is confusing to users,
and makes it unnecessarily difficult to share drivers between arches.
Now on x86, priority levels 0 and 1 are available. Semantically, all
priority levels have had 2 subtracted from them.
It is no longer necessary to specify a priority level when the
vector itself is specified. If an IDT entry has a specific vector
associated with it, any priority argument is simply ignored.
In gen_idt, some simplifications have been made:
- The printed representation of a generated entry now fits on one line
- Some checks being done in validate_priority() were redundant, as
generate_interrupt_vector_bitmap() also ensures that there are
sufficient free vectors within a priority level.
Change-Id: I26669d8ee0a53f48fbc2283490a8c42d8b1daf8e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It's not a function and requires all its arguments to be build-time
constants. Make this more obvious to the end user to ease confusion.
Change-Id: I64107cf4d9db9f0e853026ce78e477060570fe6f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Most systems have far less than 256 IRQ lines available, so
save some bytes in ROM by making this a config option.
On systems with MVIC, omit the table entirely as the mapping
is fixed.
The build cmd_gen_idt is slightly easier to read and will fail
immediately if any of the commands in the sequence error out.
Change-Id: I411f114557591e5cd96b618e6f79f97e8bedadf0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This bitfield is only needed to find unused vectors in the IDT
for installing dynamic interrupts.
Change-Id: I34ecd330774a0e50f240b4396527682eded29627
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add sys_exc_connect() (and its x86-compatible alias nanoCpuExcConnect())
that allows connecting an exception handler at runtime.
The current implementation is a bit of a bastard, to avoid disturbing
the current implementation of the exception handlers. Instead of hooking
_exc_wrapper() in all vectors and adapting the exception handlers, the
current exception handlers are still hooked directly in the vectors.
When an exception is hooked at runtime, _exc_wrapper() gets installed in
the vector and the real handler gets inserted in _sw_exc_table; this
means that the scheme only works with non-XIP kernels.
This should be enhanced so that _exc_wrapper() is hooked in all vectors,
and that current exception handlers (for faults mostly) are reworked to
be inserted in the _sw_exc_table and wrapped in _exc_wrapper().
Change-Id: Icaa14f4835b57873d2905b7fbcbb94eeb3b247d1
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Rename the function and allow it to handle the 'type'
argument, which is ignored in this case.
Change-Id: I3d3493bea4511b2d026747505e7e52c5acc85012
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The ESF was built using the 'alias' names of the GPRs (a1, lr, pc, etc)
rather than their 'real' name (rN).
Change-Id: I49cae5e94869a79a3165dc7f2347d8cec39dbf67
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
On ARM, GPRs are often known by two names. E.g. the stack pointer is
both 'sp' and 'r13', the first parameter to a function 'a1' and 'r0',
etc. This macro allows defining them in a data structure, e.g. in the
ESF, without having to create a union, use the correct type, etc: it is
less error-prone and makes for shorter code.
sys_define_gpr_with_alias(name1, name2)
Change-Id: Ie4a6caa1ac23f26be4f7f0e05e9265f2655062cc
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The image will be linked at a different address and with different
ROM/RAM sizes to allow running a bootloder image that loads a payload
image. The addresses/sizes depend on if it is a XIP image or not
(CONFIG_XIP), and in the case of a XIP image, if it is a bootloader
image (CONFIG_IS_BOOTLOADER) or not.
In the case of a bootloader, it is given the full ROM and
CONFIG_BOOTLOADER_SRAM_SIZE kB of SRAM. When not a XIP image, it is given
the full SRAM minus CONFIG_BOOTLOADER_SRAM_SIZE kB, and is linked at the
start of SRAM.
Change-Id: Ibbb693c7bff022f313dac40f21c04a61f4bed115
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds C++ support to the build system.
Change-Id: Ice1e57a13598e7a48b0bf3298fc318f4ce012ee6
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds extern "C" { } blocks to header files so that they can be
safely used by C++ source files.
Change-Id: Ia4db0c36a5dac5d3de351184a297d2af0df64532
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We can save a great deal of RAM this way, it only needs to be
in RAM if dynamic interrupts are in use.
At some point this config option broke, probably when static
interrupts were introduced into the system.
To induce build (instead of runtime) errors when irq_connect_dynamic()
is used without putting the table in RAM, the dynamic interrupt
functions are now conditionally compiled.
Change-Id: I4860508746fd375d189390163876c59b6c544c9a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is needed for setting up an image that runs entirely from SRAM,
including its vector table. Ensure integrity of relocated vector table
by using serialization instructions when moving the vector table to
ensure it has been fully written before something makes use of it.
Change-Id: I00c600d557c87c75847f67fbc42f1c2c16157608
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This option misunderstands how XIP works. The IDT is ALWAYS in ROM,
the question is whether crt0 will copy it into RAM or not. You can't
save ROM space in this way.
Change-Id: I58025e3d71ead35730d0a5026213299b4fcb5eb9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The interrupt API has been redesigned:
- irq_connect() for dynamic interrupts renamed to irq_connect_dynamic().
It will be used in situations where the new static irq_connect()
won't work, i.e. the value of arguments can't be computed at build time
- a new API for static interrupts replaces irq_connect(). it is used
exactly the same way as its dynamic counterpart. The old static irq
macros will be removed
- Separate stub assembly files are no longer needed as the stubs are now
generated inline with irq_connect()
ReST documentation updated for the changed API. Some detail about the
IDT in ROM added, and an oblique reference to the internal-only
_irq_handler_set() API removed; we don't talk about internal APIs in
the official documentation.
Change-Id: I280519993da0e0fe671eb537a876f67de33d3cd4
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
We are checking against the wrong option, which does not exist.
Change-Id: Ied24daa0930bc4629750ea90f3ac6dbc45e87fff
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
On SysV ABI, the NANO_ESF parameter is passed in via the stack.
For IAMCU, this is instead expected to be in EAX.
_ExcEnter is currently using EAX to stash the return address of
the calling stub while it does a stack switch. Change it to use ECX
for this purpose, and if we are running with IAMCU place the
parameter in EAX instead of pushing it.
The output of the fault handler has been cleaned up a bit and it
now also includes the code segment.
Change-Id: I466e3990a26a1a82dd486f3d8af5395eab60b049
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This was never implemented on ARC/ARM and has been superseded
by irq_offload().
Some checks that were only done with CONFIG_LOAPIC_DEBUG fall
under the category of 'shouldn't ever happen' and have been
converted into assertions, instead of propagating return values
which are largely never checked.
Change-Id: I4eedca05bb7b384c4f3aa41a4f037f221f4a9cfe
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
If we are not doing any dynamic interrupts or exceptions, we
can put the IDT in ROM and save a considerable amount of RAM,
up to 2K if the IDT is the default size of 256 entries.
The _interrupt_vectors_allocated table can also be put in ROM
if we're not using any dynamic interrupts.
We introduce a new Kconfig option to force the IDT to be in RAM
for situations where no dynamic IRQs are used, but ROM footprint
needs to be conserved.
Change-Id: I38c9f1a8837b4db9f3dea1caa008374a26cbbf1d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The routines _int_latency_start() and _int_latency_stop() have been
replaced by macros that evaluate to nothing when the kernel config
option INT_LATENCY_BENCHMARK is not enabled thereby giving a performance
boost to the x86 versions of irq_lock() and and irq_unlock().
Change-Id: Iabfa7bf001f5b8396e7bcf5eebd6b1aa342bac46
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change terminology and use SoC instead of platform. An SoC provides
features and default configurations available with an SoC. A board
implements the SoC and adds more features and IP block specific to the
board to extend the SoC functionality such as sensors and debugging
features.
Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for compilers conforming to the IAMCU calling convention
as documented by
https://github.com/hjl-tools/x86-psABI/wiki/iamcu-psABI-0.7.pdf
Change-Id: I6fd9d5bede0538b2049772e3850a5940c5dd911e
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Add null definitions for the interrupt latency measurement API so we
can remove compile fences in C code.
Change-Id: If86eedf79afcb49002108814dd4fb864956eb667
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Removed old style file description and documnetation and apply
doxygen synatx.
Change-Id: I3ac9f06d4f574bf3c79c6f6044cec3a7e2f6e4c8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Removes the 'priority' parameter from the IRQ_CONFIG macro.
This parameter was not used anymore in any architecture.
The priority is handled in the IRQ_CONNECT macro.
The documentation is updated as well.
Change-Id: I24a293c5e41bd729d5e759113e0c4a8a6a61e0dd
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Adds static irq support for the Quark SE platform for the ARC core.
New linker sections and sw isr table initialization is needed to support
static IRQ.
Change-Id: I82af98a189f5a156e7f1018f3ecdbfa73ad3e6ef
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Adds support for static IRQ handler initialization.
Currently, IRQ_CONNECT and IRQ_CONFIG macros are emulating static
behavior through dynamic initialization.
This commit updates the macros to get real static initialization.
IRQ handlers must be assigned at build time.
Change-Id: Ia07fb25a5e4dae489f84ffcedb28007ee18a3b82
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
IRQ_CONNECT_STATIC takes 6 arguments on other
architectures, but the ARC one had only 5.
Change-Id: I257e8db12582ee2d6f93bba63af9aa597197a53d
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
With MVIC these can't be arbitrarily assigned and the vector must be
<irq num> + 0x20.
The correct number of vectors is now set for footprint-min on D2000.
Change-Id: Ibf59921dbc438c7465b7050dd74d0badc9a91fc3
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Uses the "trap_s" exception to simulate entry into IRQ context;
offloaded functions run on the FIRQ stack.
Change-Id: I310ce42b45aca5dabd1d27e486645d23fa0b118f
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This way, it does not fall in the middle of a group, like the RAM group
and as a side-effect potentially move the dot (current address pointer).
Change-Id: Iefbff8bbeadfc740dee61154d7db99b7b7aad6d6
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The linker scripts for the quark_se_ss and generic_arc platforms are the
exact same, so extract the contents in an includable file.
Change-Id: I2cb90a6f819b12db77880228e41ff14c9755d59a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Initialization level can be one of five predefined.
Init priority is numeric from 1 to 99. If init level or priority
is defined wrong, linker prints out the message and stops.
Change-Id: I165a32ffb668cda983fd48eb2aa7b94998e31a18
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Do not depend on environment variables and use a kconfig variable
for defining the architecture.
In addition, remove the X86_32 variable, it just duplicates X86 for
not good reason, at least until start supporting MCUs with 64bit.
Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
These should now work for drivers written for other arches.
Still a hack to do all the IRQ setup at runtime.
Change-Id: I9717f74abef3b9934f9a1c0acbd76d960ed7a3cb
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The new flags parameter needs some documentation.
Change-Id: I24dc9df62323957bb4b294adf27487df3f76ea01
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Was exposed when building with clang. No need for a second const.
Change-Id: Ie97f6a4756aff62ce969e3eb786593f2fc175a56
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Flags allow passing IRQ triggering option for x86 architecture.
Each platform defines flags for a particular device and then
device driver uses them when registers the interrupt handler.
The change in API means that device drivers and sample
applications need to use the new API.
IRQ triggering configuration is now handled by device drivers
by using flags passed to interrupt registering API:
IRQ_CONNECT_STATIC() or irq_connect()
Change-Id: Ibc4312ea2b4032a2efc5b913c6389f780a2a11d1
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
I/O ports are not memory and thus such asm instruction cannot follow
such constraint. Plus, usual BT* instruction can be used on normal
registers.
Change-Id: Ie3aad668173962a0a90e7cb11231c7843836d412
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Let the compiler decide about the registers to use, depending on which
functions those are called from (as they might be already in use or
not).
Change-Id: I00afa0f82c740c8ea70133d85ab67e9cb117187d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Remove prototype support for C++ constructors, since it is not well
designed. Device drivers (or other application code) that requires an
automatic initialization capability should use the device initialization
macros instead.
Note: Support for C++ constructors may be re-introduced at a later date.
However, a number of issues need to be settled, such as when the
constructors are invoked and what context they run in. (Running them
during nanokernel initialization, as was previously done, is probably
not the right approach.)
Change-Id: If6d27ac16b485cb39d5ec34084e9d0f1991074f4
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Since commit 3d7b21b69e the 'priority' parameter is used by the macro
IRQ_CONNECT_STATIC. This patch fixes the macro documentation which
says it is ignored.
Change-Id: I56eec49466a33441fa1822af78956ebb7f5c24ce
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
As the system always operates in ring 0, neither the SS nor ESP registers
are pushed onto the stack when an exception or an interrupt occurs.
However, as the ESP field is still relevant to debugging fatal errors, a
place has been carved for it in the NANO_ESF.
Change-Id: Ibb2578c69fa6365fd6e9dbf7b51f461063dadc68
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
As page fault exceptions can not occur in the system as it is currently
designed, there is no need to track the CR2 register as part of the
exception stack frame.
Change-Id: I75d7a74c5d2c6efcc0e9141d2662861bc2052629
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Implementation of the sys_arch_reboot() call for galileo, using the
RST_CNT register (I/O port 0xcf9).
Change-Id: I00fbf4aaaf746f640674da6880e1d6c5aa230e06
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
It can be used by some subsystems even in a microkernel.
Change-Id: I07241aab94ecf67c94dce2d05f2cd774b2a6b044
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
These symbols have more meaningful names when trying to figure out where
the ROM/RAM starts/ends, rather than relying on e.g. __data_rom_start for
the end of the ROM (__data_rom_start is the beginning of the data in
ROM, thus is not part of the image).
Change-Id: I4aa0354ee414fd0d46d0f40952e091ba090e7bce
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This option is not building and currently not supported, removing
it because there does not seem to be a use case for it.
Change-Id: Idb8ffedf83f43cffc68a01573c6f2d1a90fc40fb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
We are interested in supporting some XIP x86 platforms which are
unable to fetch CPU instructions from system RAM. This requires
refactoring our dynamic IRQ/exc code which currently synthesizes
assembly language instructions to create IRQ stubs on-the-fly.
Instead, a new approach is taken. Given that the configuration at
build time specifies the number of required stubs, use this
to generate a build time a set of tiny stub functions which simply
push a 'stub id' and then call common dynamic interrupt code.
The handler function and handler argument is saved in a table keyed by
this stub id.
CONFIG_EOI_HANDLER_SUPPORTED removed, the code hasn't been conditionally
compiled for some time and in all cases we call _loapic_eoi() when
finished with an interrupt.
Some other out-of-date verbiage in comments related to supporting
non-APIC removed.
Previously, when dynamic exceptions were created a pointer would
be passed in by the caller reserving ram for the stub code. Since
this is no longer feasible, two new Kconfig options have been added.
CONFIG_NUM_DYNAMIC_EXC_STUBS and CONFIG_NUM_DYNAMIC_EXC_NO_ERR_STUBS
control how many stubs are created for exceptions that push
an error code, and no error code, respectively.
SW Interrupts are no longer triggered by "int <vector>" hard-coded
assembly instructions. Instead this is done by sending a self-directed
inter-processor interrupt from the LOAPIC, using a new API
loapic_int_vect_trigger(). In this way we get rid of dynamically
generated code in irq_test_common.h.
All interrupts call _loapic_eoi() when finished, since this is now
the right thing to do for all IRQs, including SW interrupts.
_irq_handler_set() for x86 no longer requires the old function pointer
to be supplied.
Change-Id: I78993d3d00dd153c9051c518b417cce8d3acee9e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit adds asm implementation for the methods:
sys_io_set_bit
sys_io_clear_bit
sys_io_test_bit
sys_io_test_and_set_bit
sys_io_test_and_clear_bit
Change-Id: I144568e113316fa43d943cdc5457cb17e66839c3
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
ARC targets now have access to the address types 'paddr_t' and 'vaddr_t'.
Change-Id: I2cccddbdd76771529e4501aaee6cb2a2b640013e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
ARM targets now have access to the address types 'paddr_t' and 'vaddr_t'.
Change-Id: Ic7225647f3776d4afa853cf2c4a19699b656866a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This makes the types 'paddr_t' and 'vaddr_t' available via nanokernel.h.
Change-Id: I75b81356566e2063979f2ec46f326d606638efa2
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This was only needed for the older 8259A style PICs which are no
longer supported.
Since we now just support APIC, we always just call loapic_eoi which
no longer requires an argument and informs the IOAPIC that the interrupt
is complete if necessary.
Change-Id: I15c9b7b4f03b872656220af32220b62e043bfa6b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This patch enables defining microkernel events within source code.
This is similar to other private kernel object patches.
The test has been modified a little bit due to the fact that
the event ID is now a memory address, instead of numeric ID.
Change-Id: Ie3c8d4f4e459d9c631e50bb242cf7a05ca8ea82c
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Updates the 'gen_idt' tool to generate a mapping of IRQ numbers to
interrupt vector IDs, thereby allowing the IRQ priority to be utilized
when statically connecting an interrupt.
Change-Id: I2e54ceb65145682820dfbd8ca1ee6ec68d71ce1a
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Change-Id: Ie051000e3d3f0f5bdc330d0265010c37acb873bd
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I819d13f0d7a23e3a61dcda6a3ced18810b192158
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Change-Id: I6da43e41f9c6efee577b70513ec368ae3cce0144
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Updates several files to remove mention of Diab toolchain
support, which is no longer supported. These changes do not
affect system operation.
Change-Id: If9de85e595f6685295e565bc94ca17f51d87513f
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
In order to have drivers that are usable cross architecture the
signature for IRQ_CONFIG needs to be the same to avoid #ifdef hell in
the driver code based on architecture.
Update the macro and it usage for existing drivers
Change-Id: I22e142b21d4e984add231d1dbd97020e4823985f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Introduces the SYS_DEFINE_DEVICE() macro, which supports 5 distinct
levels of device initialization and 100 priorities within each level.
Note: The existing init macros (e.g. nano_early_init()) have been
adapted to utilize the enhanced initialization model, but will
eventually be retired.
Change-Id: If677029d8b711a3fae9b2f32b5470cd97d19aeda
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Drivers do it by themselves, usually either in a dedicated irq
configuration function or direcly in their initialization routine.
Change-Id: Id1cca1a1e3e3f36264d99d1d2f2d651d84e0687e
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This functions - reusing _arc_v2_aux_reg_* ones - will ease porting
drivers to ARC architecture hiding arch specific calls under generic
functions. On ARC, auxiliary registers is conceptually comparable to
x86 ports, thus the possibility to bring sys_in/sys_out to access those.
Change-Id: Ic5c0fc41f32ec4ad861dbb58cd8defaf4497bc03
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Change all the Intel and Wind River code license from BSD-3 to Apache 2.
Change-Id: Id8be2c1c161a06ea8a0b9f38e17660e11dbb384b
Signed-off-by: Javier B Perez Hernandez <javier.b.perez.hernandez@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Updates the 'gen_idt' tool to generate a bitmap of (statically) allocated
interrupt vectors that is linked into the final image in a manner similar to
the static IDT. The kernel then uses this bitmap when dynamically connecting
an interrupt vector, thereby preventing the dynamic irq connections
from clobbering the static irq connections.
Change-Id: I0a8f488408dad4912736865179f32f63ff1ca98f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Adds two new fields to the ISR_LIST structure (irq and priority) to allow
the decoupling of the vector ID and priority from the IRQ number at some
future time.
As a result of the addition of these two new fields, the gen_idt tool is
modified to both process these new fields as well as validate them.
Change-Id: I343dac68d99c78168a25b19784140f85d5db7578
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Fixes a bug in the x86 IRQ_CONNECT_STATIC() macro that resulted in setting
the DPL for the interrupt to the IRQ priority level.
Note 1: Using a proper value for the DPL (instead of the priority) prevents
the corruption of the other IDT fields.
Note 2: The priority of the IRQ is completely ignored.
Change-Id: Ic9f59bd91db4b356263f533cc26a0168b1d236e1
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
We are seeing on some platforms that the VMA alignment
does not match the LMA alignment for this section, resulting
in problems when copying into RAM by __csSet(); any copied
sections afterwards end up misaligned in RAM.
While the true fix for this is under investigation, force
4-byte alignment for VMA and LMA.
Change-Id: I627d9e7a3446cbc09dc310a156d8b3268e61c91d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Due to similar padding issue as pipe, the list of task object
may not be used directly. As mentioned before, some compiler/linker
may pad the large struct. For example, compiling under gcc and
march=i686 pads the struct to 32-byte alignment (march=atom to
64-byte alignment). This causes issue with sizeof() and pointer
arithmetic because they have no idea about the padding.
When the stars align in a certain way, these task structs may be
corrupted. So add a task pointer list and use it for task
manipulation. The task list remains as it is beneficial to group
them together to take advantage of cache locality.
Change-Id: I0e86bfe05742040f4540d7854c1ac14e76162776
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit fixes small errors on the asm implementation of arc
register reading and the built-in functions call.
Change-Id: Iea2df715eaefb25095770971ac03d441311abf16
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
The _ARC_V2_IRQ_VECT_BASE register must be set to the vector table in
flash.
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
Change-Id: Ied5451c98222f545cd669967023aef26c3d8e48e
- Finally switched from ldw/stw to ldh/sth, as Benjamin noticed in an
earlier comment (I was using ARC ISA, and not ARC V2 ISA). So indeed
ldw/stw are obsolete and equivalent to ldh/std.
- clear, set and test were not working in case of using a memory address
which would not point to a register: bclr, bset and btst requires
registers as operands, and cannot deal with pure memory address (i.e.
something like [rx] is not valid), thus the requirement to load first
the value pointed by the address into a register, operate on that
register and storing the result of it into the pointed address.
Change-Id: Ib9c24c0a2c6d2b02e2d08d24f31cbc1981536a7d
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Doxegenize and cleanup headers for nanokernel
- fibers
- context
- timers
- stacks
Also minor cleanup of x86/arch.h
Change-Id: Ib65568d4ec034b69e8a6214ba4b52a7f719300bb
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
sys_in/sys_out are not implemented as there is no "ports" in ARC.
Change-Id: Ie72d6274ae1a2b2ca22955a9764e281e7669b973
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This will be helpful also in drivers mostly, where non-atomic bit
setting could be unnecessary.
Change-Id: I10c069387d1045f14337b3ac8acfc7b6c1f106c3
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
sys_io.h header file declares the generic API for such operations. It
properly separates port and memory mapped registers, with declaring
respective types: io_port_t and mm_reg_t.
Memory mapped registers are the most common type of registers drivers
will play with. Thus providing generic sys_readX/sys_writeX functions in
sys_io.h. Those are defined as inline as they are really simple.
Ports are mostly (always?) found in x86 architecture.
Currently no ARM or ARC header file propose any implementation of
those. If really necessary (a cross-architecture driver using
sys_in/sys_out functions), those architecture will provide the proper
implementation or at least a macro gluing those towards
sys_read/sys_write.
Change-Id: If77590d4bcefcdfa6aa181a88ced342f8565d5b8
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The term 'context' is vague and overloaded. Its usage for 'an execution
context' is now referred as such, in both comments and some APIs' names.
When the execution context can only be a fiber or a task (i.e. not an
ISR), it is referred to as a 'thread', again in comments and everywhere
in the code.
APIs that had their names changed:
- nano_context_id_t is now nano_thread_id_t
- context_self_get() is now sys_thread_self_get()
- context_type_get() is now sys_execution_context_type_get()
- context_custom_data_set/get() are now
sys_thread_custom_data_set/get()
The 'context' prefix namespace does not have to be reserved by the
kernel anymore.
The Context Control Structure (CCS) data structure is now the Thread
Control Structure (TCS):
- struct ccs is now struct tcs
- tCCS is now tTCS
Change-Id: I7526a76c5b01e7c86333078e2d2e77c9feef5364
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The files idtEnt.h and segselect.h in shared are linked from
the source tree for no good reason adding and extra top level
directory that might be confusing.
The shared/ here means shared between host and target, this is
not longer necessary in our build system.
Change-Id: Id9665e10de7a1d290888d9069be3db9f4330d284
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Highlight the fact that find_[lsb|msb]_set operate on a 32-bit word.
Change-Id: I24cee7709ea6497508dbc7f96a7b4d74fa4bc257
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The new names reflect better what the functions do: they find the first
bit set starting from the least or most significant bit, i.e. they find
the least or most significant bit set, in a 32-bit word.
Change-Id: I6f0ee4b543f6f37c2f08f7067e14e039c92a6f6a
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.
Change-Id: Iee2e6adcfb5da1fe0a978a05aa854e10ae82a8b8
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
The inline versions are renamed to remove the _inline suffix, and the
non-inline versions are removed from the code base.
Change-Id: I7314b96c42835f15df4c537ec11ab7961d4ee60f
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
irq_handler_set, irq_priority_set and irq_disconnect have been made
private by prepending an underscore to their names:
irq_handler_set -> irq_handler_set
irq_priority_set -> irq_priority_set
irq_disconnect -> irq_disconnect
The prototypes have been removed from header files when possible, and
extern statements used in C code where they were called.
_irq_priority_set() for ARM is still in the header file because
IRQ_CONFIG() relies on it.
Change-Id: I2ad585f8156ff80250f6d9eeca4a249a4477fd9d
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This enable defining memory maps in source code in addition to
defining in MDEF files. This introduces the macro
DEFINE_MEM_MAP(mem_map_name, ...). The memory maps created this
way are the same, in functionality, as those defined in MDEF
files. They can be manipulated by the standard microkernel
memory map APIs.
Define the memory map using:
DEFINE_MEM_MAP(mem_map1, blocks, block_size);
and "mem_map1" can be used, for example:
task_mem_map_alloc(mem_map1, ...);
or,
task_mem_map_free(mem_map1, ...);
etc.
To use the memory map defined in another source file, simply add:
extern const kmemory_map_t mem_map1;
to the desired C or header file.
Change-Id: I9c551b90f9d0a95f961fd8ec1c5278c2ea44312d
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The _k_mem_map_list was a static array generated by sysgen,
where it containing all pre-defined memory maps from MDEF file.
To support private memory map objects (aka, defining them within
source files), the list has to accommodate memory maps that
are not only processed through sysgen, but also those defined
within source files.
This is done by creating a new section in binary, and all memory
map pointers go into this section. By doing this, the list
can still be manipulated as an array.
Change-Id: I1f3414b72f685fef4b99850749178661f14d9345
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This enable defining pipes in source code in addition to
defining in MDEF files. This introduces the macro
DEFINE_PIPE(pipe_name, ...). The pipes created this
way are the same, in functionality, as those defined in MDEF
files. They can be manipulated by the standard microkernel
pipe APIs.
Define the pipe using:
DEFINE_PIPE(pipe1, size);
and "pipe1" can be used, for example:
task_pipe_put(pipe1, ...);
or,
task_pipe_get(pipe1, ...);
etc.
To use the pipe defined in another source file, simply add:
extern const kpipe_t pipe1;
to the desired C or header file.
Change-Id: Iae8e04706359bc18aae51acc75df3e3d26388882
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The _k_pipe_list was a static array generated by sysgen,
where it containing all pre-defined pipes from MDEF file.
To support private pipe objects (aka, defining pipes within
source files), the pipe list has to accommodate pipes that
are not only processed through sysgen, but also those defined
within source files.
This is done by creating a new section in binary, and all pipe
pointers go into this section. By doing this, the pipe list
can still be manipulated as an array. The reason behind
putting the pointers to pipe, instead of the pipe objects
themselves, is that some compiler/linker may pad the large pipe
struct. For example, compiling under gcc and march=i686 pads
the struct to 32-byte alignment (march=atom to 64-byte alignment).
This causes issue with sizeof() and pointer arithmetic because
they have no idea about the padding. So use pointers here to
prevent padding.
Change-Id: I6d3b75614c4d8760c037a5c26746410d4e4b17cb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This enable defining tasks in source code in addition to
defining in MDEF files. This introduces the macro
DEFINE_TASK(task_name). The tasks created this
way are the same, in functionality, as those defined in MDEF
files. They can be manipulated by the standard microkernel
task APIs.
Define the task using:
DEFINE_TASK(task1, priority, entry_func, stack_size, groups);
and "task1" can be used, for example:
task_start(task1);
or,
task_abort(task1);
etc.
To use the task defined in another source file, simply add:
extern const ktask_t task1;
to the desired C or header file.
Change-Id: Ib2f3572950ca74b359b7fde1ccd6cfd04783eefb
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The _k_task_list was a static array generated by sysgen,
where it containing all pre-defined tasks from MDEF file.
To support private task objects (aka, defining tasks within
source files), the task list has to accommodate tasks that
are not only processed through sysgen, but also those defined
within source files.
This is done by creating a new section in binary, and all task
objects go into this section. By doing this, the task list
can still be manipulated as an array, which is required for
task group operation.
Change-Id: I799d6967567079498bc414e0cb809e8af856b53e
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Galileo testing uses Linux kexec() feature to load Zephyr OS.
kexec() requires all program headers page size aligned.
Add page size padding to initlevel section in order to make
BSS page aligned.
Change-Id: I7c0e309be70aef45b347b16c6d5c01bdf5659351
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
Removes references to obsolete BSP terminology. Where appropriate, replaces it
with platform terminology.
Change-Id: If38c859338c7cf0de58430336e1046b28f9e9944
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The configuration of SRAM and flash options are no longer hardcoded in the
platform's linker script file, but are instead defined in the platform
configuration file.
Change-Id: I557a8228080d607f6add5f86b9b2509ed3fd31ce
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Updates Kconfig option names as part of transforming BSPs to platforms.
Change-Id: If397bcac8b058e5700e82c3cabbfe64588316d1d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Remove function name from comment and add @brief instead.
Also capitilize first letter.
Change-Id: Ib708b49bf02e5bc89b0066637a55874e659637e0
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Previous comment style used RETRURNS:, use @return to comply
with javadoc style.
Change-Id: Ib1dffd92da1d97d60063ec5309b08049828f6661
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The change replaces multiple asterisks to ** at
the beginning of comments and adds a space before
the asterisks at the beginning of lines.
Change-Id: I7656bde3bf4d9a31e38941e43b580520432dabc1
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
In order to provide the same irq_connect() on all platforms
on x86, irq_connect() now uses a static array of interrupt
stubs. Device driver does not need to provide interrupt stub
to irq_connect() function.
Add NUM_DYNAMIC_STUBS configuration parameter, the number
of interrupt stubs used for dynamic interrupt registration.
Modify tests for unified interrupt register API
Tests that deal with interrupts are modified to work
with the new interrupt registration API.
Add CONFIG_NUM_DYNAMIC_STUBS option to dynamic interrupt projects
Projects that use dynamic interrupt handler registration on x86
have to include CONFIG_NUM_DYNAMIC_STUBS parameter in the
configuration.
Change-Id: Ic90c726485521a57cf695fd3edc8cac85d0b827d
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
IRQ_CONNECT_STATIC() macro provides static interrupt registration.
It creates an entry for _sw_isr_table, table of interrupt handlers.
IRQ_CONFIG() macro provides interrupt controller configuration.
On ARM platform it configures the priority of each interrupt.
_sw_isr_table is implemented the way that each of it's elements
is located in individual section. Sections are marked a "linkonce",
thus when a device driver declares an interrupt handler, it overwrites
the default _sw_isr_table entry.
Change-Id: I182bf7158dd67f45b597783dca038a4f78166a03
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
In order to simplify x86 interrupt stub creation, each interrupt
controller implements an interrupt stub definition macro.
Add IRQ_CONNECT_STATIC() for static interrupt registration, and
construct the interrupt stubs name from device and interrupt
handler names.
Add IRQ_CONFIG() macro for the interrupt controller configuration.
On x86 platform it programs APIC to associate an IRQ number with
the interupt vector.
Add HPET_TIMER0_INT_PRI parameter to Quark platform header to
make it build correctly.
Change-Id: I24ad25e1aa807ffa63733a27ad882877fcad72af
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
The Cortex-M0 processor is not supported.
Change-Id: I3ada6615a8b41eb318f80edb13947f70459c761b
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Makes name more consistent with other CPU_CORTEX_M* options.
Change-Id: I65968cb300207ba0de6231d9a67f2720be77b6ba
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
CPU_CORTEX_M3_M4 replaces CPU_CORTEXM3 as the umbrella option for Cortex M3/M4
processors.
NOTE: Selecting CPU_CORTEXM4 still currently forces the selection of
CPU_CORTEXM3. Breaking that forced select will be done in a later commit.
Change-Id: I0f36b3a2adc5c6c66db4e9b6353b921199544deb
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The #include <__assert.h> in nvic.h must be guarded by __ASMLANGUAGE
since nvic.h is usable by asm code, and __assert.h is C-only.
Change-Id: I16d72e4579705dbd0bfb55a787525c5938fd1f22
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This commit set back .S as the assembly code extension for Kbuild.
Change-Id: Ib0119876bd0bed6617bbfbad2ca6a44e172ab042
Signed-off-by: Juan Manuel Cruz <juan.m.cruz.alcaraz@linux.intel.com>
Eliminates references to the obsolete OS name. In most cases the
name is simply removed, as it isn't necessary.
Change-Id: I32f9e7390e436aec008a9454b72657e129d65152
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
This file doesn't belong in the architecture-specific portion of
the tree, and its contents don't warrant their own file, so the
content is moved to the main nanokernel public API include file.
Change-Id: I0455fc9eb4f5ca31a8e6b487f56b09d0562fdb77
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Introduces nano_internal.h, which will declare all architecture-
independent non-public nanokernel APIs. This file is automatically
incorporated by the various architecture-specific include files
for non-public nanokernel APIs, and will not normally be included
directly by any other files.
Change-Id: I9f3de812a5747cc720fa0ff739007315e8d07dd9
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
These declarations are now co-located with the declarations
for the routines that utilize them.
Change-Id: I70940923d9e424345aeac60cb5ddd7f7a2a54734
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
These files now have no useful content.
Change-Id: If5d2df361eb8769ca38c4ae63f68a5681b3ad85b
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
These now appear in the files which declare other non-public
nanokernel APIs.
Change-Id: Iea01d6de44851a08b308004b2c3104c08b020970
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Since cputype.h no longer has any meaningful content it can be
eliminated, along with the arch-specific files it incorporated.
(This means that the arch-specific nanokernel public APIs are
now referenced only via cpu.h and its derivatives.)
Change-Id: I7f35b6c3c6c092d61c372ff85d73e49414474938
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Moves these macros to the main public API include file for each
supported architecture, since the <arch>type.h include file is
to be eliminated.
Change-Id: Ia87b9c0bed1501bcce7f363bd4155f7ef642376a
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Several files were not explicitly including APIs that they reference,
which could eventually lead to trouble.
Change-Id: Ib33cadfa658280df3fcb4c670463d41b63097b31
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Add infrastructure support having multiple instances of a driver
configured into the system each with its own compile time
configuration information.
Change-Id: I1e447af18311139b43f74fe0439483ccd132b63f
Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com>
The "__stack" tag is to be used to align an array (to STACK_ALIGN) for stack
use by either a fiber or task.
Change-Id: I5828f3ee1b09b0b5ba894ea30689d179de347494
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The __attribute__ keyword is toolchain specific.
Change-Id: Ia3c0ff54d778785679c864704f8db6a3ba898948
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
The __attribute__ keyword is toolchain specific.
Change-Id: I2183d154ccdb9b5bed3bc245cc37cbf4c5cc62cc
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Completes the renaming of nanoFiberStart() -> fiber_fiber_start().
There is little value in listing the callers of _NewContext() in its function
header. Not only was the (deleted) list both incomplete and wrong, keeping
it around and properly updated requires error prone maintenance.
Change-Id: Ic45f51b285c027a2e8be331c0d28c16bdc97647d
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
It is a fatal error if the microkernel is configured with either too few
command packets or too few timer packets.
NOTE: During this refactoring of _Cget(), not only is it renamed to
_nano_fiber_lifo_get_panic(), but it is moved into "nano_lifo.c".
Change-Id: I1d866cda1b444da04877f7eda03762b6e83c9a6f
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
This reason code will be used indicate that the kernel failed to allocate a
critical resource (such as a command packet or a timer packet).
Change-Id: I6d4c3d96fc70b2b8cab4027b1b8e4febf4d6c474
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
Since ARC does not support the microkernel, there is no need to
define any microkernel event symbols for it. (And TICK_EVENT is
an architecture-independent concept anyway ...)
Change-Id: I918a55743f8685ef23b9bb5a8afc67b905ab9766
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
1) Renames APIs to align them with conventions used by other
general-context nanokernel APIs.
2) Relocates implementation of these APIs to the architecture-
independent portion of the nanokernel.
Change-Id: I1aa60029aaa96697cd8fcb594bbae23ba6656661
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
These APIs are no longer referenced anywhere.
Change-Id: I56e3410b9fb6bc4eb72bc9299b33f75227916434
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
This is not required since the secure string library routines
have been removed.
Change-Id: I284a21e4167d9bb6f78354d809c563a4c52f619c
Signed-off-by: Allan Stephens <allan.stephens@windriver.com>
Renaming the directory include/nanokernel to be include/arch, which
better reflects the real nature of the directory and the contents
inside.
Change-Id: I2bc33ebc6715e2f0403227a558279fdf52398ade
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
