dts: arc: Add dts support for arc

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>
This commit is contained in:
Savinay Dharmappa 2017-09-22 00:15:14 +05:30 committed by Kumar Gala
commit 7c8a23d643
5 changed files with 72 additions and 1 deletions

View file

@ -201,6 +201,7 @@ source "arch/arc/core/mpu/Kconfig"
endmenu
if !HAS_DTS
config ICCM_SIZE
int "ICCM Size in kB"
help
@ -256,6 +257,7 @@ config FLASH_BASE_ADDRESS
This option specifies the base address of the flash on the board. It is
normally set by the board's defconfig file and the user should generally
avoid modifying it via the menu configuration.
endif
config CACHE_LINE_SIZE_DETECT
bool

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@ -28,6 +28,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config HARVARD
def_bool n
if !HAS_DTS
config FLASH_BASE_ADDRESS
default 0x40000000
@ -53,6 +54,7 @@ config DCCM_BASE_ADDRESS
config DCCM_SIZE
default 8
endif
config QMSI
def_bool y
@ -266,7 +268,7 @@ endif # UART_QMSI_1
endif # UART_QMSI
if UART_CONSOLE
if UART_CONSOLE && !HAS_DTS
config UART_CONSOLE_ON_DEV_NAME
default "UART_1"

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@ -26,4 +26,5 @@
#define DCCM_START CONFIG_DCCM_BASE_ADDRESS
#define DCCM_SIZE CONFIG_DCCM_SIZE
#include <generated_dts_board.h>
#include <arch/arc/v2/linker.ld>

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@ -0,0 +1,65 @@
#include "skeleton.dtsi"
#define __SIZE_K(x) (x * 1024)
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem4";
reg = <1>;
};
core_intc: arcv2-intc@0 {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
flash0: flash@40010000 {
reg = <0x40000000 DT_FLASH_SIZE>;
};
sram0: memory@a8000400 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa8000400 DT_SRAM_SIZE>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 DT_DCCM_SIZE>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@b0002000 {
compatible = "intel,qmsi-uart";
reg = <0xb0002000 0x400>;
interrupts = <5 0>;
interrupt-parent = <&core_intc>;
label = "UART_0";
status = "disabled";
};
uart1: uart@b0002400 {
compatible = "intel,qmsi-uart";
reg = <0xb0002400 0x400>;
interrupts = <6 0>;
interrupt-parent = <&core_intc>;
label = "UART_1";
status = "disabled";
};
};
};

View file

@ -25,6 +25,7 @@ extern "C" {
#define OCTET_TO_SIZEOFUNIT(X) (X)
#define SIZEOFUNIT_TO_OCTET(X) (X)
#include <generated_dts_board.h>
#include <sw_isr_table.h>
#ifdef CONFIG_CPU_ARCV2
#include <arch/arc/v2/exc.h>