arm: nvic: kill _NvicSwInterruptTrigger
_NvicSwInterruptTrigger is only utilized by a testcase for irq handling on ARM-V7M. Just put the code into the testcase so we dont need to support an additional interface. Change-Id: I763c63c32a7a52918250458351d08b8fa54069dd Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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3 changed files with 12 additions and 28 deletions
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@ -224,32 +224,6 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
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#endif /* CONFIG_ARMV6_M */
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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/**
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*
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* @brief Trigger an interrupt via software
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*
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* Trigger interrupt #@a irq. The CPU will handle the IRQ when interrupts are
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* enabled and/or returning from a higher priority interrupt.
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*
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* @param irq IRQ number
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* @return N/A
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*/
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static inline void _NvicSwInterruptTrigger(unsigned int irq)
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{
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
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/* the QEMU does not simulate the STIR register: this is a workaround */
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_NvicIrqPend(irq);
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#else
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__scs.stir = irq;
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#endif
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}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* !_ASMLANGUAGE */
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#ifdef __cplusplus
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@ -81,7 +81,12 @@ void test_irq_vector_table(void)
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k_sem_take(&sem[2], K_NO_WAIT)), NULL);
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for (int ii = 0; ii < 3; ii++) {
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_NvicSwInterruptTrigger(ii);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
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/* the QEMU does not simulate the STIR register: this is a workaround */
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_NvicIrqPend(ii);
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#else
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__scs.stir = ii;
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#endif
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}
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assert_false((k_sem_take(&sem[0], K_NO_WAIT) ||
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@ -94,7 +94,12 @@ void main(void)
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}
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for (int ii = 0; ii < 3; ii++) {
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_NvicSwInterruptTrigger(ii);
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#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
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/* the QEMU does not simulate the STIR register: this is a workaround */
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_NvicIrqPend(ii);
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#else
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__scs.stir = ii;
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#endif
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}
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rv = nano_task_sem_take(&sem[0], TICKS_NONE) &&
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