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arm: nvic: kill _NvicSwInterruptTrigger

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_NvicSwInterruptTrigger is only utilized by a testcase for irq handling
on ARM-V7M.  Just put the code into the testcase so we dont need to
support an additional interface.

Change-Id: I763c63c32a7a52918250458351d08b8fa54069dd
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-01-18 11:07:25 -06:00
commit 2e0c2aff97
3 changed files with 12 additions and 28 deletions
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26
include/arch/arm/cortex_m/nvic.h
View file

@ -224,32 +224,6 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
#endif /* CONFIG_ARMV6_M */
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**
*
* @brief Trigger an interrupt via software
*
* Trigger interrupt #@a irq. The CPU will handle the IRQ when interrupts are
* enabled and/or returning from a higher priority interrupt.
*
* @param irq IRQ number
* @return N/A
*/
static inline void _NvicSwInterruptTrigger(unsigned int irq)
{
#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
/* the QEMU does not simulate the STIR register: this is a workaround */
_NvicIrqPend(irq);
#else
__scs.stir = irq;
#endif
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
#endif /* !_ASMLANGUAGE */
#ifdef __cplusplus

7
tests/kernel/arm_irq_vector_table/src/main.c
View file

@ -81,7 +81,12 @@ void test_irq_vector_table(void)
k_sem_take(&sem[2], K_NO_WAIT)), NULL);
for (int ii = 0; ii < 3; ii++) {
_NvicSwInterruptTrigger(ii);
#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
/* the QEMU does not simulate the STIR register: this is a workaround */
_NvicIrqPend(ii);
#else
__scs.stir = ii;
#endif
}
assert_false((k_sem_take(&sem[0], K_NO_WAIT) ||

7
tests/legacy/kernel/test_arm_irq_vector_table/src/main.c
View file

@ -94,7 +94,12 @@ void main(void)
}
for (int ii = 0; ii < 3; ii++) {
_NvicSwInterruptTrigger(ii);
#if defined(CONFIG_SOC_TI_LM3S6965_QEMU)
/* the QEMU does not simulate the STIR register: this is a workaround */
_NvicIrqPend(ii);
#else
__scs.stir = ii;
#endif
}
rv = nano_task_sem_take(&sem[0], TICKS_NONE) &&