arm: Replace CONFIG_CPU_CORTEX_M3_M4 with CONFIG_ARMV7_M
Precursor patches have arranged that conditional compilation hanging on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the config variable to reflect this. Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
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727dc2c5d6
commit
ef8200dfcd
18 changed files with 51 additions and 53 deletions
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@ -69,7 +69,7 @@ config ARMV6_M
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help
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This option signifies the use of an ARMv6-M processor implementation.
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config CPU_CORTEX_M3_M4
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config ARMV7_M
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bool
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# Omit prompt to signify "hidden" option
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default n
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@ -78,7 +78,7 @@ config CPU_CORTEX_M3_M4
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select CPU_CORTEX_M_HAS_BASEPRI
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select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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help
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This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
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This option signifies the use of an ARMv7-M processor implementation.
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config CPU_CORTEX_M0
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bool
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@ -97,14 +97,14 @@ config CPU_CORTEX_M0PLUS
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config CPU_CORTEX_M3
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bool
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# Omit prompt to signify "hidden" option
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select CPU_CORTEX_M3_M4
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select ARMV7_M
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help
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This option signifies the use of a Cortex-M3 CPU
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config CPU_CORTEX_M4
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bool
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# Omit prompt to signify "hidden" option
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select CPU_CORTEX_M3_M4
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select ARMV7_M
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help
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This option signifies the use of a Cortex-M4 CPU
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@ -211,7 +211,7 @@ config FLASH_BASE_ADDRESS
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endmenu
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menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
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depends on ARMV6_M || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
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depends on ARMV6_M || ARMV7_M || CPU_CORTEX_M7
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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@ -74,7 +74,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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/* lock interrupts: will get unlocked when switch to main task */
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#if defined(CONFIG_ARMV6_M)
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cpsid i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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#else
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@ -91,7 +91,7 @@ void sys_arch_reboot(int type)
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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* @brief Set the number of priority groups based on the number of exception
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@ -66,7 +66,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
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.word __reserved
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.word __reserved /* SVC not used for now (PendSV used instead) */
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.word __reserved
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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.word __mpu_fault
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.word __bus_fault
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.word __usage_fault
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@ -49,7 +49,7 @@ GTEXT(__reset)
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GTEXT(__nmi)
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GTEXT(__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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GTEXT(__usage_fault)
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@ -129,7 +129,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
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#if defined(CONFIG_ARMV6_M)
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cpsie i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* clear BASEPRI so wfi is awakened by incoming interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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@ -193,7 +193,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
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cpsie i
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_irq_disabled:
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* r1: zero, for setting BASEPRI (needs a register) */
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eors.n r1, r1
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@ -70,7 +70,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
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esf->pc);
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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int escalation = 0;
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if (3 == fault) { /* hard fault */
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@ -124,7 +124,7 @@ static void _FaultThreadShow(const NANO_ESF *esf)
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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@ -266,7 +266,7 @@ static void _HardFault(const NANO_ESF *esf)
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#if defined(CONFIG_ARMV6_M)
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_FaultThreadShow(esf);
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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if (_ScbHardFaultIsBusErrOnVectorRead()) {
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PR_EXC(" Bus fault on vector table read\n");
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} else if (_ScbHardFaultIsForced()) {
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@ -327,7 +327,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
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_HardFault(esf);
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break;
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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case 4:
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_MpuFault(esf, 0);
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break;
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@ -388,7 +388,7 @@ void _Fault(const NANO_ESF *esf)
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void _FaultInit(void)
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{
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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_ScbDivByZeroFaultEnable();
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#else
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#error Unknown ARM architecture
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@ -33,7 +33,7 @@ GTEXT(_Fault)
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GTEXT(__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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GTEXT(__usage_fault)
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@ -68,7 +68,7 @@ GTEXT(__reserved)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
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@ -95,7 +95,7 @@ _stack_frame_msp:
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mrs r0, MSP
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_stack_frame_endif:
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* force unlock interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
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blx _sys_power_save_idle_exit
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_idle_state_cleared:
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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ittt ne
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movne r1, #0
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/* clear kernel idle state */
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@ -106,7 +106,7 @@ _idle_state_cleared:
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ldr r1, =16
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subs r0, r1 /* get IRQ number */
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lsls r0, #3 /* table is 8-byte wide */
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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sub r0, r0, #16 /* get IRQ number */
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lsl r0, r0, #3 /* table is 8-byte wide */
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#else
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@ -122,7 +122,7 @@ _idle_state_cleared:
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#if defined(CONFIG_ARMV6_M)
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pop {r3}
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mov lr, r3
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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pop {lr}
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#else
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#error Unknown ARM architecture
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@ -33,7 +33,7 @@ _ASM_FILE_PROLOGUE
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GTEXT(_Swap)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__svc)
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#else
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#error Unknown ARM architecture
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@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, __pendsv)
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mov r7, ip
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/* store r8-12 */
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stmea r0!, {r3-r7}
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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stmia r0, {v1-v8, ip}
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#ifdef CONFIG_FP_SHARING
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add r0, r2, #_thread_offset_to_preempt_float
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@ -111,7 +111,7 @@ SECTION_FUNC(TEXT, __pendsv)
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/* protect the kernel state while we play with the thread lists */
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#if defined(CONFIG_ARMV6_M)
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cpsid i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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#else
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@ -170,7 +170,7 @@ _thread_irq_disabled:
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/* restore r4-r7, go back 9*4 bytes to the start of the stored block */
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subs r0, #36
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ldmia r0!, {r4-r7}
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* restore BASEPRI for the incoming thread */
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msr BASEPRI, r0
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@ -192,7 +192,7 @@ _thread_irq_disabled:
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bx lr
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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* @brief Service call handler
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@ -316,7 +316,7 @@ SECTION_FUNC(TEXT, _Swap)
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* of a higher priority pending.
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*/
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cpsie i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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svc #0
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#else
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#error Unknown ARM architecture
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@ -60,7 +60,7 @@ static ALWAYS_INLINE int _IsInIsr(void)
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*/
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#if defined(CONFIG_ARMV6_M)
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return (vector > 10) || (vector == 3);
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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return (vector > 10) || (vector && _ScbIsNestedExc());
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#else
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#error Unknown ARM architecture
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@ -69,7 +69,7 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size,
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/* unlock interrupts */
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#ifdef CONFIG_ARMV6_M
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"cpsie i \t\n"
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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"movs %%r1, #0 \n\t"
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"msr BASEPRI, %%r1 \n\t"
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#else
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@ -134,7 +134,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
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: "=r" (key)
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:
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: "memory");
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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unsigned int tmp;
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__asm__ volatile(
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return;
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}
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__asm__ volatile("cpsie i" : : : "memory");
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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__asm__ volatile("msr BASEPRI, %0" : : "r"(key) : "memory");
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#else
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#error Unknown ARM architecture
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@ -205,7 +205,7 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
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volatile uint32_t * const ipr = &__scs.nvic.ipr[_PRIO_IP_IDX(irq)];
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*ipr = ((*ipr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(irq))) |
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((uint32_t)prio << _PRIO_BIT_SHIFT(irq)));
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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__scs.nvic.ipr[irq] = prio;
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#else
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#error Unknown ARM architecture
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@ -227,7 +227,7 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
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{
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#if defined(CONFIG_ARMV6_M)
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return (__scs.nvic.ipr[_PRIO_IP_IDX(irq)] >> _PRIO_BIT_SHIFT(irq));
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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return __scs.nvic.ipr[irq];
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#else
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#error Unknown ARM architecture
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@ -235,7 +235,7 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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* @brief Trigger an interrupt via software
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@ -442,7 +442,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc)
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#if defined(CONFIG_ARMV6_M)
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__ASSERT((exc > 10) && (exc < 16), "");
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return (__scs.scb.shpr[_PRIO_SHP_IDX(exc)] >> _PRIO_BIT_SHIFT(exc));
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* For priority exception handler 4-15 */
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__ASSERT((exc > 3) && (exc < 16), "");
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return __scs.scb.shpr[exc - 4];
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@ -477,7 +477,7 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
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__ASSERT((exc > 10) && (exc < 16), "");
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*shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) |
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((uint32_t)pri << _PRIO_BIT_SHIFT(exc)));
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/* For priority exception handler 4-15 */
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__ASSERT((exc > 3) && (exc < 16), "");
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__scs.scb.shpr[exc - 4] = pri;
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@ -487,7 +487,7 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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* @brief Find out if the currently executing exception is nested
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@ -120,7 +120,7 @@ union __icsr {
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uint32_t rsvd__9_10_11 : 3 __packed;
|
||||
uint32_t vectpending : 9 __packed;
|
||||
uint32_t rsvd__21 : 1 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t vectactive : 10 __packed;
|
||||
uint32_t rsvd__10 : 1 __packed;
|
||||
uint32_t rettobase : 1 __packed;
|
||||
|
@ -155,7 +155,7 @@ union __aircr {
|
|||
struct {
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd__0 : 1 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t vecreset : 1 __packed; /* WO */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
|
@ -164,7 +164,7 @@ union __aircr {
|
|||
uint32_t sysresetreq : 1 __packed; /* WO */
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd__3_14 : 12 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t rsvd__3_7 : 5 __packed;
|
||||
uint32_t prigroup : 3 __packed;
|
||||
uint32_t rsvd__11_14 : 4 __packed;
|
||||
|
@ -195,7 +195,7 @@ union __ccr {
|
|||
struct {
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_0_2 : 3 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t nonbasethrdena : 1 __packed;
|
||||
uint32_t usersetmpend : 1 __packed;
|
||||
uint32_t rsvd__2 : 1 __packed;
|
||||
|
@ -205,7 +205,7 @@ union __ccr {
|
|||
uint32_t unalign_trp : 1 __packed;
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_4_8 : 5 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t div_0_trp : 1 __packed;
|
||||
uint32_t rsvd__5_7 : 3 __packed;
|
||||
uint32_t bfhfnmign : 1 __packed;
|
||||
|
@ -490,7 +490,7 @@ struct __scs {
|
|||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t ipr[8];
|
||||
uint32_t rsvd__420_4ff[56];
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint8_t ipr[240]; /* 0x400 Interrupt Priority Registers */
|
||||
uint32_t rsvd__4f0_4ff[4];
|
||||
#else
|
||||
|
@ -506,7 +506,7 @@ struct __scs {
|
|||
union __icsr icsr; /* 0xd04 IRQ Control and Start Register */
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_9_12;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
union __vtor vtor; /* 0xd08 Vector Table Offset Register */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
|
@ -518,7 +518,7 @@ struct __scs {
|
|||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_24_27;
|
||||
uint32_t shpr[2];
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint8_t shpr[12]; /* 0xd18 System Handler Priority Registers
|
||||
* Use ('exception number' - 4) to
|
||||
* get index into array
|
||||
|
@ -530,7 +530,7 @@ struct __scs {
|
|||
shcsr; /* 0xd24 Sys Handler Control and State Reg */
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_40_63[6];
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register
|
||||
*/
|
||||
union __hfsr hfsr; /* 0xd2C Hard Fault Status Register */
|
||||
|
@ -594,14 +594,14 @@ extern volatile struct __scs __scs;
|
|||
#define _PRIO_BIT_SHIFT(IRQn) (((((uint32_t)(IRQn))) & 0x03UL) * 8UL)
|
||||
#define _PRIO_SHP_IDX(IRQn) ((((((uint32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL))
|
||||
#define _PRIO_IP_IDX(IRQn) ((((uint32_t)(IRQn)) >> 2UL))
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
/* API */
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
/**
|
||||
*
|
||||
* @brief Obtain the number of interrupt lines on the target
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
[test]
|
||||
tags = core bat_commit
|
||||
filter = CONFIG_CPU_CORTEX_M3_M4
|
||||
|
||||
filter = CONFIG_ARMV7_M
|
||||
|
|
|
@ -1,4 +1,3 @@
|
|||
[test]
|
||||
tags = legacy core bat_commit
|
||||
filter = CONFIG_CPU_CORTEX_M3_M4
|
||||
|
||||
filter = CONFIG_ARMV7_M
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue