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arm: Replace CONFIG_CPU_CORTEX_M3_M4 with CONFIG_ARMV7_M

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Precursor patches have arranged that conditional compilation hanging
on CONFIG_CPU_CORTEX_M3_M4 provides support for ARMv7-M, rename the
config variable to reflect this.

Change-Id: Ifa56e3c1c04505d061b2af3aec9d8b9e55b5853d
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
Marcus Shawcroft 2016-12-31 13:21:43 +00:00 • committed by Kumar Gala
commit ef8200dfcd
18 changed files with 51 additions and 53 deletions
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10
arch/arm/core/cortex_m/Kconfig
View file

@ -69,7 +69,7 @@ config ARMV6_M
help
This option signifies the use of an ARMv6-M processor implementation.
config CPU_CORTEX_M3_M4
config ARMV7_M
bool
# Omit prompt to signify "hidden" option
default n
@ -78,7 +78,7 @@ config CPU_CORTEX_M3_M4
select CPU_CORTEX_M_HAS_BASEPRI
select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
This option signifies the use of an ARMv7-M processor implementation.
config CPU_CORTEX_M0
bool
@ -97,14 +97,14 @@ config CPU_CORTEX_M0PLUS
config CPU_CORTEX_M3
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M3_M4
select ARMV7_M
help
This option signifies the use of a Cortex-M3 CPU
config CPU_CORTEX_M4
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M3_M4
select ARMV7_M
help
This option signifies the use of a Cortex-M4 CPU
@ -211,7 +211,7 @@ config FLASH_BASE_ADDRESS
endmenu
menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
depends on ARMV6_M || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
depends on ARMV6_M || ARMV7_M || CPU_CORTEX_M7
config IRQ_OFFLOAD
bool "Enable IRQ offload"

2
arch/arm/core/cortex_m/reset.S
View file

@ -74,7 +74,7 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
/* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_ARMV6_M)
cpsid i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#else

2
arch/arm/core/cortex_m/scb.c
View file

@ -91,7 +91,7 @@ void sys_arch_reboot(int type)
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
* @brief Set the number of priority groups based on the number of exception

2
arch/arm/core/cortex_m/vector_table.S
View file

@ -66,7 +66,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __reserved
.word __reserved /* SVC not used for now (PendSV used instead) */
.word __reserved
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
.word __mpu_fault
.word __bus_fault
.word __usage_fault

2
arch/arm/core/cortex_m/vector_table.h
View file

@ -49,7 +49,7 @@ GTEXT(__reset)
GTEXT(__nmi)
GTEXT(__hard_fault)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
GTEXT(__usage_fault)

4
arch/arm/core/cpu_idle.S
View file

@ -129,7 +129,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
#if defined(CONFIG_ARMV6_M)
cpsie i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/* clear BASEPRI so wfi is awakened by incoming interrupts */
eors.n r0, r0
msr BASEPRI, r0
@ -193,7 +193,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
cpsie i
_irq_disabled:
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/* r1: zero, for setting BASEPRI (needs a register) */
eors.n r1, r1

10
arch/arm/core/fault.c
View file

@ -70,7 +70,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
esf->pc);
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
int escalation = 0;
if (3 == fault) { /* hard fault */
@ -124,7 +124,7 @@ static void _FaultThreadShow(const NANO_ESF *esf)
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -266,7 +266,7 @@ static void _HardFault(const NANO_ESF *esf)
#if defined(CONFIG_ARMV6_M)
_FaultThreadShow(esf);
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
if (_ScbHardFaultIsBusErrOnVectorRead()) {
PR_EXC(" Bus fault on vector table read\n");
} else if (_ScbHardFaultIsForced()) {
@ -327,7 +327,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
_HardFault(esf);
break;
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
case 4:
_MpuFault(esf, 0);
break;
@ -388,7 +388,7 @@ void _Fault(const NANO_ESF *esf)
void _FaultInit(void)
{
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
_ScbDivByZeroFaultEnable();
#else
#error Unknown ARM architecture

6
arch/arm/core/fault_s.S
View file

@ -33,7 +33,7 @@ GTEXT(_Fault)
GTEXT(__hard_fault)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
GTEXT(__usage_fault)
@ -68,7 +68,7 @@ GTEXT(__reserved)
SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
@ -95,7 +95,7 @@ _stack_frame_msp:
mrs r0, MSP
_stack_frame_endif:
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/* force unlock interrupts */
eors.n r0, r0
msr BASEPRI, r0

6
arch/arm/core/isr_wrapper.S
View file

@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
blx _sys_power_save_idle_exit
_idle_state_cleared:
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
ittt ne
movne r1, #0
/* clear kernel idle state */
@ -106,7 +106,7 @@ _idle_state_cleared:
ldr r1, =16
subs r0, r1 /* get IRQ number */
lsls r0, #3 /* table is 8-byte wide */
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
sub r0, r0, #16 /* get IRQ number */
lsl r0, r0, #3 /* table is 8-byte wide */
#else
@ -122,7 +122,7 @@ _idle_state_cleared:
#if defined(CONFIG_ARMV6_M)
pop {r3}
mov lr, r3
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
pop {lr}
#else
#error Unknown ARM architecture

12
arch/arm/core/swap.S
View file

@ -33,7 +33,7 @@ _ASM_FILE_PROLOGUE
GTEXT(_Swap)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__svc)
#else
#error Unknown ARM architecture
@ -88,7 +88,7 @@ SECTION_FUNC(TEXT, __pendsv)
mov r7, ip
/* store r8-12 */
stmea r0!, {r3-r7}
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
stmia r0, {v1-v8, ip}
#ifdef CONFIG_FP_SHARING
add r0, r2, #_thread_offset_to_preempt_float
@ -111,7 +111,7 @@ SECTION_FUNC(TEXT, __pendsv)
/* protect the kernel state while we play with the thread lists */
#if defined(CONFIG_ARMV6_M)
cpsid i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#else
@ -170,7 +170,7 @@ _thread_irq_disabled:
/* restore r4-r7, go back 9*4 bytes to the start of the stored block */
subs r0, #36
ldmia r0!, {r4-r7}
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/* restore BASEPRI for the incoming thread */
msr BASEPRI, r0
@ -192,7 +192,7 @@ _thread_irq_disabled:
bx lr
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
* @brief Service call handler
@ -316,7 +316,7 @@ SECTION_FUNC(TEXT, _Swap)
* of a higher priority pending.
*/
cpsie i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
svc #0
#else
#error Unknown ARM architecture

2
arch/arm/include/cortex_m/exc.h
View file

@ -60,7 +60,7 @@ static ALWAYS_INLINE int _IsInIsr(void)
*/
#if defined(CONFIG_ARMV6_M)
return (vector > 10) || (vector == 3);
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
return (vector > 10) || (vector && _ScbIsNestedExc());
#else
#error Unknown ARM architecture

2
arch/arm/include/kernel_arch_func.h
View file

@ -69,7 +69,7 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size,
/* unlock interrupts */
#ifdef CONFIG_ARMV6_M
"cpsie i \t\n"
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
"movs %%r1, #0 \n\t"
"msr BASEPRI, %%r1 \n\t"
#else

4
include/arch/arm/cortex_m/asm_inline_gcc.h
View file

@ -134,7 +134,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
: "=r" (key)
:
: "memory");
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
unsigned int tmp;
__asm__ volatile(
@ -178,7 +178,7 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
return;
}
__asm__ volatile("cpsie i" : : : "memory");
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
__asm__ volatile("msr BASEPRI, %0" : : "r"(key) : "memory");
#else
#error Unknown ARM architecture

6
include/arch/arm/cortex_m/nvic.h
View file

@ -205,7 +205,7 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
volatile uint32_t * const ipr = &__scs.nvic.ipr[_PRIO_IP_IDX(irq)];
*ipr = ((*ipr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(irq))) |
((uint32_t)prio << _PRIO_BIT_SHIFT(irq)));
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
__scs.nvic.ipr[irq] = prio;
#else
#error Unknown ARM architecture
@ -227,7 +227,7 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
{
#if defined(CONFIG_ARMV6_M)
return (__scs.nvic.ipr[_PRIO_IP_IDX(irq)] >> _PRIO_BIT_SHIFT(irq));
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
return __scs.nvic.ipr[irq];
#else
#error Unknown ARM architecture
@ -235,7 +235,7 @@ static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
* @brief Trigger an interrupt via software

6
include/arch/arm/cortex_m/scb.h
View file

@ -442,7 +442,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc)
#if defined(CONFIG_ARMV6_M)
__ASSERT((exc > 10) && (exc < 16), "");
return (__scs.scb.shpr[_PRIO_SHP_IDX(exc)] >> _PRIO_BIT_SHIFT(exc));
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/* For priority exception handler 4-15 */
__ASSERT((exc > 3) && (exc < 16), "");
return __scs.scb.shpr[exc - 4];
@ -477,7 +477,7 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
__ASSERT((exc > 10) && (exc < 16), "");
*shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) |
((uint32_t)pri << _PRIO_BIT_SHIFT(exc)));
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/* For priority exception handler 4-15 */
__ASSERT((exc > 3) && (exc < 16), "");
__scs.scb.shpr[exc - 4] = pri;
@ -487,7 +487,7 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
* @brief Find out if the currently executing exception is nested

22
include/arch/arm/cortex_m/scs.h
View file

@ -120,7 +120,7 @@ union __icsr {
uint32_t rsvd__9_10_11 : 3 __packed;
uint32_t vectpending : 9 __packed;
uint32_t rsvd__21 : 1 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t vectactive : 10 __packed;
uint32_t rsvd__10 : 1 __packed;
uint32_t rettobase : 1 __packed;
@ -155,7 +155,7 @@ union __aircr {
struct {
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd__0 : 1 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t vecreset : 1 __packed; /* WO */
#else
#error Unknown ARM architecture
@ -164,7 +164,7 @@ union __aircr {
uint32_t sysresetreq : 1 __packed; /* WO */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd__3_14 : 12 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t rsvd__3_7 : 5 __packed;
uint32_t prigroup : 3 __packed;
uint32_t rsvd__11_14 : 4 __packed;
@ -195,7 +195,7 @@ union __ccr {
struct {
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_0_2 : 3 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t nonbasethrdena : 1 __packed;
uint32_t usersetmpend : 1 __packed;
uint32_t rsvd__2 : 1 __packed;
@ -205,7 +205,7 @@ union __ccr {
uint32_t unalign_trp : 1 __packed;
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_4_8 : 5 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t div_0_trp : 1 __packed;
uint32_t rsvd__5_7 : 3 __packed;
uint32_t bfhfnmign : 1 __packed;
@ -490,7 +490,7 @@ struct __scs {
#if defined(CONFIG_ARMV6_M)
uint32_t ipr[8];
uint32_t rsvd__420_4ff[56];
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint8_t ipr[240]; /* 0x400 Interrupt Priority Registers */
uint32_t rsvd__4f0_4ff[4];
#else
@ -506,7 +506,7 @@ struct __scs {
union __icsr icsr; /* 0xd04 IRQ Control and Start Register */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_9_12;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
union __vtor vtor; /* 0xd08 Vector Table Offset Register */
#else
#error Unknown ARM architecture
@ -518,7 +518,7 @@ struct __scs {
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_24_27;
uint32_t shpr[2];
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
uint8_t shpr[12]; /* 0xd18 System Handler Priority Registers
* Use ('exception number' - 4) to
* get index into array
@ -530,7 +530,7 @@ struct __scs {
shcsr; /* 0xd24 Sys Handler Control and State Reg */
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_40_63[6];
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register
*/
union __hfsr hfsr; /* 0xd2C Hard Fault Status Register */
@ -594,14 +594,14 @@ extern volatile struct __scs __scs;
#define _PRIO_BIT_SHIFT(IRQn) (((((uint32_t)(IRQn))) & 0x03UL) * 8UL)
#define _PRIO_SHP_IDX(IRQn) ((((((uint32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL))
#define _PRIO_IP_IDX(IRQn) ((((uint32_t)(IRQn)) >> 2UL))
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
/* API */
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#elif defined(CONFIG_ARMV7_M) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
* @brief Obtain the number of interrupt lines on the target

3
tests/kernel/arm_irq_vector_table/testcase.ini
View file

@ -1,4 +1,3 @@
[test]
tags = core bat_commit
filter = CONFIG_CPU_CORTEX_M3_M4
filter = CONFIG_ARMV7_M

3
tests/legacy/kernel/test_arm_irq_vector_table/testcase.ini
View file

@ -1,4 +1,3 @@
[test]
tags = legacy core bat_commit
filter = CONFIG_CPU_CORTEX_M3_M4
filter = CONFIG_ARMV7_M