arc: enable gen_isr_tables mechanism
Change-Id: I5897e110f554377796bfe38dd5c0f8652c29e5be Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
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10 changed files with 56 additions and 212 deletions
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@ -144,6 +144,12 @@ config XIP
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default n if NSIM
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default y
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_START_VECTOR
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default 16
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config HARVARD
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prompt "Harvard Architecture"
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bool
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@ -208,46 +214,6 @@ config FLASH_BASE_ADDRESS
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normally set by the board's defconfig file and the user should generally
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avoid modifying it via the menu configuration.
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config SW_ISR_TABLE
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bool
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prompt "Enable software interrupt handler table"
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default y
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help
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Enable an interrupt handler table implemented in software. This
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table, unlike ISRs connected directly in the vector table, allow
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a parameter to be passed to the interrupt handlers. Also, invoking
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the exeception/interrupt exit stub is automatically done.
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config IRQ_VECTOR_TABLE_CUSTOM
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bool
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prompt "Projects provide a custom static IRQ part of vector table"
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depends on !SW_ISR_TABLE
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default n
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help
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Projects, not the BSP, provide the IRQ part of the vector table.
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This is the table of interrupt handlers with the best potential
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performance, but is the less flexible.
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The ISRs are installed directly in the vector table, thus are
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directly called by the CPU when an interrupt is taken. This adds
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the least overhead when handling an interrupt.
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Downsides:
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- ISRs cannot have a parameter
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- ISRs cannot be connected at runtime
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- ISRs must notify the kernel manually by invoking _ExcExit() when
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then are about to return.
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config IRQ_VECTOR_TABLE_BSP
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bool
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# omit prompt to signify a "hidden" option
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depends on SW_ISR_TABLE || !IRQ_VECTOR_TABLE_CUSTOM
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default y
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help
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Not user-selectable, helps build system logic.
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config CACHE_LINE_SIZE_DETECT
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bool
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prompt "Detect d-cache line size at runtime"
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@ -16,5 +16,3 @@ obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
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# Some ARC cores like the EM4 lack the atomic LLOCK/SCOND and
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# can't use these.
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obj-$(CONFIG_ATOMIC_OPERATIONS_CUSTOM) += atomic.o
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obj-$(CONFIG_IRQ_VECTOR_TABLE_BSP) += irq_vector_table.o
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obj-$(CONFIG_SW_ISR_TABLE) += sw_isr_table.o
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@ -72,7 +72,7 @@ SECTION_FUNC(TEXT, _firq_enter)
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* If CONFIG_RGF_NUM_BANKS>1, firq uses a 2nd register bank so GPRs do
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* not need to be saved.
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* If CONFIG_RGF_NUM_BANKS==1, firq must use the stack to save registers.
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* This has already been done by _isr_enter.
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* This has already been done by _isr_wrapper.
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*/
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#ifdef CONFIG_ARC_STACK_CHECKING
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@ -1,43 +0,0 @@
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/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief IRQ part of vector table for Quark SE Sensor Subsystem
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*
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* This file contains the IRQ part of the vector table. It is meant to be used
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* for one of two cases:
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*
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* a) When software-managed ISRs (SW_ISR_TABLE) is enabled, and in that case it
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* binds _IsrWrapper() to all the IRQ entries in the vector table.
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*
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* b) When the BSP is written so that device ISRs are installed directly in the
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* vector table, they are enumerated here.
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*
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*/
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#include <toolchain.h>
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#include <sections.h>
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extern void _isr_enter(void);
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typedef void (*vth)(void); /* Vector Table Handler */
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#if defined(CONFIG_SW_ISR_TABLE)
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vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
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[0 ...(CONFIG_NUM_IRQS - 17)] = _isr_enter
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};
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#elif !defined(CONFIG_IRQ_VECTOR_TABLE_CUSTOM)
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extern void _SpuriousIRQ(void);
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/* placeholders: fill with real ISRs */
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vth __irq_vector_table _irq_vector_table[CONFIG_NUM_IRQS - 16] = {
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[0 ...(CONFIG_NUM_IRQS - 17)] = _SpuriousIRQ
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};
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#endif /* CONFIG_SW_ISR_TABLE */
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@ -20,7 +20,7 @@
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#include <kernel_structs.h>
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#include <arch/cpu.h>
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GTEXT(_isr_enter)
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GTEXT(_isr_wrapper)
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GTEXT(_isr_demux)
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#if CONFIG_RGF_NUM_BANKS == 1
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@ -41,9 +41,9 @@ _rirq_enter/_firq_enter: they are jump points.
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The flow is the following:
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ISR -> _isr_enter -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
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+ -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
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ISR -> _isr_wrapper -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
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+ -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
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Context switch explanation:
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@ -216,7 +216,7 @@ From RIRQ:
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interrupt.
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*/
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SECTION_FUNC(TEXT, _isr_enter)
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SECTION_FUNC(TEXT, _isr_wrapper)
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#if CONFIG_RGF_NUM_BANKS == 1
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st r0,[saved_r0]
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#endif
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@ -1,52 +0,0 @@
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/* sw_isr_table.S - ISR table for static ISR declarations for ARC */
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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/*
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* enable preprocessor features, such
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* as %expr - evaluate the expression and use it as a string
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*/
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.altmacro
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/*
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* Define an ISR table entry
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* Define symbol as weak and give the section .gnu.linkonce
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* prefix. This allows linker overload the symbol and the
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* whole section by the one defined by a device driver
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*/
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.macro _isr_table_entry_declare index
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WDATA(_isr_irq\index)
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.section .gnu.linkonce.isr_irq\index
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_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
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.endm
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/*
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* Declare the ISR table
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*/
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.macro _isr_table_declare from, to
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counter = \from
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.rept (\to - \from)
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_isr_table_entry_declare %counter
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counter = counter + 1
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.endr
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.endm
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GTEXT(_irq_spurious)
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GDATA(_sw_isr_table)
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.section .isr_irq16
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.align
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_sw_isr_table:
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/*In ARC architecture, IRQ 0-15 are reserved for the system and are not
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assignable by the user, for that reason the isr table linker section
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start at IRQ 16*/
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_isr_table_declare 16 CONFIG_NUM_IRQS
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@ -134,7 +134,7 @@ parameter.
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executing. A common interrupt handler demuxer is installed for all entries of
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the real interrupt vector table, which then fetches the device's ISR and
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parameter from the separate table. This approach is commonly used in the ARC
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and ARM architectures via the :option:`CONFIG_SW_ISR_TABLE` implementation.
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and ARM architectures via the :option:`CONFIG_GEN_ISR_TABLES` implementation.
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You can find examples of the stubs by looking at :code:`_interrupt_enter()` in
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x86, :code:`_IntExit()` in ARM, :code:`_isr_wrapper()` in ARM, or the full
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implementation description for ARC in :file:`arch/arc/core/isr_wrapper.S`.
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@ -43,53 +43,4 @@ extern "C" {
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#ifdef __cplusplus
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}
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#endif
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#ifndef _ASMLANGUAGE
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#include <irq.h>
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/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
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extern void _irq_priority_set(unsigned int irq, unsigned int prio,
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uint32_t flags);
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/**
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* Configure a static interrupt.
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*
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* All arguments must be computable by the compiler at build time.
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*
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* Internally this function does a few things:
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*
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* 1. The enum statement has no effect but forces the compiler to only
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* accept constant values for the irq_p parameter, very important as the
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* numerical IRQ line is used to create a named section.
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*
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* 2. An instance of struct _isr_table_entry is created containing the ISR and
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* its parameter. If you look at how _sw_isr_table is created, each entry in
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* the array is in its own section named by the IRQ line number. What we are
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* doing here is to override one of the default entries (which points to the
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* spurious IRQ handler) with what was supplied here.
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*
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* 3. The priority level for the interrupt is configured by a call to
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* _irq_priority_set()
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority, in range 0-13
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ options (ignored for now)
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*
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* @return The vector assigned to this interrupt
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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enum { IRQ = irq_p }; \
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static struct _isr_table_entry _CONCAT(_isr_irq, irq_p) \
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__attribute__ ((used)) \
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__attribute__ ((section(STRINGIFY(_CONCAT(.gnu.linkonce.isr_irq, irq_p))))) = \
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{isr_param_p, isr_p}; \
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_irq_priority_set(irq_p, priority_p, flags_p); \
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irq_p; \
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})
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#endif
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#endif /* _ARC_ARCH__H_ */
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@ -18,6 +18,7 @@
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#include <toolchain/common.h>
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#include <irq.h>
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#include <misc/util.h>
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#include <sw_isr_table.h>
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#ifdef __cplusplus
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extern "C" {
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@ -33,6 +34,40 @@ extern void _arch_irq_enable(unsigned int irq);
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extern void _arch_irq_disable(unsigned int irq);
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extern void _irq_exit(void);
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extern void _irq_priority_set(unsigned int irq, unsigned int prio,
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uint32_t flags);
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extern void _isr_wrapper(void);
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extern void _irq_spurious(void *unused);
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/**
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* Configure a static interrupt.
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*
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* All arguments must be computable by the compiler at build time.
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*
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* _ISR_DECLARE will populate the .intList section with the interrupt's
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* parameters, which will then be used by gen_irq_tables.py to create
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* the vector table and the software ISR table. This is all done at
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* build-time.
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*
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* We additionally set the priority in the interrupt controller at
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* runtime.
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority
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* @param isr_p Interrupt service routine
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* @param isr_param_p ISR parameter
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* @param flags_p IRQ options
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*
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* @return The vector assigned to this interrupt
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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_irq_priority_set(irq_p, priority_p, flags_p); \
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irq_p; \
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})
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/**
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*
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@ -57,6 +57,8 @@ MEMORY {
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#ifdef DCCM_START
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DCCM (rw) : ORIGIN = DCCM_START, LENGTH = DCCM_SIZE*1k
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#endif
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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SECTIONS {
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KEEP(*(".exc_vector_table.*"))
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KEEP(*(IRQ_VECTOR_TABLE))
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KEEP(*(.isr_irq*))
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/*
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* The following sections maps the location of the different
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* rows for the _sw_isr_table. Each row maps to an IRQ entry
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* (handler, argument).
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*
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* In ARC architecture, IRQ 0-15 are reserved for the system
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* and are not * assignable by the user, for that reason the
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* linker sections start on IRQ 16
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*/
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/* sections for IRQ16-19 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[1][6-9])))
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/* sections for IRQ20-99 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[2-9][0-9])))
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/* sections for IRQ100-999 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[1-9][0-9][0-9])))
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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KEEP(*(SW_ISR_TABLE))
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#endif
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*(.text)
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*(".text.*")
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*(.gnu.linkonce.t.*)
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#include <custom-sections.ld>
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#endif
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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