arm: Replace CONFIG_CPU_CORTEX_M0_M0PLUS with CONFIG_ARMV6_M
Precursor patches have arranged all conditional compilation hanging on CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support for ARM ARMv6-M, rename the config variable to reflect this. Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
parent
e2d3cc4b81
commit
727dc2c5d6
16 changed files with 93 additions and 93 deletions
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@ -60,14 +60,14 @@ config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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This option signifies the CPU faults other than the hard fault, and
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needs to reserve a priority for them.
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config CPU_CORTEX_M0_M0PLUS
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config ARMV6_M
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bool
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# Omit prompt to signify "hidden" option
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default n
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select ATOMIC_OPERATIONS_C
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select ISA_THUMB2
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help
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This option signifies the use of either a Cortex-M0 or Cortex-M0+ CPU.
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This option signifies the use of an ARMv6-M processor implementation.
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config CPU_CORTEX_M3_M4
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bool
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@ -83,14 +83,14 @@ config CPU_CORTEX_M3_M4
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config CPU_CORTEX_M0
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bool
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# Omit prompt to signify "hidden" option
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select CPU_CORTEX_M0_M0PLUS
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select ARMV6_M
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help
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This option signifies the use of a Cortex-M0 CPU
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config CPU_CORTEX_M0PLUS
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bool
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# Omit prompt to signify "hidden" option
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select CPU_CORTEX_M0_M0PLUS
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select ARMV6_M
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help
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This option signifies the use of a Cortex-M0+ CPU
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@ -211,7 +211,7 @@ config FLASH_BASE_ADDRESS
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endmenu
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menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
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depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
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depends on ARMV6_M || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
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config IRQ_OFFLOAD
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bool "Enable IRQ offload"
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@ -72,14 +72,14 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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#endif
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/* lock interrupts: will get unlocked when switch to main task */
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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cpsid i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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#ifdef CONFIG_WDOG_INIT
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/* board-specific watchdog initialization is necessary */
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@ -90,7 +90,7 @@ void sys_arch_reboot(int type)
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DO_REBOOT();
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}
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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@ -138,4 +138,4 @@ void _ScbNumPriGroupSet(unsigned int n)
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}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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@ -56,7 +56,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
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.word __nmi
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.word __hard_fault
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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.word __reserved
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.word __reserved
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.word __reserved
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@ -78,7 +78,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
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.word __debug_monitor
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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.word __reserved
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.word __pendsv
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#if defined(CONFIG_CORTEX_M_SYSTICK)
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@ -48,7 +48,7 @@ GTEXT(_vector_table)
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GTEXT(__reset)
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GTEXT(__nmi)
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GTEXT(__hard_fault)
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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@ -57,7 +57,7 @@ GTEXT(__svc)
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GTEXT(__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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GTEXT(__pendsv)
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GTEXT(__reserved)
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@ -127,7 +127,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
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mov lr, r0
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#endif
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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cpsie i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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/* clear BASEPRI so wfi is awakened by incoming interrupts */
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@ -135,7 +135,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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wfi
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@ -184,7 +184,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
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/* r0: interrupt mask from caller */
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
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wfe
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@ -206,5 +206,5 @@ _irq_disabled:
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cpsie i
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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bx lr
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@ -69,7 +69,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
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k_current_get(),
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esf->pc);
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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int escalation = 0;
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@ -103,7 +103,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
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_ScbUsageFaultAllFaultsReset();
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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}
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#endif
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@ -123,7 +123,7 @@ static void _FaultThreadShow(const NANO_ESF *esf)
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k_current_get(), esf->pc);
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}
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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@ -250,7 +250,7 @@ static void _DebugMonitor(const NANO_ESF *esf)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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/**
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*
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@ -264,7 +264,7 @@ static void _HardFault(const NANO_ESF *esf)
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{
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PR_EXC("***** HARD FAULT *****\n");
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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_FaultThreadShow(esf);
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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if (_ScbHardFaultIsBusErrOnVectorRead()) {
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@ -281,7 +281,7 @@ static void _HardFault(const NANO_ESF *esf)
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}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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}
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/**
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@ -326,7 +326,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
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case 3:
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_HardFault(esf);
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break;
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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case 4:
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_MpuFault(esf, 0);
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@ -342,7 +342,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
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break;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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default:
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_ReservedException(esf, fault);
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break;
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@ -387,10 +387,10 @@ void _Fault(const NANO_ESF *esf)
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*/
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void _FaultInit(void)
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{
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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_ScbDivByZeroFaultEnable();
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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}
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@ -32,7 +32,7 @@ _ASM_FILE_PROLOGUE
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GTEXT(_Fault)
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GTEXT(__hard_fault)
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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@ -40,7 +40,7 @@ GTEXT(__usage_fault)
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GTEXT(__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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GTEXT(__reserved)
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/**
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@ -67,7 +67,7 @@ GTEXT(__reserved)
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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/* force unlock interrupts */
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cpsie i
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@ -114,7 +114,7 @@ _stack_frame_endif:
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* frame is on the PSP */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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push {lr}
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bl _Fault
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@ -80,7 +80,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
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ldr r0, [r2, #_kernel_offset_to_idle]
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cmp r0, #0
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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beq _idle_state_cleared
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movs.n r1, #0
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/* clear kernel idle state */
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blxne _sys_power_save_idle_exit
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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cpsie i /* re-enable interrupts (PRIMASK = 0) */
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#endif
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mrs r0, IPSR /* get exception number */
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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ldr r1, =16
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subs r0, r1 /* get IRQ number */
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lsls r0, #3 /* table is 8-byte wide */
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@ -111,7 +111,7 @@ _idle_state_cleared:
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lsl r0, r0, #3 /* table is 8-byte wide */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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ldr r1, =_sw_isr_table
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add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
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* in thumb mode */
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@ -119,14 +119,14 @@ _idle_state_cleared:
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ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
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blx r3 /* call ISR */
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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pop {r3}
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mov lr, r3
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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pop {lr}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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/* exception return is done in _IntExit() */
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b _IntExit
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@ -32,12 +32,12 @@
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_ASM_FILE_PROLOGUE
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GTEXT(_Swap)
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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GTEXT(__svc)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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GTEXT(__pendsv)
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GDATA(_k_neg_eagain)
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/* save callee-saved + psp in TCS */
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mrs ip, PSP
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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/* Store current r4-r7 */
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stmea r0!, {r4-r7}
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/* copy r8-r12 into r3-r7 */
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@ -96,7 +96,7 @@ SECTION_FUNC(TEXT, __pendsv)
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#endif /* CONFIG_FP_SHARING */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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/*
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* Prepare to clear PendSV with interrupts unlocked, but
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@ -109,14 +109,14 @@ SECTION_FUNC(TEXT, __pendsv)
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ldr v3, =_SCS_ICSR_UNPENDSV
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/* protect the kernel state while we play with the thread lists */
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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cpsid i
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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/* _kernel is still in r1 */
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@ -142,7 +142,7 @@ SECTION_FUNC(TEXT, __pendsv)
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movs.n r3, #0
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str r3, [r2, #_thread_offset_to_basepri]
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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/* BASEPRI not available, previous interrupt disable state
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* maps to PRIMASK.
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*
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@ -184,14 +184,14 @@ _thread_irq_disabled:
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ldmia r0, {v1-v8, ip}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
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#endif /* CONFIG_ARMV6_M */
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msr PSP, ip
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/* exc return */
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bx lr
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#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
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/**
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*
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||||
|
@ -249,7 +249,7 @@ _context_switch:
|
|||
bx lr
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
/**
|
||||
*
|
||||
|
@ -302,7 +302,7 @@ SECTION_FUNC(TEXT, _Swap)
|
|||
ldr r1, [r1]
|
||||
str r1, [r2, #_thread_offset_to_swap_return_value]
|
||||
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
/* No priority-based interrupt masking on M0/M0+,
|
||||
* pending PendSV is used instead of svc
|
||||
*/
|
||||
|
@ -320,7 +320,7 @@ SECTION_FUNC(TEXT, _Swap)
|
|||
svc #0
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
/* coming back from exception, r2 still holds the pointer to _current */
|
||||
ldr r0, [r2, #_thread_offset_to_swap_return_value]
|
||||
|
|
|
@ -58,13 +58,13 @@ static ALWAYS_INLINE int _IsInIsr(void)
|
|||
* On ARMv6-M there is no nested execution bit, so we check exception 3,
|
||||
* hard fault, to a detect a nested exception.
|
||||
*/
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
return (vector > 10) || (vector == 3);
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
return (vector > 10) || (vector && _ScbIsNestedExc());
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -67,14 +67,14 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size,
|
|||
"msr PSP, %0 \t\n"
|
||||
|
||||
/* unlock interrupts */
|
||||
#ifdef CONFIG_CPU_CORTEX_M0_M0PLUS
|
||||
#ifdef CONFIG_ARMV6_M
|
||||
"cpsie i \t\n"
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
"movs %%r1, #0 \n\t"
|
||||
"msr BASEPRI, %%r1 \n\t"
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
/* branch to _thread_entry(_main, 0, 0, 0) */
|
||||
"mov %%r0, %1 \n\t"
|
||||
|
|
|
@ -128,7 +128,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
|
|||
{
|
||||
unsigned int key;
|
||||
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
__asm__ volatile("mrs %0, PRIMASK;"
|
||||
"cpsid i"
|
||||
: "=r" (key)
|
||||
|
@ -146,7 +146,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
|
|||
: "memory");
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
return key;
|
||||
}
|
||||
|
@ -173,7 +173,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
|
|||
|
||||
static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
|
||||
{
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
if (key) {
|
||||
return;
|
||||
}
|
||||
|
@ -182,7 +182,7 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
|
|||
__asm__ volatile("msr BASEPRI, %0" : : "r"(key) : "memory");
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -201,7 +201,7 @@ static inline void _NvicIrqUnpend(unsigned int irq)
|
|||
|
||||
static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
|
||||
{
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
volatile uint32_t * const ipr = &__scs.nvic.ipr[_PRIO_IP_IDX(irq)];
|
||||
*ipr = ((*ipr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(irq))) |
|
||||
((uint32_t)prio << _PRIO_BIT_SHIFT(irq)));
|
||||
|
@ -209,7 +209,7 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
|
|||
__scs.nvic.ipr[irq] = prio;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -225,16 +225,16 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
|
|||
|
||||
static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
|
||||
{
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
return (__scs.nvic.ipr[_PRIO_IP_IDX(irq)] >> _PRIO_BIT_SHIFT(irq));
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
return __scs.nvic.ipr[irq];
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
/**
|
||||
*
|
||||
|
@ -258,7 +258,7 @@ static inline void _NvicSwInterruptTrigger(unsigned int irq)
|
|||
}
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
|
|
|
@ -439,7 +439,7 @@ static inline void ScbCcrSet(uint32_t val)
|
|||
|
||||
static inline uint8_t _ScbExcPrioGet(uint8_t exc)
|
||||
{
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
__ASSERT((exc > 10) && (exc < 16), "");
|
||||
return (__scs.scb.shpr[_PRIO_SHP_IDX(exc)] >> _PRIO_BIT_SHIFT(exc));
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
|
@ -448,7 +448,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc)
|
|||
return __scs.scb.shpr[exc - 4];
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -472,7 +472,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc)
|
|||
|
||||
static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
|
||||
{
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
volatile uint32_t * const shpr = &__scs.scb.shpr[_PRIO_SHP_IDX(exc)];
|
||||
__ASSERT((exc > 10) && (exc < 16), "");
|
||||
*shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) |
|
||||
|
@ -483,10 +483,10 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
|
|||
__scs.scb.shpr[exc - 4] = pri;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
/**
|
||||
*
|
||||
|
@ -1229,7 +1229,7 @@ static inline void _ScbUsageFaultAllFaultsReset(void)
|
|||
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
|
|
@ -115,7 +115,7 @@ union __cpuid {
|
|||
union __icsr {
|
||||
uint32_t val;
|
||||
struct {
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t vectactive : 9 __packed;
|
||||
uint32_t rsvd__9_10_11 : 3 __packed;
|
||||
uint32_t vectpending : 9 __packed;
|
||||
|
@ -127,7 +127,7 @@ union __icsr {
|
|||
uint32_t vectpending : 10 __packed;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
uint32_t isrpending : 1 __packed;
|
||||
uint32_t rsvd__23 : 1 __packed;
|
||||
uint32_t rsvd__24 : 1 __packed;
|
||||
|
@ -153,16 +153,16 @@ union __vtor {
|
|||
union __aircr {
|
||||
uint32_t val;
|
||||
struct {
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd__0 : 1 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t vecreset : 1 __packed; /* WO */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
uint32_t vectclractive : 1 __packed; /* WO */
|
||||
uint32_t sysresetreq : 1 __packed; /* WO */
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd__3_14 : 12 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t rsvd__3_7 : 5 __packed;
|
||||
|
@ -170,7 +170,7 @@ union __aircr {
|
|||
uint32_t rsvd__11_14 : 4 __packed;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
uint32_t endianness : 1 __packed; /* RO */
|
||||
uint32_t vectkey : 16 __packed;
|
||||
} bit;
|
||||
|
@ -193,7 +193,7 @@ union __scr {
|
|||
union __ccr {
|
||||
uint32_t val;
|
||||
struct {
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_0_2 : 3 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t nonbasethrdena : 1 __packed;
|
||||
|
@ -201,9 +201,9 @@ union __ccr {
|
|||
uint32_t rsvd__2 : 1 __packed;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
uint32_t unalign_trp : 1 __packed;
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_4_8 : 5 __packed;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
uint32_t div_0_trp : 1 __packed;
|
||||
|
@ -211,7 +211,7 @@ union __ccr {
|
|||
uint32_t bfhfnmign : 1 __packed;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
uint32_t stkalign : 1 __packed;
|
||||
uint32_t rsvd__10_31 : 22 __packed;
|
||||
} bit;
|
||||
|
@ -487,7 +487,7 @@ struct __scs {
|
|||
uint32_t rsvd__320_37f[24];
|
||||
|
||||
uint32_t rsvd__380_3ff[32];
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t ipr[8];
|
||||
uint32_t rsvd__420_4ff[56];
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
|
@ -495,7 +495,7 @@ struct __scs {
|
|||
uint32_t rsvd__4f0_4ff[4];
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
} nvic; /* offset: 0x100, size 0x400 */
|
||||
|
||||
uint32_t rsvd__500_cff[(0xd00 - 0x500) / 4];
|
||||
|
@ -504,18 +504,18 @@ struct __scs {
|
|||
struct {
|
||||
union __cpuid cpuid; /* 0xd00 CPUID register */
|
||||
union __icsr icsr; /* 0xd04 IRQ Control and Start Register */
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_9_12;
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
union __vtor vtor; /* 0xd08 Vector Table Offset Register */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
union __aircr
|
||||
aircr; /* 0xd0c App IRQ and Reset Control Register */
|
||||
union __scr scr; /* 0xd10 System Control Register */
|
||||
union __ccr ccr; /* 0xd14 Configuration and Control Register */
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_24_27;
|
||||
uint32_t shpr[2];
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
|
@ -525,10 +525,10 @@ struct __scs {
|
|||
*/
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
union __shcsr
|
||||
shcsr; /* 0xd24 Sys Handler Control and State Reg */
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
uint32_t rsvd_40_63[6];
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register
|
||||
|
@ -540,7 +540,7 @@ struct __scs {
|
|||
uint32_t afsr; /* 0xd3C Aux Fault Status Register */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
} scb; /* offset: 0xd00, size 0x040 */
|
||||
|
||||
/*
|
||||
|
@ -588,7 +588,7 @@ struct __scs {
|
|||
/* the linker always puts this object at 0xe000e000 */
|
||||
extern volatile struct __scs __scs;
|
||||
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and masks */
|
||||
#define _PRIO_BIT_SHIFT(IRQn) (((((uint32_t)(IRQn))) & 0x03UL) * 8UL)
|
||||
|
@ -597,10 +597,10 @@ extern volatile struct __scs __scs;
|
|||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
/* API */
|
||||
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
|
||||
/**
|
||||
*
|
||||
|
@ -739,7 +739,7 @@ static inline void _scs_relocate_vector_table(void *new_addr)
|
|||
}
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue