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arm: Replace CONFIG_CPU_CORTEX_M0_M0PLUS with CONFIG_ARMV6_M

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Precursor patches have arranged all conditional compilation hanging on
CONFIG_CPU_CORTEX_M0_M0PLUS such that it actually represents support
for ARM ARMv6-M, rename the config variable to reflect this.

Change-Id: I553fcf3e606b350a9e823df31bac96636be1504f
Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
This commit is contained in:
Marcus Shawcroft 2016-12-31 14:09:41 +00:00 • committed by Kumar Gala
commit 727dc2c5d6
16 changed files with 93 additions and 93 deletions
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10
arch/arm/core/cortex_m/Kconfig
View file

@ -60,14 +60,14 @@ config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
This option signifies the CPU faults other than the hard fault, and
needs to reserve a priority for them.
config CPU_CORTEX_M0_M0PLUS
config ARMV6_M
bool
# Omit prompt to signify "hidden" option
default n
select ATOMIC_OPERATIONS_C
select ISA_THUMB2
help
This option signifies the use of either a Cortex-M0 or Cortex-M0+ CPU.
This option signifies the use of an ARMv6-M processor implementation.
config CPU_CORTEX_M3_M4
bool
@ -83,14 +83,14 @@ config CPU_CORTEX_M3_M4
config CPU_CORTEX_M0
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M0_M0PLUS
select ARMV6_M
help
This option signifies the use of a Cortex-M0 CPU
config CPU_CORTEX_M0PLUS
bool
# Omit prompt to signify "hidden" option
select CPU_CORTEX_M0_M0PLUS
select ARMV6_M
help
This option signifies the use of a Cortex-M0+ CPU
@ -211,7 +211,7 @@ config FLASH_BASE_ADDRESS
endmenu
menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
depends on ARMV6_M || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
config IRQ_OFFLOAD
bool "Enable IRQ offload"

4
arch/arm/core/cortex_m/reset.S
View file

@ -72,14 +72,14 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
#endif
/* lock interrupts: will get unlocked when switch to main task */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsid i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
#ifdef CONFIG_WDOG_INIT
/* board-specific watchdog initialization is necessary */

4
arch/arm/core/cortex_m/scb.c
View file

@ -90,7 +90,7 @@ void sys_arch_reboot(int type)
DO_REBOOT();
}
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -138,4 +138,4 @@ void _ScbNumPriGroupSet(unsigned int n)
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */

4
arch/arm/core/cortex_m/vector_table.S
View file

@ -56,7 +56,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __nmi
.word __hard_fault
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
.word __reserved
.word __reserved
.word __reserved
@ -78,7 +78,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,__start)
.word __debug_monitor
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
.word __reserved
.word __pendsv
#if defined(CONFIG_CORTEX_M_SYSTICK)

4
arch/arm/core/cortex_m/vector_table.h
View file

@ -48,7 +48,7 @@ GTEXT(_vector_table)
GTEXT(__reset)
GTEXT(__nmi)
GTEXT(__hard_fault)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
@ -57,7 +57,7 @@ GTEXT(__svc)
GTEXT(__debug_monitor)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
GTEXT(__pendsv)
GTEXT(__reserved)

8
arch/arm/core/cpu_idle.S
View file

@ -127,7 +127,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
mov lr, r0
#endif
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsie i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/* clear BASEPRI so wfi is awakened by incoming interrupts */
@ -135,7 +135,7 @@ SECTION_FUNC(TEXT, k_cpu_idle)
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
wfi
@ -184,7 +184,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
/* r0: interrupt mask from caller */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
wfe
@ -206,5 +206,5 @@ _irq_disabled:
cpsie i
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
bx lr

20
arch/arm/core/fault.c
View file

@ -69,7 +69,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
k_current_get(),
esf->pc);
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
int escalation = 0;
@ -103,7 +103,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
_ScbUsageFaultAllFaultsReset();
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
#endif
@ -123,7 +123,7 @@ static void _FaultThreadShow(const NANO_ESF *esf)
k_current_get(), esf->pc);
}
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
@ -250,7 +250,7 @@ static void _DebugMonitor(const NANO_ESF *esf)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/**
*
@ -264,7 +264,7 @@ static void _HardFault(const NANO_ESF *esf)
{
PR_EXC("***** HARD FAULT *****\n");
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
_FaultThreadShow(esf);
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
if (_ScbHardFaultIsBusErrOnVectorRead()) {
@ -281,7 +281,7 @@ static void _HardFault(const NANO_ESF *esf)
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
/**
@ -326,7 +326,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
case 3:
_HardFault(esf);
break;
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
case 4:
_MpuFault(esf, 0);
@ -342,7 +342,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
break;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
default:
_ReservedException(esf, fault);
break;
@ -387,10 +387,10 @@ void _Fault(const NANO_ESF *esf)
*/
void _FaultInit(void)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
_ScbDivByZeroFaultEnable();
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}

12
arch/arm/core/fault_s.S
View file

@ -32,7 +32,7 @@ _ASM_FILE_PROLOGUE
GTEXT(_Fault)
GTEXT(__hard_fault)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__mpu_fault)
GTEXT(__bus_fault)
@ -40,7 +40,7 @@ GTEXT(__usage_fault)
GTEXT(__debug_monitor)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
GTEXT(__reserved)
/**
@ -67,7 +67,7 @@ GTEXT(__reserved)
*/
SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
@ -75,10 +75,10 @@ SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* force unlock interrupts */
cpsie i
@ -114,7 +114,7 @@ _stack_frame_endif:
* frame is on the PSP */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
push {lr}
bl _Fault

12
arch/arm/core/isr_wrapper.S
View file

@ -80,7 +80,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
ldr r0, [r2, #_kernel_offset_to_idle]
cmp r0, #0
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
beq _idle_state_cleared
movs.n r1, #0
/* clear kernel idle state */
@ -96,13 +96,13 @@ _idle_state_cleared:
blxne _sys_power_save_idle_exit
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
cpsie i /* re-enable interrupts (PRIMASK = 0) */
#endif
mrs r0, IPSR /* get exception number */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
ldr r1, =16
subs r0, r1 /* get IRQ number */
lsls r0, #3 /* table is 8-byte wide */
@ -111,7 +111,7 @@ _idle_state_cleared:
lsl r0, r0, #3 /* table is 8-byte wide */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
ldr r1, =_sw_isr_table
add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
* in thumb mode */
@ -119,14 +119,14 @@ _idle_state_cleared:
ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
blx r3 /* call ISR */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
pop {r3}
mov lr, r3
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
pop {lr}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* exception return is done in _IntExit() */
b _IntExit

24
arch/arm/core/swap.S
View file

@ -32,12 +32,12 @@
_ASM_FILE_PROLOGUE
GTEXT(_Swap)
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
GTEXT(__svc)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
GTEXT(__pendsv)
GDATA(_k_neg_eagain)
@ -77,7 +77,7 @@ SECTION_FUNC(TEXT, __pendsv)
/* save callee-saved + psp in TCS */
mrs ip, PSP
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* Store current r4-r7 */
stmea r0!, {r4-r7}
/* copy r8-r12 into r3-r7 */
@ -96,7 +96,7 @@ SECTION_FUNC(TEXT, __pendsv)
#endif /* CONFIG_FP_SHARING */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/*
* Prepare to clear PendSV with interrupts unlocked, but
@ -109,14 +109,14 @@ SECTION_FUNC(TEXT, __pendsv)
ldr v3, =_SCS_ICSR_UNPENDSV
/* protect the kernel state while we play with the thread lists */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
cpsid i
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
msr BASEPRI, r0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* _kernel is still in r1 */
@ -142,7 +142,7 @@ SECTION_FUNC(TEXT, __pendsv)
movs.n r3, #0
str r3, [r2, #_thread_offset_to_basepri]
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* BASEPRI not available, previous interrupt disable state
* maps to PRIMASK.
*
@ -184,14 +184,14 @@ _thread_irq_disabled:
ldmia r0, {v1-v8, ip}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
msr PSP, ip
/* exc return */
bx lr
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -249,7 +249,7 @@ _context_switch:
bx lr
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/**
*
@ -302,7 +302,7 @@ SECTION_FUNC(TEXT, _Swap)
ldr r1, [r1]
str r1, [r2, #_thread_offset_to_swap_return_value]
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* No priority-based interrupt masking on M0/M0+,
* pending PendSV is used instead of svc
*/
@ -320,7 +320,7 @@ SECTION_FUNC(TEXT, _Swap)
svc #0
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* coming back from exception, r2 still holds the pointer to _current */
ldr r0, [r2, #_thread_offset_to_swap_return_value]

4
arch/arm/include/cortex_m/exc.h
View file

@ -58,13 +58,13 @@ static ALWAYS_INLINE int _IsInIsr(void)
* On ARMv6-M there is no nested execution bit, so we check exception 3,
* hard fault, to a detect a nested exception.
*/
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
return (vector > 10) || (vector == 3);
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
return (vector > 10) || (vector && _ScbIsNestedExc());
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
/**

4
arch/arm/include/kernel_arch_func.h
View file

@ -67,14 +67,14 @@ _arch_switch_to_main_thread(char *main_stack, size_t main_stack_size,
"msr PSP, %0 \t\n"
/* unlock interrupts */
#ifdef CONFIG_CPU_CORTEX_M0_M0PLUS
#ifdef CONFIG_ARMV6_M
"cpsie i \t\n"
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
"movs %%r1, #0 \n\t"
"msr BASEPRI, %%r1 \n\t"
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* branch to _thread_entry(_main, 0, 0, 0) */
"mov %%r0, %1 \n\t"

8
include/arch/arm/cortex_m/asm_inline_gcc.h
View file

@ -128,7 +128,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
{
unsigned int key;
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
__asm__ volatile("mrs %0, PRIMASK;"
"cpsid i"
: "=r" (key)
@ -146,7 +146,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
: "memory");
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
return key;
}
@ -173,7 +173,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
if (key) {
return;
}
@ -182,7 +182,7 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
__asm__ volatile("msr BASEPRI, %0" : : "r"(key) : "memory");
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}

12
include/arch/arm/cortex_m/nvic.h
View file

@ -201,7 +201,7 @@ static inline void _NvicIrqUnpend(unsigned int irq)
static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
volatile uint32_t * const ipr = &__scs.nvic.ipr[_PRIO_IP_IDX(irq)];
*ipr = ((*ipr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(irq))) |
((uint32_t)prio << _PRIO_BIT_SHIFT(irq)));
@ -209,7 +209,7 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
__scs.nvic.ipr[irq] = prio;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
/**
@ -225,16 +225,16 @@ static inline void _NvicIrqPrioSet(unsigned int irq, uint8_t prio)
static inline uint8_t _NvicIrqPrioGet(unsigned int irq)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
return (__scs.nvic.ipr[_PRIO_IP_IDX(irq)] >> _PRIO_BIT_SHIFT(irq));
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
return __scs.nvic.ipr[irq];
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -258,7 +258,7 @@ static inline void _NvicSwInterruptTrigger(unsigned int irq)
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
#endif /* !_ASMLANGUAGE */

12
include/arch/arm/cortex_m/scb.h
View file

@ -439,7 +439,7 @@ static inline void ScbCcrSet(uint32_t val)
static inline uint8_t _ScbExcPrioGet(uint8_t exc)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
__ASSERT((exc > 10) && (exc < 16), "");
return (__scs.scb.shpr[_PRIO_SHP_IDX(exc)] >> _PRIO_BIT_SHIFT(exc));
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
@ -448,7 +448,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc)
return __scs.scb.shpr[exc - 4];
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
/**
@ -472,7 +472,7 @@ static inline uint8_t _ScbExcPrioGet(uint8_t exc)
static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
{
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
volatile uint32_t * const shpr = &__scs.scb.shpr[_PRIO_SHP_IDX(exc)];
__ASSERT((exc > 10) && (exc < 16), "");
*shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) |
@ -483,10 +483,10 @@ static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
__scs.scb.shpr[exc - 4] = pri;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
}
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -1229,7 +1229,7 @@ static inline void _ScbUsageFaultAllFaultsReset(void)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
#endif /* _ASMLANGUAGE */

44
include/arch/arm/cortex_m/scs.h
View file

@ -115,7 +115,7 @@ union __cpuid {
union __icsr {
uint32_t val;
struct {
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t vectactive : 9 __packed;
uint32_t rsvd__9_10_11 : 3 __packed;
uint32_t vectpending : 9 __packed;
@ -127,7 +127,7 @@ union __icsr {
uint32_t vectpending : 10 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
uint32_t isrpending : 1 __packed;
uint32_t rsvd__23 : 1 __packed;
uint32_t rsvd__24 : 1 __packed;
@ -153,16 +153,16 @@ union __vtor {
union __aircr {
uint32_t val;
struct {
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd__0 : 1 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t vecreset : 1 __packed; /* WO */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
uint32_t vectclractive : 1 __packed; /* WO */
uint32_t sysresetreq : 1 __packed; /* WO */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd__3_14 : 12 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t rsvd__3_7 : 5 __packed;
@ -170,7 +170,7 @@ union __aircr {
uint32_t rsvd__11_14 : 4 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
uint32_t endianness : 1 __packed; /* RO */
uint32_t vectkey : 16 __packed;
} bit;
@ -193,7 +193,7 @@ union __scr {
union __ccr {
uint32_t val;
struct {
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_0_2 : 3 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t nonbasethrdena : 1 __packed;
@ -201,9 +201,9 @@ union __ccr {
uint32_t rsvd__2 : 1 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
uint32_t unalign_trp : 1 __packed;
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_4_8 : 5 __packed;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
uint32_t div_0_trp : 1 __packed;
@ -211,7 +211,7 @@ union __ccr {
uint32_t bfhfnmign : 1 __packed;
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
uint32_t stkalign : 1 __packed;
uint32_t rsvd__10_31 : 22 __packed;
} bit;
@ -487,7 +487,7 @@ struct __scs {
uint32_t rsvd__320_37f[24];
uint32_t rsvd__380_3ff[32];
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t ipr[8];
uint32_t rsvd__420_4ff[56];
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
@ -495,7 +495,7 @@ struct __scs {
uint32_t rsvd__4f0_4ff[4];
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
} nvic; /* offset: 0x100, size 0x400 */
uint32_t rsvd__500_cff[(0xd00 - 0x500) / 4];
@ -504,18 +504,18 @@ struct __scs {
struct {
union __cpuid cpuid; /* 0xd00 CPUID register */
union __icsr icsr; /* 0xd04 IRQ Control and Start Register */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_9_12;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
union __vtor vtor; /* 0xd08 Vector Table Offset Register */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
union __aircr
aircr; /* 0xd0c App IRQ and Reset Control Register */
union __scr scr; /* 0xd10 System Control Register */
union __ccr ccr; /* 0xd14 Configuration and Control Register */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_24_27;
uint32_t shpr[2];
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
@ -525,10 +525,10 @@ struct __scs {
*/
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
union __shcsr
shcsr; /* 0xd24 Sys Handler Control and State Reg */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
uint32_t rsvd_40_63[6];
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register
@ -540,7 +540,7 @@ struct __scs {
uint32_t afsr; /* 0xd3C Aux Fault Status Register */
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
} scb; /* offset: 0xd00, size 0x040 */
/*
@ -588,7 +588,7 @@ struct __scs {
/* the linker always puts this object at 0xe000e000 */
extern volatile struct __scs __scs;
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and masks */
#define _PRIO_BIT_SHIFT(IRQn) (((((uint32_t)(IRQn))) & 0x03UL) * 8UL)
@ -597,10 +597,10 @@ extern volatile struct __scs __scs;
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
/* API */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
/**
*
@ -739,7 +739,7 @@ static inline void _scs_relocate_vector_table(void *new_addr)
}
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M0_M0PLUS */
#endif /* CONFIG_ARMV6_M */
#endif /* _ASMLANGUAGE */