x86: exception-assisted panic/oops support
We reserve a specific vector in the IDT to trigger when we want to enter a fatal exception state from software. Disabled for drivers/build_all tests as we were up to the ROM limit on Quark D2000. Issue: ZEP-843 Change-Id: I4de7f025fba0691d07bcc3b3f0925973834496a0 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
Anas Nashif
parent
cdb94d6425
commit
7827b7bf4a
7 changed files with 89 additions and 23 deletions
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@ -256,6 +256,26 @@ config IRQ_OFFLOAD_VECTOR
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config X86_KERNEL_OOPS
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bool "Enable handling of kernel oops as an exception"
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default y
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help
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Enable handling of k_oops() API as a CPU exception, which will provide
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extra debugging information such as program counter and register
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values when the oops is triggered. Requires an entry in the IDT.
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config X86_KERNEL_OOPS_VECTOR
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int "IDT vector to use for kernel oops"
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default 62 if MVIC
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default 33 if !MVIC
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range 32 255
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depends on X86_KERNEL_OOPS
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help
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Specify the IDT vector to use for the kernel oops exception handler.
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The default should be fine for most arches, but on systems like MVIC
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where there is a fixed IRQ-to-vector mapping another value may be
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needed to avoid collision.
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config XIP
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default n
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@ -23,8 +23,11 @@
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/* exports (internal APIs) */
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GTEXT(_exception_enter)
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GTEXT(_kernel_oops_handler)
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/* externs (internal APIs) */
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GTEXT(_do_kernel_oops)
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/**
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*
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* @brief Inform the kernel of an exception
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@ -226,3 +229,9 @@ nestedException:
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/* Pop of EFLAGS will re-enable interrupts and restore direction flag */
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iret
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#if CONFIG_X86_KERNEL_OOPS
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SECTION_FUNC(TEXT, _kernel_oops_handler)
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push $0 /* dummy error code */
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push $_do_kernel_oops
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jmp _exception_enter
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#endif
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@ -24,24 +24,6 @@
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__weak void _debug_fatal_hook(const NANO_ESF *esf) { ARG_UNUSED(esf); }
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/*
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* Define a default ESF for use with _NanoFatalErrorHandler() in the event
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* the caller does not have a NANO_ESF to pass
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*/
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const NANO_ESF _default_esf = {
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0xdeaddead, /* ESP */
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0xdeaddead, /* EBP */
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0xdeaddead, /* EBX */
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0xdeaddead, /* ESI */
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0xdeaddead, /* EDI */
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0xdeaddead, /* EDX */
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0xdeaddead, /* ECX */
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0xdeaddead, /* EAX */
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0xdeaddead, /* error code */
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0xdeaddead, /* EIP */
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0xdeaddead, /* CS */
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0xdeaddead, /* EFLAGS */
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};
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/**
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*
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@ -110,9 +92,9 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
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}
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printk("Current thread ID = %p\n"
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"Faulting segment:address = 0x%x:0x%x\n"
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"eax: 0x%x, ebx: 0x%x, ecx: 0x%x, edx: 0x%x\n"
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"esi: 0x%x, edi: 0x%x, ebp: 0%x, esp: 0x%x\n"
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"Faulting segment:address = 0x%04x:0x%08x\n"
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"eax: 0x%08x, ebx: 0x%08x, ecx: 0x%08x, edx: 0x%08x\n"
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"esi: 0x%08x, edi: 0x%08x, ebp: 0x%08x, esp: 0x%08x\n"
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"eflags: 0x%x\n",
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k_current_get(),
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pEsf->cs & 0xFFFF, pEsf->eip,
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@ -130,6 +112,45 @@ FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
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_SysFatalErrorHandler(reason, pEsf);
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}
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#ifdef CONFIG_X86_KERNEL_OOPS
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/* The reason code gets pushed onto the stack right before the exception is
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* triggered, so it would be after the nano_esf data
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*/
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struct oops_esf {
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NANO_ESF nano_esf;
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unsigned int reason;
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};
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FUNC_NORETURN void _do_kernel_oops(const struct oops_esf *esf)
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{
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_NanoFatalErrorHandler(esf->reason, &esf->nano_esf);
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}
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extern void (*_kernel_oops_handler)(void);
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NANO_CPU_INT_REGISTER(_kernel_oops_handler, NANO_SOFT_IRQ,
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CONFIG_X86_KERNEL_OOPS_VECTOR / 16,
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CONFIG_X86_KERNEL_OOPS_VECTOR, 0);
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#else
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/*
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* Define a default ESF for use with _NanoFatalErrorHandler() in the event
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* the caller does not have a NANO_ESF to pass
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*/
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const NANO_ESF _default_esf = {
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0xdeaddead, /* ESP */
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0xdeaddead, /* EBP */
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0xdeaddead, /* EBX */
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0xdeaddead, /* ESI */
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0xdeaddead, /* EDI */
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0xdeaddead, /* EDX */
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0xdeaddead, /* ECX */
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0xdeaddead, /* EAX */
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0xdeaddead, /* error code */
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0xdeaddead, /* EIP */
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0xdeaddead, /* CS */
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0xdeaddead, /* EFLAGS */
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};
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#endif /* CONFIG_X86_KERNEL_OOPS */
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#if CONFIG_EXCEPTION_DEBUG
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static FUNC_NORETURN void generic_exc_handle(unsigned int vector,
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@ -498,11 +498,25 @@ extern u32_t _timer_cycle_get_32(void);
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/** kernel provided routine to report any detected fatal error. */
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extern FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
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const NANO_ESF * pEsf);
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/** User provided routine to handle any detected fatal error post reporting. */
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extern FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
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const NANO_ESF * pEsf);
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#if CONFIG_X86_KERNEL_OOPS
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#define _ARCH_EXCEPT(reason_p) do { \
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__asm__ volatile( \
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"push %[reason]\n\t" \
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"int %[vector]\n\t" \
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: \
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: [vector] "i" (CONFIG_X86_KERNEL_OOPS_VECTOR), \
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[reason] "i" (reason_p)); \
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CODE_UNREACHABLE; \
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} while (0)
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#else
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/** Dummy ESF for fatal errors that would otherwise not have an ESF */
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extern const NANO_ESF _default_esf;
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#endif /* CONFIG_X86_KERNEL_OOPS */
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#endif /* !_ASMLANGUAGE */
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@ -13,3 +13,4 @@ CONFIG_SERIAL=n
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CONFIG_IPM=n
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CONFIG_GPIO=n
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CONFIG_ERRNO=n
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CONFIG_X86_KERNEL_OOPS=n
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@ -8,3 +8,4 @@ CONFIG_PWM=y
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CONFIG_SERIAL=y
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CONFIG_SPI=y
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CONFIG_WATCHDOG=y
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CONFIG_X86_KERNEL_OOPS=n
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@ -23,8 +23,8 @@
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#endif
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/* These vectors are somewhat arbitrary. We try and use unused vectors */
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#define TEST_SOFT_INT 62
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#define TEST_SPUR_INT 63
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#define TEST_SOFT_INT 60
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#define TEST_SPUR_INT 61
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#define MY_STACK_SIZE 2048
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