arch: xtensa: Convert Xtensa port to use gen_isr_table
The Xtensa port was the only one remaining to be converted to the new way of connecting interrupts in Zephyr. Some things are still unconverted, mainly the exception table, and this will be performed another time. Of note: _irq_priority_set() isn't called on _ARCH_IRQ_CONNECT(), since IRQs can't change priority on Xtensa: while the architecture has the concept of interrupt priority levels, each line has a fixed level and can't be changed. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This commit is contained in:
parent
1e506d3b42
commit
27ea2d8eb7
28 changed files with 128 additions and 76 deletions
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@ -4,6 +4,8 @@ OUTPUT_OBJ := isr_tables.o
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ifeq ($(ARCH),riscv32)
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OUTPUT_FORMAT := elf32-littleriscv
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else ifeq ($(ARCH),xtensa)
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OUTPUT_FORMAT := elf32-xtensa-le
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else
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OUTPUT_FORMAT := elf32-little$(ARCH)
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endif
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@ -13,5 +13,3 @@ obj-y = ${obj-atomic} cpu_idle.o fatal.o \
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xtensa_intr.o xtensa_vectors.o irq_manage.o
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obj-$(CONFIG_XTENSA_USE_CORE_CRT1) += crt1.o
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obj-$(CONFIG_IRQ_OFFLOAD) += irq_offload.o
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# Keep this last so that vague linking works
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obj-y += sw_isr_table.o
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@ -1,59 +0,0 @@
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/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ISR table for static ISR declarations for XTENSA
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*
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* Software ISR table for XTENSA
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*/
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#include <toolchain.h>
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#include <linker/sections.h>
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#include <arch/cpu.h>
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#include <xtensa/config/core.h>
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/*
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* Xtensa assembly code uses xt_unhandled_interrupt for default IRQ handler.
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*/
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#define _irq_spurious xt_unhandled_interrupt
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/*
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* enable preprocessor features, such
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* as %expr - evaluate the expression and use it as a string
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*/
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.altmacro
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/*
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* Define an ISR table entry
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* Define symbol as weak and give the section .gnu.linkonce.d
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* prefix. This allows linker overload the symbol and the
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* whole section by the one defined by a device driver
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*/
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.macro _isr_table_entry_declare index
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WDATA(_isr_irq\index)
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.section .gnu.linkonce.d.isr_irq\index
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_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
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.endm
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/*
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* Declare the ISR table
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*/
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.macro _isr_table_declare from, to
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counter = \from
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.rept (\to - \from)
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_isr_table_entry_declare %counter
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counter = counter + 1
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.endr
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.endm
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GTEXT(_irq_spurious)
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GDATA(_sw_isr_table)
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.section .isr_irq0
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.align
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_sw_isr_table:
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_isr_table_declare 0 XCHAL_NUM_INTERRUPTS
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@ -14,6 +14,7 @@
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#include "xtensa_rtos.h"
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#include "xtensa_api.h"
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#include <kernel_structs.h>
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#include <sw_isr_table.h>
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#if XCHAL_HAVE_EXCEPTIONS
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@ -21,7 +22,6 @@
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extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
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/*
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* Default handler for unhandled exceptions.
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*/
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#endif
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#if XCHAL_HAVE_INTERRUPTS
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/*
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* Default handler for unhandled interrupts.
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*/
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void xt_unhandled_interrupt(void *arg)
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#if defined(CONFIG_SW_ISR_TABLE) && defined(XCHAL_HAVE_INTERRUPTS)
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void _irq_spurious(void *arg)
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{
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ReservedInterruptHandler((unsigned int)arg);
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CODE_UNREACHABLE;
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}
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#endif /* XCHAL_HAVE_INTERRUPTS */
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#endif
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@ -49,6 +49,9 @@ MEMORY
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srom0_seg : org = 0x50000000, len = 0x300
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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@ -49,6 +49,9 @@ MEMORY
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sram17_seg : org = 0x60000378, len = 0x48
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sram18_seg : org = 0x600003C0, len = 0x40
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sram19_seg : org = 0x60000400, len = 0x3FFFC00
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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@ -46,6 +46,9 @@ MEMORY
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sram20_seg : org = 0x00002500, len = 0x3FFDB00
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srom0_seg : org = 0xFE000000, len = 0x300
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srom1_seg : org = 0xFE000300, len = 0xFFFD00
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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@ -49,6 +49,9 @@ MEMORY
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sram17_seg : org = 0x60000278, len = 0x4
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sram18_seg : org = 0x6000027C, len = 0x1C
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sram19_seg : org = 0x60000298, len = 0x3FFFD68
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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@ -34,6 +34,9 @@ MEMORY
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srom0_seg : org = 0x50000000, len = 0x300
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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@ -37,6 +37,9 @@ MEMORY
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drom0_0_seg(R): org = 0x3F400010, len = 0x800000
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rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000
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rtc_slow_seg(RW): org = 0x50000000, len = 0x1000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST(RW): org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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@ -219,4 +222,8 @@ SECTIONS
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_bss_end = ABSOLUTE(.);
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_heap_start = ABSOLUTE(.);
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} GROUP_LINK_IN(RAMABLE_REGION)
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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sram17_seg : org = 0x60000378, len = 0x48
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sram18_seg : org = 0x600003C0, len = 0x40
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sram19_seg : org = 0x60000400, len = 0x3FFFC00
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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sram7_seg : org = 0x600001D8, len = 0x4
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sram8_seg : org = 0x600001DC, len = 0x1C
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sram9_seg : org = 0x600001F8, len = 0x3FFFE08
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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sram7_seg : org = 0x600001D8, len = 0x4
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sram8_seg : org = 0x600001DC, len = 0x1C
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sram9_seg : org = 0x600001F8, len = 0x3FFFE08
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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sram11_seg : org = 0x600002B8, len = 0x48
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sram12_seg : org = 0x60000300, len = 0x40
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sram13_seg : org = 0x60000340, len = 0x3FFCC0
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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iram0_5_seg : org = 0x60020320, len = 0x4
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iram0_6_seg : org = 0x60020324, len = 0x1C
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iram0_7_seg : org = 0x60020340, len = 0x1FCC0
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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iram0_5_seg : org = 0x60020320, len = 0x4
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iram0_6_seg : org = 0x60020324, len = 0x1C
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iram0_7_seg : org = 0x60020340, len = 0x1FCC0
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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srom0_seg : org = 0x50000000, len = 0x300
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srom1_seg : org = 0x50000300, len = 0xFFFD00
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sram0_seg : org = 0x60000000, len = 0x4000000
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#ifdef CONFIG_GEN_ISR_TABLES
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IDT_LIST : org = 0xffffdfff, len = 0x2000
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#endif
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}
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PHDRS
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{
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KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
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}
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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}
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CONFIG_GPIO_ESP32=y
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CONFIG_RANDOM_ESP32_RNG=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER=y
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000
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CONFIG_TOOLCHAIN_VARIANT=""
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_D_108mini=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_D_212GP=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_D_233L=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_XRC_FUSION_AON_ALL_LM=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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@ -4,3 +4,7 @@ CONFIG_XTENSA=y
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CONFIG_SOC_HIFI2_STD=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_SOC_HIFI3_BD5=y
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CONFIG_BOARD_XT_SIM=y
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CONFIG_CONSOLE=y
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CONFIG_SW_ISR_TABLE=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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enum { IRQ = irq_p }; \
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static struct _isr_table_entry \
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_CONCAT(_isr_irq, irq_p) \
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__attribute__ ((used)) \
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__attribute__ ((section(\
|
||||
STRINGIFY(_CONCAT(.gnu.linkonce.d.isr_irq, irq_p)))\
|
||||
)) = {isr_param_p, isr_p}; \
|
||||
_irq_priority_set(irq_p, priority_p, flags_p); \
|
||||
_ISR_DECLARE(irq_p, flags_p, isr_p, isr_param_p); \
|
||||
irq_p; \
|
||||
})
|
||||
|
||||
/* Spurious interrupt handler. Throws an error if called */
|
||||
extern void _irq_spurious(void *unused);
|
||||
|
||||
FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
|
||||
const NANO_ESF *esf);
|
||||
|
|
|
@ -9,6 +9,9 @@
|
|||
#include <xtensa_api.h>
|
||||
#include <xtensa/xtruntime.h>
|
||||
|
||||
#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
|
||||
#define CONFIG_GEN_IRQ_START_VECTOR 0
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief Enable an interrupt line
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue