riscv32: enable gen_isr_tables mechanism
Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
parent
b2e136c5f0
commit
bd69c3bdf0
7 changed files with 36 additions and 104 deletions
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@ -2,14 +2,10 @@ GEN_ISR_TABLE := $(srctree)/arch/common/gen_isr_tables.py
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OUTPUT_SRC := isr_tables.c
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OUTPUT_OBJ := isr_tables.o
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ifeq ($(ARCH),arm)
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OUTPUT_FORMAT := elf32-littlearm
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OUTPUT_ARCH := arm
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else ifeq ($(ARCH),nios2)
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OUTPUT_FORMAT := elf32-littlenios2
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OUTPUT_ARCH := nios2
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ifeq ($(ARCH),riscv32)
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OUTPUT_FORMAT := elf32-littleriscv
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else
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$(error Output formats not defined for this architecture)
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OUTPUT_FORMAT := elf32-little$(ARCH)
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endif
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GEN_ISR_TABLE_EXTRA_ARGS :=
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@ -63,6 +63,13 @@ config RISCV_HAS_CPU_IDLE
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default n
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help
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Does SOC has CPU IDLE instruction
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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endmenu
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source "arch/riscv32/soc/*/Kconfig"
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@ -1,5 +1,5 @@
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ccflags-y += -I$(srctree)/kernel/unified/include
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ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
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obj-y += isr.o reset.o sw_isr_table.o fatal.o irq_manage.o \
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obj-y += isr.o reset.o fatal.o irq_manage.o \
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prep_c.o cpu_idle.o swap.o thread.o irq_offload.o
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@ -1,49 +0,0 @@
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/* sw_isr_table.S - ISR table for static ISR declarations for RISCV32 */
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/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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/*
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* enable preprocessor features, such
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* as %expr - evaluate the expression and use it as a string
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*/
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.altmacro
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/*
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* Define an ISR table entry
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* Define symbol as weak and give the section .gnu.linkonce
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* prefix. This allows linker overload the symbol and the
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* whole section by the one defined by a device driver
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*/
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.macro _isr_table_entry_declare index
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WDATA(_isr_irq\index)
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.section .gnu.linkonce.isr_irq\index
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_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
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.endm
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/*
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* Declare the ISR table
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*/
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.macro _isr_table_declare from, to
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counter = \from
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.rept (\to - \from)
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_isr_table_entry_declare %counter
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counter = counter + 1
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.endr
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.endm
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GTEXT(_irq_spurious)
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GDATA(_sw_isr_table)
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.section .isr_irq0
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.align
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_sw_isr_table:
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_isr_table_declare 0 CONFIG_NUM_IRQS
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@ -56,6 +56,7 @@ extern uint32_t __soc_get_irq(void);
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void _arch_irq_enable(unsigned int irq);
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void _arch_irq_disable(unsigned int irq);
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int _arch_irq_is_enabled(unsigned int irq);
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void _irq_spurious(void *unused);
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/**
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@ -63,20 +64,6 @@ int _arch_irq_is_enabled(unsigned int irq);
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*
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* All arguments must be computable by the compiler at build time.
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*
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* Internally this function does a few things:
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*
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* 1. The enum statement has no effect but forces the compiler to only
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* accept constant values for the irq_p parameter, very important as the
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* numerical IRQ line is used to create a named section.
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*
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* 2. An instance of struct _isr_table_entry is created containing the ISR and
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* its parameter. If you look at how _sw_isr_table is created, each entry in
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* the array is in its own section named by the IRQ line number. What we are
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* doing here is to override one of the default entries (which points to the
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* spurious IRQ handler) with what was supplied here.
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*
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* 3. interrupt priority is not supported by pulpino core
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*
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* @param irq_p IRQ line number
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* @param priority_p Interrupt priority
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* @param isr_p Interrupt service routine
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@ -87,11 +74,7 @@ int _arch_irq_is_enabled(unsigned int irq);
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*/
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#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
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({ \
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enum { IRQ = irq_p }; \
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static struct _isr_table_entry _CONCAT(_isr_irq, irq_p) \
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__attribute__ ((used)) \
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__attribute__ ((section(STRINGIFY(_CONCAT(.gnu.linkonce.isr_irq, irq_p))))) = \
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{isr_param_p, isr_p}; \
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_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
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irq_p; \
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})
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@ -37,6 +37,8 @@ MEMORY
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{
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ROM (rx) : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
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RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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SECTIONS
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@ -69,20 +71,11 @@ SECTIONS
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SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
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{
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. = ALIGN(4);
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KEEP(*(.isr_irq*))
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/* sections for IRQ0-9 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))
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/* sections for IRQ10-99 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))
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/* sections for IRQ100-999 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
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KEEP(*(.openocd_debug))
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KEEP(*(".openocd_debug.*"))
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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KEEP(*(SW_ISR_TABLE))
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#endif
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KEEP(*(.openocd_debug))
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KEEP(*(".openocd_debug.*"))
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_image_text_start = .;
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*(.text)
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@ -160,5 +153,9 @@ SECTIONS
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_image_ram_end = .;
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_end = .; /* end of image */
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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GROUP_END(RAMABLE_REGION)
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}
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@ -33,6 +33,8 @@ MEMORY
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{
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INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE
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DATARAM (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE
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/* Used by and documented in include/linker/intlist.ld */
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IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
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}
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SECTIONS
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@ -80,9 +82,12 @@ SECTIONS
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SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
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{
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. = ALIGN(4);
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*(.rodata)
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*(".rodata.*")
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*(.gnu.linkonce.r.*)
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#ifdef CONFIG_GEN_SW_ISR_TABLE
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KEEP(*(SW_ISR_TABLE))
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#endif
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*(.rodata)
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*(".rodata.*")
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*(.gnu.linkonce.r.*)
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} GROUP_LINK_IN(RAMABLE_REGION)
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#include <linker/common-ram.ld>
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@ -91,17 +96,6 @@ SECTIONS
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{
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. = ALIGN(4);
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KEEP(*(.isr_irq*))
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/* sections for IRQ0-9 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))
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/* sections for IRQ10-99 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))
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/* sections for IRQ100-999 */
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KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
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*(.data)
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*(".data.*")
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@ -142,5 +136,9 @@ SECTIONS
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_end = .; /* end of image */
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#ifdef CONFIG_GEN_ISR_TABLES
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#include <linker/intlist.ld>
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#endif
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GROUP_END(RAMABLE_REGION)
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}
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