arm: exception-assisted kernel panic/oops support
Put the reason code in r0 and make a SVC #2 call, which will be propagated to _fatal_error_handler as an exception. The _is_in_isr() implementation had to be tweaked a bit. User-generated SVC exception no longer just used for irq_offload(); just because we are in it does not mean we are in interrupt context. Instead, have the irq_offload code set and clear the offload_routine global; it will be non-NULL only if it's in use. Upcoming changes to support memory protection (which will require system calls) will need this too. We free up some small amount of ROM deleting _default_esf struct as it's no longer needed. Issue: ZEP-843 Change-Id: Ie82bd708575934cffe41e64f5c128c8704ca4e48 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie
Anas Nashif
parent
7827b7bf4a
commit
75caa2b084
6 changed files with 60 additions and 38 deletions
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@ -19,28 +19,6 @@
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#include <kernel_structs.h>
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#include <misc/printk.h>
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/*
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* Define a default ESF for use with _NanoFatalErrorHandler() in the event
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* the caller does not have a NANO_ESF to pass
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*/
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const NANO_ESF _default_esf = {
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{0xdeaddead}, /* r0/a1 */
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{0xdeaddead}, /* r1/a2 */
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{0xdeaddead}, /* r2/a3 */
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{0xdeaddead}, /* r3/a4 */
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{0xdeaddead}, /* r12/ip */
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{0xdeaddead}, /* r14/lr */
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{0xdeaddead}, /* r15/pc */
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0xdeaddead, /* xpsr */
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#ifdef CONFIG_FLOAT
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{0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead, /* s0 .. s3 */
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0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead, /* s4 .. s7 */
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0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead, /* s8 .. s11 */
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0xdeaddead, 0xdeaddead, 0xdeaddead, 0xdeaddead}, /* s12 .. s15 */
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0xdeaddead, /* fpscr */
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0xdeaddead, /* undefined */
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#endif
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};
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/**
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*
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@ -108,3 +86,8 @@ void _NanoFatalErrorHandler(unsigned int reason,
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_SysFatalErrorHandler(reason, pEsf);
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}
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void _do_kernel_oops(const NANO_ESF *esf)
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{
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_NanoFatalErrorHandler(esf->r0, esf);
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}
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@ -11,7 +11,7 @@
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#include <kernel.h>
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#include <irq_offload.h>
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static irq_offload_routine_t offload_routine;
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volatile irq_offload_routine_t offload_routine;
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static void *offload_param;
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/* Called by __svc */
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@ -28,7 +28,12 @@ void irq_offload(irq_offload_routine_t routine, void *parameter)
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offload_routine = routine;
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offload_param = parameter;
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__asm__ volatile ("svc #1" : : : "memory");
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__asm__ volatile ("svc %[id]"
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:
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: [id] "i" (_SVC_CALL_IRQ_OFFLOAD)
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: "memory");
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offload_routine = NULL;
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irq_unlock(key);
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}
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@ -27,6 +27,7 @@ GTEXT(__svc)
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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GTEXT(__pendsv)
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GTEXT(_do_kernel_oops)
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GDATA(_k_neg_eagain)
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GDATA(_kernel)
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@ -193,32 +194,39 @@ _thread_irq_disabled:
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SECTION_FUNC(TEXT, __svc)
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#if CONFIG_IRQ_OFFLOAD
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tst lr, #0x4 /* did we come from thread mode ? */
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ite eq /* if zero (equal), came from handler mode */
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mrseq r0, MSP /* handler mode, stack frame is on MSP */
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mrsne r0, PSP /* thread mode, stack frame is on PSP */
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ldr r0, [r0, #24] /* grab address of PC from stack frame */
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ldr r1, [r0, #24] /* grab address of PC from stack frame */
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/* SVC is a two-byte instruction, point to it and read encoding */
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ldrh r0, [r0, #-2]
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ldrh r1, [r1, #-2]
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/*
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* grab service call number: if zero, it's a context switch; if not,
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* it's an irq offload
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* grab service call number:
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* 0: context switch
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* 1: irq_offload (if configured)
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* 2: kernel panic or oops (software generated fatal exception)
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* Planned implementation of system calls for memory protection will
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* expand this case.
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*/
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ands r0, #0xff
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ands r1, #0xff
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beq _context_switch
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cmp r1, #2
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beq _oops
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#if CONFIG_IRQ_OFFLOAD
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push {lr}
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blx _irq_do_offload /* call C routine which executes the offload */
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pop {lr}
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/* exception return is done in _IntExit() */
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b _IntExit
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#endif
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_context_switch:
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#endif
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/*
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* Unlock interrupts:
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@ -235,6 +243,12 @@ _context_switch:
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/* handler mode exit, to PendSV */
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bx lr
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_oops:
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push {lr}
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blx _do_kernel_oops
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pop {pc}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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@ -28,14 +28,19 @@ extern "C" {
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#else
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#include <arch/arm/cortex_m/cmsis.h>
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#include <irq_offload.h>
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#ifdef CONFIG_IRQ_OFFLOAD
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extern volatile irq_offload_routine_t offload_routine;
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#endif
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/**
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*
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* @brief Find out if running in an ISR context
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*
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*
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* The current executing vector is found in the IPSR register. We consider the
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* IRQs (exception 16 and up), and the SVC, PendSV, and SYSTICK exceptions,
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* to be interrupts. Taking a fault within an exception is also considered in
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* IRQs (exception 16 and up), and the PendSV and SYSTICK exceptions to be
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* interrupts. Taking a fault within an exception is also considered in
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* interrupt context.
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*
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* @return 1 if in ISR, 0 if not.
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@ -44,8 +49,12 @@ static ALWAYS_INLINE int _IsInIsr(void)
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{
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u32_t vector = _IpsrGet();
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/* IRQs + PendSV (14) + SVC (11) + SYSTICK (15) are interrupts. */
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return (vector > 10)
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/* IRQs + PendSV (14) + SYSTICK (15) are interrupts. */
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return (vector > 13)
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#ifdef CONFIG_IRQ_OFFLOAD
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/* Only non-NULL if currently running an offloaded function */
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|| offload_routine != NULL
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#endif
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#if defined(CONFIG_ARMV6_M)
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/* On ARMv6-M there is no nested execution bit, so we check
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* exception 3, hard fault, to a detect a nested exception.
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@ -32,6 +32,19 @@ extern void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf);
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#define _NANO_ERR_KERNEL_OOPS (4) /* Kernel oops (fatal to thread) */
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#define _NANO_ERR_KERNEL_PANIC (5) /* Kernel panic (fatal to system) */
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#define _SVC_CALL_IRQ_OFFLOAD 1
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#define _SVC_CALL_RUNTIME_EXCEPT 2
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#define _ARCH_EXCEPT(reason_p) do { \
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__asm__ volatile ( \
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"mov r0, %[reason]\n\t" \
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"svc %[id]\n\t" \
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: \
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: [reason] "i" (reason_p), [id] "i" (_SVC_CALL_RUNTIME_EXCEPT) \
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: "memory"); \
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CODE_UNREACHABLE; \
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} while (0)
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#ifdef __cplusplus
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}
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#endif
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@ -63,8 +63,6 @@ struct __esf {
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typedef struct __esf NANO_ESF;
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extern const NANO_ESF _default_esf;
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extern void _ExcExit(void);
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/**
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