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arm: cmsis: Convert enable_floating_point to use CMSIS

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As a first step towards removing the custom ARM Cortex-M Core code
present in Zephyr in benefit of using CMSIS, this change replaces
the use of the custom core code with CMSIS macros in
enable_floating_point().

Jira: ZEP-1568

Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Carles Cufi 2017-01-11 17:46:38 +01:00 • committed by Kumar Gala
commit 88bbd6ccb1
2 changed files with 19 additions and 5 deletions
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8
arch/arm/core/cortex_m/prep_c.c
View file

@ -21,6 +21,7 @@
#include <toolchain.h>
#include <linker-defs.h>
#include <nano_internal.h>
#include <arch/arm/cortex_m/cmsis.h>
#ifdef CONFIG_ARMV6_M
static inline void relocate_vector_table(void) { /* do nothing */ }
@ -50,17 +51,14 @@ static inline void enable_floating_point(void)
* Upon reset, the Co-Processor Access Control Register is 0x00000000.
* Enable CP10 and CP11 coprocessors to enable floating point.
*/
__scs.cpacr.val = (_SCS_CPACR_CP10_FULL_ACCESS |
_SCS_CPACR_CP11_FULL_ACCESS);
SCB->CPACR |= CPACR_CP10_FULL_ACCESS | CPACR_CP11_FULL_ACCESS;
/*
* Upon reset, the FPU Context Control Register is 0xC0000000
* (both Automatic and Lazy state preservation is enabled).
* Disable lazy state preservation so the volatile FP registers are
* always saved on exception.
*/
__scs.fpu.ccr.val = (_SCS_FPU_CCR_ASPEN_ENABLE |
_SCS_FPU_CCR_LSPEN_DISABLE);
FPU->FPCCR = FPU_FPCCR_ASPEN_Msk; /* FPU_FPCCR_LSPEN = 0 */
/*
* Although automatic state preservation is enabled, the processor

16
include/arch/arm/cortex_m/cmsis.h
View file

@ -20,6 +20,22 @@ extern "C" {
#include <soc.h>
/* CP10 Access Bits */
#define CPACR_CP10_Pos 20U
#define CPACR_CP10_Msk (3UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_NO_ACCESS (0UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_PRIV_ACCESS (1UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_RESERVED (2UL << _SCS_CPACR_CP10_Pos)
#define CPACR_CP10_FULL_ACCESS (3UL << _SCS_CPACR_CP10_Pos)
/* CP11 Access Bits */
#define CPACR_CP11_Pos 22U
#define CPACR_CP11_Msk (3UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_NO_ACCESS (0UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_PRIV_ACCESS (1UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_RESERVED (2UL << _SCS_CPACR_CP11_Pos)
#define CPACR_CP11_FULL_ACCESS (3UL << _SCS_CPACR_CP11_Pos)
/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
* Use __NVIC_PRIO_BITS as it is required and simple to check, but
* ultimately all SoCs will define their own CMSIS types and constants.