arm: cmsis: Convert enable_floating_point to use CMSIS
As a first step towards removing the custom ARM Cortex-M Core code present in Zephyr in benefit of using CMSIS, this change replaces the use of the custom core code with CMSIS macros in enable_floating_point(). Jira: ZEP-1568 Change-id: I544a712bf169358c826a3b2acd032c6b30b2801b Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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2 changed files with 19 additions and 5 deletions
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@ -21,6 +21,7 @@
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#include <toolchain.h>
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#include <linker-defs.h>
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#include <nano_internal.h>
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#include <arch/arm/cortex_m/cmsis.h>
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#ifdef CONFIG_ARMV6_M
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static inline void relocate_vector_table(void) { /* do nothing */ }
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@ -50,17 +51,14 @@ static inline void enable_floating_point(void)
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* Upon reset, the Co-Processor Access Control Register is 0x00000000.
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* Enable CP10 and CP11 coprocessors to enable floating point.
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*/
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__scs.cpacr.val = (_SCS_CPACR_CP10_FULL_ACCESS |
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_SCS_CPACR_CP11_FULL_ACCESS);
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SCB->CPACR |= CPACR_CP10_FULL_ACCESS | CPACR_CP11_FULL_ACCESS;
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/*
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* Upon reset, the FPU Context Control Register is 0xC0000000
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* (both Automatic and Lazy state preservation is enabled).
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* Disable lazy state preservation so the volatile FP registers are
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* always saved on exception.
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*/
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__scs.fpu.ccr.val = (_SCS_FPU_CCR_ASPEN_ENABLE |
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_SCS_FPU_CCR_LSPEN_DISABLE);
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FPU->FPCCR = FPU_FPCCR_ASPEN_Msk; /* FPU_FPCCR_LSPEN = 0 */
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/*
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* Although automatic state preservation is enabled, the processor
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@ -20,6 +20,22 @@ extern "C" {
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#include <soc.h>
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/* CP10 Access Bits */
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#define CPACR_CP10_Pos 20U
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#define CPACR_CP10_Msk (3UL << _SCS_CPACR_CP10_Pos)
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#define CPACR_CP10_NO_ACCESS (0UL << _SCS_CPACR_CP10_Pos)
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#define CPACR_CP10_PRIV_ACCESS (1UL << _SCS_CPACR_CP10_Pos)
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#define CPACR_CP10_RESERVED (2UL << _SCS_CPACR_CP10_Pos)
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#define CPACR_CP10_FULL_ACCESS (3UL << _SCS_CPACR_CP10_Pos)
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/* CP11 Access Bits */
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#define CPACR_CP11_Pos 22U
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#define CPACR_CP11_Msk (3UL << _SCS_CPACR_CP11_Pos)
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#define CPACR_CP11_NO_ACCESS (0UL << _SCS_CPACR_CP11_Pos)
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#define CPACR_CP11_PRIV_ACCESS (1UL << _SCS_CPACR_CP11_Pos)
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#define CPACR_CP11_RESERVED (2UL << _SCS_CPACR_CP11_Pos)
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#define CPACR_CP11_FULL_ACCESS (3UL << _SCS_CPACR_CP11_Pos)
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/* Fill in CMSIS required values for non-CMSIS compliant SoCs.
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* Use __NVIC_PRIO_BITS as it is required and simple to check, but
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* ultimately all SoCs will define their own CMSIS types and constants.
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