arm: cmsis: Convert _ScbExcPrioSet to NVIC_SetPriority
Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both interrupt and exception priorities. We don't need to shift around the priority values for NVIC_SetPriority. Jira: ZEP-1568 Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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4 changed files with 10 additions and 61 deletions
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@ -27,6 +27,8 @@ extern "C" {
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#else
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#include <arch/arm/cortex_m/cmsis.h>
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/**
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*
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* @brief Find out if running in an ISR context
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@ -57,6 +59,8 @@ static ALWAYS_INLINE int _IsInIsr(void)
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#endif /* CONFIG_ARMV6_M */
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}
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#define _EXC_SVC_PRIO 0
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#define _EXC_FAULT_PRIO 0
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/**
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* @brief Setup system exceptions
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*
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@ -69,16 +73,16 @@ static ALWAYS_INLINE int _IsInIsr(void)
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*/
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static ALWAYS_INLINE void _ExcSetup(void)
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{
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_ScbExcPrioSet(_EXC_PENDSV, _EXC_PRIO(0xff));
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
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_ScbExcPrioSet(_EXC_SVC, _EXC_PRIO(_EXC_SVC_PRIO));
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NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO);
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#endif
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#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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_ScbExcPrioSet(_EXC_MPU_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
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_ScbExcPrioSet(_EXC_BUS_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
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_ScbExcPrioSet(_EXC_USAGE_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
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NVIC_SetPriority(MemoryManagement_IRQn, _EXC_FAULT_PRIO);
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NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO);
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NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO);
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_ScbUsageFaultEnable();
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_ScbBusFaultEnable();
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@ -537,7 +537,7 @@ int _sys_clock_driver_init(struct device *device)
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#endif /* CONFIG_TICKLESS_IDLE */
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_ScbExcPrioSet(_EXC_SYSTICK, _EXC_IRQ_DEFAULT_PRIO);
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NVIC_SetPriority(SysTick_IRQn, _IRQ_PRIO_OFFSET);
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SysTick->CTRL = ctrl;
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@ -55,26 +55,6 @@ extern "C" {
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#define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(_IRQ_PRIO_OFFSET)
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#define _EXC_SVC_PRIO 0
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#define _EXC_FAULT_PRIO 0
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/* no exc #0 */
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#define _EXC_RESET 1
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#define _EXC_NMI 2
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#define _EXC_HARD_FAULT 3
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#define _EXC_MPU_FAULT 4
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#define _EXC_BUS_FAULT 5
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#define _EXC_USAGE_FAULT 6
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/* 7-10 reserved */
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#define _EXC_SVC 11
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#define _EXC_DEBUG 12
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/* 13 reserved */
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#define _EXC_PENDSV 14
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#define _EXC_SYSTICK 15
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/* 16+ IRQs */
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#define _NUM_EXC 16
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#define NUM_IRQS_PER_REG 32
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#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
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#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
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@ -110,41 +110,6 @@ static inline uint32_t _ScbActiveVectorGet(void)
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return __scs.scb.icsr.bit.vectactive;
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}
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/**
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*
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* @brief Set priority of an exception
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*
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* Only works with exceptions; i.e. do not use this for interrupts, which
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* are exceptions 16+.
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*
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* Note that the processor might not implement all 8 bits, in which case the
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* lower N bits are ignored.
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*
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* ARMv6-M: Exceptions 1 to 3 priorities are fixed (-3, -2, -1) and 4 to 9 are
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* reserved exceptions.
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* ARMv7-M: Exceptions 1 to 3 priorities are fixed (-3, -2, -1).
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*
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* @param exc exception number, 10 to 15 on ARMv6-M and 4 to 15 on ARMv7-M
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* @param pri priority, 0 to 255
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* @return N/A
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*/
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static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
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{
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#if defined(CONFIG_ARMV6_M)
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volatile uint32_t * const shpr = &__scs.scb.shpr[_PRIO_SHP_IDX(exc)];
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__ASSERT((exc > 10) && (exc < 16), "");
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*shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) |
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((uint32_t)pri << _PRIO_BIT_SHIFT(exc)));
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#elif defined(CONFIG_ARMV7_M)
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/* For priority exception handler 4-15 */
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__ASSERT((exc > 3) && (exc < 16), "");
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__scs.scb.shpr[exc - 4] = pri;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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/**
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