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arm: cmsis: Convert _ScbExcPrioSet to NVIC_SetPriority

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Replace _ScbExcPrioSet with calls to NVIC_SetPriority as it handles both
interrupt and exception priorities.  We don't need to shift around the
priority values for NVIC_SetPriority.

Jira: ZEP-1568

Change-Id: Iccd68733c3f7faa82b7ccb17200eef328090b6da
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-01-18 12:28:52 -06:00
commit f85dbb1b34
4 changed files with 10 additions and 61 deletions
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14
arch/arm/include/cortex_m/exc.h
View file

@ -27,6 +27,8 @@ extern "C" {
#else
#include <arch/arm/cortex_m/cmsis.h>
/**
*
* @brief Find out if running in an ISR context
@ -57,6 +59,8 @@ static ALWAYS_INLINE int _IsInIsr(void)
#endif /* CONFIG_ARMV6_M */
}
#define _EXC_SVC_PRIO 0
#define _EXC_FAULT_PRIO 0
/**
* @brief Setup system exceptions
*
@ -69,16 +73,16 @@ static ALWAYS_INLINE int _IsInIsr(void)
*/
static ALWAYS_INLINE void _ExcSetup(void)
{
_ScbExcPrioSet(_EXC_PENDSV, _EXC_PRIO(0xff));
NVIC_SetPriority(PendSV_IRQn, 0xff);
#ifdef CONFIG_CPU_CORTEX_M_HAS_BASEPRI
_ScbExcPrioSet(_EXC_SVC, _EXC_PRIO(_EXC_SVC_PRIO));
NVIC_SetPriority(SVCall_IRQn, _EXC_SVC_PRIO);
#endif
#ifdef CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
_ScbExcPrioSet(_EXC_MPU_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
_ScbExcPrioSet(_EXC_BUS_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
_ScbExcPrioSet(_EXC_USAGE_FAULT, _EXC_PRIO(_EXC_FAULT_PRIO));
NVIC_SetPriority(MemoryManagement_IRQn, _EXC_FAULT_PRIO);
NVIC_SetPriority(BusFault_IRQn, _EXC_FAULT_PRIO);
NVIC_SetPriority(UsageFault_IRQn, _EXC_FAULT_PRIO);
_ScbUsageFaultEnable();
_ScbBusFaultEnable();

2
drivers/timer/cortex_m_systick.c
View file

@ -537,7 +537,7 @@ int _sys_clock_driver_init(struct device *device)
#endif /* CONFIG_TICKLESS_IDLE */
_ScbExcPrioSet(_EXC_SYSTICK, _EXC_IRQ_DEFAULT_PRIO);
NVIC_SetPriority(SysTick_IRQn, _IRQ_PRIO_OFFSET);
SysTick->CTRL = ctrl;

20
include/arch/arm/cortex_m/nvic.h
View file

@ -55,26 +55,6 @@ extern "C" {
#define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(_IRQ_PRIO_OFFSET)
#define _EXC_SVC_PRIO 0
#define _EXC_FAULT_PRIO 0
/* no exc #0 */
#define _EXC_RESET 1
#define _EXC_NMI 2
#define _EXC_HARD_FAULT 3
#define _EXC_MPU_FAULT 4
#define _EXC_BUS_FAULT 5
#define _EXC_USAGE_FAULT 6
/* 7-10 reserved */
#define _EXC_SVC 11
#define _EXC_DEBUG 12
/* 13 reserved */
#define _EXC_PENDSV 14
#define _EXC_SYSTICK 15
/* 16+ IRQs */
#define _NUM_EXC 16
#define NUM_IRQS_PER_REG 32
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)

35
include/arch/arm/cortex_m/scb.h
View file

@ -110,41 +110,6 @@ static inline uint32_t _ScbActiveVectorGet(void)
return __scs.scb.icsr.bit.vectactive;
}
/**
*
* @brief Set priority of an exception
*
* Only works with exceptions; i.e. do not use this for interrupts, which
* are exceptions 16+.
*
* Note that the processor might not implement all 8 bits, in which case the
* lower N bits are ignored.
*
* ARMv6-M: Exceptions 1 to 3 priorities are fixed (-3, -2, -1) and 4 to 9 are
* reserved exceptions.
* ARMv7-M: Exceptions 1 to 3 priorities are fixed (-3, -2, -1).
*
* @param exc exception number, 10 to 15 on ARMv6-M and 4 to 15 on ARMv7-M
* @param pri priority, 0 to 255
* @return N/A
*/
static inline void _ScbExcPrioSet(uint8_t exc, uint8_t pri)
{
#if defined(CONFIG_ARMV6_M)
volatile uint32_t * const shpr = &__scs.scb.shpr[_PRIO_SHP_IDX(exc)];
__ASSERT((exc > 10) && (exc < 16), "");
*shpr = ((*shpr & ~((uint32_t)0xff << _PRIO_BIT_SHIFT(exc))) |
((uint32_t)pri << _PRIO_BIT_SHIFT(exc)));
#elif defined(CONFIG_ARMV7_M)
/* For priority exception handler 4-15 */
__ASSERT((exc > 3) && (exc < 16), "");
__scs.scb.shpr[exc - 4] = pri;
#else
#error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M */
}
#if defined(CONFIG_ARMV6_M)
#elif defined(CONFIG_ARMV7_M)
/**