arm: core: Add MPU parameter to the arm core
This patch add the Memory Protection Unit parameter to the arm core configuration. Change-Id: Ifee8cdd5738391a6f182e8d0382d27eeb8c546ba Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org> Signed-off-by: Marc Moreno <marc.morenoberengue@linaro.org>
This commit is contained in:
Vincenzo Frascino
Kumar Gala
parent
8f6d874f59
commit
0974496d52
2 changed files with 159 additions and 0 deletions
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@ -31,6 +31,13 @@ config CPU_HAS_SYSTICK
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help
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This option is enabled when the CPU has systick timer implemented.
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config CPU_HAS_MPU
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bool
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# Omit prompt to signify "hidden" option
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default n
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help
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This option is enabled when the CPU has a Memory Protection Unit (MPU).
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config CPU_HAS_FPU
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# Hidden config selected by CPU family
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bool
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152
include/arch/arm/cortex_m/mpu/arm_mpu.h
Normal file
152
include/arch/arm/cortex_m/mpu/arm_mpu.h
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@ -0,0 +1,152 @@
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/*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ARM_MPU_H_
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#define _ARM_MPU_H_
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struct arm_mpu {
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/* 0xE000ED90 MPU Type Register */
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volatile u32_t type;
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/* 0xE000ED94 MPU Control Register */
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volatile u32_t ctrl;
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/* 0xE000ED98 MPU Region Number Register */
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volatile u32_t rnr;
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/* 0xE000ED9C MPU Region Base Address Register */
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volatile u32_t rbar;
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/* 0xE000EDA0 MPU Region Attribute and Size Register */
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volatile u32_t rasr;
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/* 0xE000EDA4 Alias of RBAR */
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volatile u32_t rbar_a1;
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/* 0xE000EDA8 Alias of RASR */
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volatile u32_t rasr_a1;
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/* 0xE000EDAC Alias of RBAR */
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volatile u32_t rbar_a2;
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/* 0xE000EDB0 Alias of RASR */
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volatile u32_t rasr_a2;
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/* 0xE000EDB4 Alias of RBAR */
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volatile u32_t rbar_a3;
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/* 0xE000EDB8 Alias of RASR */
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volatile u32_t rasr_a3;
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};
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#define ARM_MPU_BASE 0xE000ED90
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#define REGION_VALID (1 << 4)
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/* eXecute Never */
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#define NOT_EXEC (0x1 << 28)
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/* Privileged No Access, Unprivileged No Access */
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#define NO_ACCESS (0x0 << 24)
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/* Privileged No Access, Unprivileged No Access */
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#define P_NA_U_NA (0x0 << 24)
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/* Privileged Read Write, Unprivileged No Access */
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#define P_RW_U_NA (0x1 << 24)
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/* Privileged Read Write, Unprivileged Read Only */
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#define P_RW_U_RO (0x2 << 24)
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/* Privileged Read Write, Unprivileged Read Write */
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#define P_RW_U_RW (0x3 << 24)
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/* Privileged Read Write, Unprivileged Read Write */
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#define FULL_ACCESS (0x3 << 24)
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/* Privileged Read Only, Unprivileged No Access */
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#define P_RO_U_NA (0x5 << 24)
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/* Privileged Read Only, Unprivileged Read Only */
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#define P_RO_U_RO (0x6 << 24)
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/* Privileged Read Only, Unprivileged Read Only */
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#define RO (0x7 << 24)
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#define STRONGLY_ORDERED_SHAREABLE (1 << 18)
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#define DEVICE_SHAREABLE ((1 << 16) | (1 << 18))
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#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE ((1 << 17) | (1 << 18))
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#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE (1 << 17)
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#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE \
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((1 << 17) | (1 << 16) | (1 << 18))
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#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE ((1 << 17) | (1 << 16))
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#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE ((1 << 19) | (1 << 18))
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#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE (1 << 19)
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#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE \
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((1 << 19) | (1 << 17) | (1 << 16) | (1 << 18))
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#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NONSHAREABLE \
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((1 << 19) | (1 << 17) | (1 << 18))
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#define DEVICE_NON_SHAREABLE (2 << 19)
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/* Some helper defines for common regions */
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#define REGION_RAM_ATTR(size) \
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(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \
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NOT_EXEC | size | FULL_ACCESS)
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#define REGION_FLASH_ATTR(size) \
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(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | size | RO)
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#define REGION_PPB_ATTR(size) (STRONGLY_ORDERED_SHAREABLE | size | FULL_ACCESS)
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#define REGION_IO_ATTR(size) (DEVICE_NON_SHAREABLE | size | FULL_ACCESS)
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#define SUB_REGION_0_DISABLED (0x01 << 8)
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#define SUB_REGION_1_DISABLED (0x02 << 8)
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#define SUB_REGION_2_DISABLED (0x04 << 8)
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#define SUB_REGION_3_DISABLED (0x08 << 8)
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#define SUB_REGION_4_DISABLED (0x10 << 8)
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#define SUB_REGION_5_DISABLED (0x20 << 8)
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#define SUB_REGION_6_DISABLED (0x40 << 8)
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#define SUB_REGION_7_DISABLED (0x80 << 8)
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#define REGION_32B (0x04 << 1)
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#define REGION_64B (0x05 << 1)
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#define REGION_128B (0x06 << 1)
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#define REGION_256B (0x07 << 1)
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#define REGION_512B (0x08 << 1)
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#define REGION_1K (0x09 << 1)
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#define REGION_2K (0x0A << 1)
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#define REGION_4K (0x0B << 1)
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#define REGION_8K (0x0C << 1)
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#define REGION_16K (0x0D << 1)
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#define REGION_32K (0x0E << 1)
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#define REGION_64K (0x0F << 1)
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#define REGION_128K (0x10 << 1)
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#define REGION_256K (0x11 << 1)
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#define REGION_512K (0x12 << 1)
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#define REGION_1M (0x13 << 1)
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#define REGION_2M (0x14 << 1)
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#define REGION_4M (0x15 << 1)
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#define REGION_8M (0x16 << 1)
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#define REGION_16M (0x17 << 1)
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#define REGION_32M (0x18 << 1)
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#define REGION_64M (0x19 << 1)
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#define REGION_128M (0x1A << 1)
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#define REGION_256M (0x1B << 1)
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#define REGION_512M (0x1C << 1)
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#define REGION_1G (0x1D << 1)
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#define REGION_2G (0x1E << 1)
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#define REGION_4G (0x1F << 1)
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#define REGION_ENABLE (1 << 0)
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/* Region definition data structure */
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struct arm_mpu_region {
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/* Region Base Address */
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u32_t base;
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/* Region Name */
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const char *name;
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/* Region Attributes */
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u32_t attr;
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};
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#define MPU_REGION_ENTRY(_name, _base, _attr) \
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{\
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.name = _name, \
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.base = _base, \
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.attr = _attr, \
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}
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/* MPU configuration data structure */
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struct arm_mpu_config {
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/* Number of regions */
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u32_t num_regions;
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/* Regions */
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struct arm_mpu_region *mpu_regions;
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};
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/* Reference to the MPU configuration */
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extern struct arm_mpu_config mpu_config;
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#endif /* _ARM_MPU_H_ */
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