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arch: Add support for Cortex-M7 processor

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All M7 features common to M3/M4 are working. New features like Tightly
Coupled Memory (TCM) are not yet supported.

Change-Id: I5f7b292e70843aec415728f24c973bb003014f4b
Jira: ZEP-977
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
This commit is contained in:
Piotr Mienkowski 2016-09-27 11:55:39 +02:00 • committed by Kumar Gala
commit 378fa6598f
3 changed files with 42 additions and 10 deletions
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9
arch/arm/Makefile
View file

@ -14,19 +14,19 @@ cflags-cortex-m3 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m3) \
$(call cc-option,-mthumb -march=armv7-m)
cflags-cortex-m4 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m4) \
$(call cc-option,-mthumb -march=armv7e-m)
cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7)
ifeq ($(CONFIG_FLOAT), y)
ifeq ($(CONFIG_FP_SOFTABI), y)
cflags-cortex-m4 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv4-sp-d16)
cflags-cortex-m7 += $(call cc-option,-mfloat-abi=softfp -mfpu=fpv5-d16)
endif
ifeq ($(CONFIG_FP_HARDABI), y)
cflags-cortex-m4 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv4-sp-d16)
cflags-cortex-m7 += $(call cc-option,-mfloat-abi=hard -mfpu=fpv5-d16)
endif
endif
cflags-cortex-m7 = $(call cc-option,-mabi=aapcs -mthumb -mcpu=cortex-m7) \
$(call cc-option,-mthumb -march=armv7e-m)
aflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
cflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
cxxflags-$(CONFIG_CPU_CORTEX_M0) += $(cflags-cortex-m0)
@ -43,6 +43,9 @@ aflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
cflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
cxxflags-$(CONFIG_CPU_CORTEX_M4) += $(cflags-cortex-m4)
aflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
cflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
cxxflags-$(CONFIG_CPU_CORTEX_M7) += $(cflags-cortex-m7)
KBUILD_AFLAGS += $(aflags-y)
KBUILD_CFLAGS += $(cflags-y)

12
arch/arm/core/cortex_m/Kconfig
View file

@ -91,6 +91,14 @@ config CPU_CORTEX_M4
help
This option signifies the use of a Cortex-M4 CPU
config CPU_CORTEX_M7
bool
# Omit prompt to signify "hidden" option
default n
select ISA_THUMB2
help
This option signifies the use of a Cortex-M7 CPU
menu "ARM Cortex-M options"
depends on CPU_CORTEX_M
@ -181,8 +189,8 @@ config FLASH_BASE_ADDRESS
avoid modifying it via the menu configuration.
endmenu
menu "ARM Cortex-M0/M0+/M3/M4 options"
depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4
menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
depends on CPU_CORTEX_M0_M0PLUS || CPU_CORTEX_M3_M4 || CPU_CORTEX_M7
config IRQ_OFFLOAD
bool "Enable IRQ offload"

31
include/arch/arm/cortex_m/memory_map.h
View file

@ -57,32 +57,53 @@
/* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS) || defined(CONFIG_CPU_CORTEX_M3_M4)
/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
/* 0xe0000000 -> 0xe003ffff: internal [256KB] */
#define _PPB_INT_BASE_ADDR 0xE0000000
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#define _PPB_INT_RSVD_0 0xE0000000
#define _PPB_INT_DWT 0xE0001000
#define _PPB_INT_BPU 0xE0002000
#define _PPB_INT_RSVD_1 0xE0003000
#define _PPB_INT_SCS 0xE000E000
#define _PPB_INT_RSVD_2 0xE000F000
#elif defined(CONFIG_CPU_CORTEX_M3_M4) || defined(CONFIG_CPU_CORTEX_M7)
#define _PPB_INT_ITM 0xE0000000
#define _PPB_INT_DWT 0xE0001000
#define _PPB_INT_FPB 0xE0002000
#define _PPB_INT_RSVD_1 0xE0003000
#define _PPB_INT_SCS 0xE000E000
#define _PPB_INT_RSVD_2 0xE000F000
#else
#error Unknown CPU
#endif
#define _PPB_INT_END_ADDR 0xE003FFFF
/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
/* 0xe0040000 -> 0xe00fffff: external [768K] */
#define _PPB_EXT_BASE_ADDR 0xE0040000
#if defined(CONFIG_CPU_CORTEX_M0_M0PLUS)
#elif defined(CONFIG_CPU_CORTEX_M3_M4)
#define _PPB_EXT_TPIU 0xE0040000
#define _PPB_EXT_ETM 0xE0041000
#define _PPB_EXT_PPB 0xE0042000
#define _PPB_EXT_ROM_TABLE 0xE00FF000
#define _PPB_EXT_END_ADDR 0xE00FFFFF
#elif defined(CONFIG_CPU_CORTEX_M7)
#define _PPB_EXT_BASE_ADDR 0xE0040000
#define _PPB_EXT_RSVD_TPIU 0xE0040000
#define _PPB_EXT_ETM 0xE0041000
#define _PPB_EXT_CTI 0xE0042000
#define _PPB_EXT_PPB 0xE0043000
#define _PPB_EXT_PROC_ROM_TABLE 0xE00FE000
#define _PPB_EXT_PPB_ROM_TABLE 0xE00FF000
#else
#error Unknown CPU
#endif
#define _PPB_EXT_END_ADDR 0xE00FFFFF
/* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB] */
#define _VENDOR_BASE_ADDR 0xE0100000
#define _VENDOR_END_ADDR 0xFFFFFFFF
#else
#error Unknown CPU
#endif
#endif /* _CORTEXM_MEMORY_MAP__H_ */